Annotation of qemu/cris-dis.c, revision 1.1.1.3

1.1       root        1: /* Disassembler code for CRIS.
                      2:    Copyright 2000, 2001, 2002, 2004, 2005, 2006 Free Software Foundation, Inc.
                      3:    Contributed by Axis Communications AB, Lund, Sweden.
                      4:    Written by Hans-Peter Nilsson.
                      5: 
                      6:    This file is part of the GNU binutils and GDB, the GNU debugger.
                      7: 
                      8:    This program is free software; you can redistribute it and/or modify it
                      9:    under the terms of the GNU General Public License as published by the
                     10:    Free Software Foundation; either version 2, or (at your option) any later
                     11:    version.
                     12: 
                     13:    This program is distributed in the hope that it will be useful, but WITHOUT
                     14:    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
                     15:    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
                     16:    more details.
                     17: 
                     18:    You should have received a copy of the GNU General Public License
1.1.1.3 ! root       19:    along with this program; if not, see <http://www.gnu.org/licenses/>. */
1.1       root       20: 
                     21: #include "dis-asm.h"
                     22: //#include "sysdep.h"
                     23: #include "target-cris/opcode-cris.h"
                     24: //#include "libiberty.h"
                     25: 
                     26: 
1.1.1.2   root       27: void *qemu_malloc(size_t len); /* can't include qemu-common.h here */
                     28: 
1.1       root       29: #define FALSE 0
                     30: #define TRUE 1
                     31: #define CONST_STRNEQ(STR1,STR2) (strncmp ((STR1), (STR2), sizeof (STR2) - 1) == 0)
                     32: 
                     33: /* cris-opc.c -- Table of opcodes for the CRIS processor.
                     34:    Copyright 2000, 2001, 2004 Free Software Foundation, Inc.
                     35:    Contributed by Axis Communications AB, Lund, Sweden.
                     36:    Originally written for GAS 1.38.1 by Mikael Asker.
                     37:    Reorganized by Hans-Peter Nilsson.
                     38: 
                     39: This file is part of GAS, GDB and the GNU binutils.
                     40: 
                     41: GAS, GDB, and GNU binutils is free software; you can redistribute it
                     42: and/or modify it under the terms of the GNU General Public License as
                     43: published by the Free Software Foundation; either version 2, or (at your
                     44: option) any later version.
                     45: 
                     46: GAS, GDB, and GNU binutils are distributed in the hope that they will be
                     47: useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
                     48: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
                     49: GNU General Public License for more details.
                     50: 
                     51: You should have received a copy of the GNU General Public License
1.1.1.3 ! root       52: along with this program; if not, see <http://www.gnu.org/licenses/>.  */
1.1       root       53: 
                     54: #ifndef NULL
                     55: #define NULL (0)
                     56: #endif
                     57: 
                     58: /* This table isn't used for CRISv32 and the size of immediate operands.  */
                     59: const struct cris_spec_reg
                     60: cris_spec_regs[] =
                     61: {
                     62:   {"bz",  0,  1, cris_ver_v32p,           NULL},
                     63:   {"p0",  0,  1, 0,               NULL},
                     64:   {"vr",  1,  1, 0,               NULL},
                     65:   {"p1",  1,  1, 0,               NULL},
                     66:   {"pid", 2,  1, cris_ver_v32p,    NULL},
                     67:   {"p2",  2,  1, cris_ver_v32p,           NULL},
                     68:   {"p2",  2,  1, cris_ver_warning, NULL},
                     69:   {"srs", 3,  1, cris_ver_v32p,    NULL},
                     70:   {"p3",  3,  1, cris_ver_v32p,           NULL},
                     71:   {"p3",  3,  1, cris_ver_warning, NULL},
                     72:   {"wz",  4,  2, cris_ver_v32p,           NULL},
                     73:   {"p4",  4,  2, 0,               NULL},
                     74:   {"ccr", 5,  2, cris_ver_v0_10,   NULL},
                     75:   {"exs", 5,  4, cris_ver_v32p,           NULL},
                     76:   {"p5",  5,  2, cris_ver_v0_10,   NULL},
                     77:   {"p5",  5,  4, cris_ver_v32p,           NULL},
                     78:   {"dcr0",6,  2, cris_ver_v0_3,           NULL},
                     79:   {"eda", 6,  4, cris_ver_v32p,           NULL},
                     80:   {"p6",  6,  2, cris_ver_v0_3,           NULL},
                     81:   {"p6",  6,  4, cris_ver_v32p,           NULL},
                     82:   {"dcr1/mof", 7, 4, cris_ver_v10p,
                     83:    "Register `dcr1/mof' with ambiguous size specified.  Guessing 4 bytes"},
                     84:   {"dcr1/mof", 7, 2, cris_ver_v0_3,
                     85:    "Register `dcr1/mof' with ambiguous size specified.  Guessing 2 bytes"},
                     86:   {"mof", 7,  4, cris_ver_v10p,           NULL},
                     87:   {"dcr1",7,  2, cris_ver_v0_3,           NULL},
                     88:   {"p7",  7,  4, cris_ver_v10p,           NULL},
                     89:   {"p7",  7,  2, cris_ver_v0_3,           NULL},
                     90:   {"dz",  8,  4, cris_ver_v32p,           NULL},
                     91:   {"p8",  8,  4, 0,               NULL},
                     92:   {"ibr", 9,  4, cris_ver_v0_10,   NULL},
                     93:   {"ebp", 9,  4, cris_ver_v32p,           NULL},
                     94:   {"p9",  9,  4, 0,               NULL},
                     95:   {"irp", 10, 4, cris_ver_v0_10,   NULL},
                     96:   {"erp", 10, 4, cris_ver_v32p,           NULL},
                     97:   {"p10", 10, 4, 0,               NULL},
                     98:   {"srp", 11, 4, 0,               NULL},
                     99:   {"p11", 11, 4, 0,               NULL},
                    100:   /* For disassembly use only.  Accept at assembly with a warning.  */
                    101:   {"bar/dtp0", 12, 4, cris_ver_warning,
                    102:    "Ambiguous register `bar/dtp0' specified"},
                    103:   {"nrp", 12, 4, cris_ver_v32p,           NULL},
                    104:   {"bar", 12, 4, cris_ver_v8_10,   NULL},
                    105:   {"dtp0",12, 4, cris_ver_v0_3,           NULL},
                    106:   {"p12", 12, 4, 0,               NULL},
                    107:   /* For disassembly use only.  Accept at assembly with a warning.  */
                    108:   {"dccr/dtp1",13, 4, cris_ver_warning,
                    109:    "Ambiguous register `dccr/dtp1' specified"},
                    110:   {"ccs", 13, 4, cris_ver_v32p,           NULL},
                    111:   {"dccr",13, 4, cris_ver_v8_10,   NULL},
                    112:   {"dtp1",13, 4, cris_ver_v0_3,           NULL},
                    113:   {"p13", 13, 4, 0,               NULL},
                    114:   {"brp", 14, 4, cris_ver_v3_10,   NULL},
                    115:   {"usp", 14, 4, cris_ver_v32p,           NULL},
                    116:   {"p14", 14, 4, cris_ver_v3p,    NULL},
                    117:   {"usp", 15, 4, cris_ver_v10,    NULL},
                    118:   {"spc", 15, 4, cris_ver_v32p,           NULL},
                    119:   {"p15", 15, 4, cris_ver_v10p,           NULL},
                    120:   {NULL, 0, 0, cris_ver_version_all, NULL}
                    121: };
                    122: 
                    123: /* Add version specifiers to this table when necessary.
                    124:    The (now) regular coding of register names suggests a simpler
                    125:    implementation.  */
                    126: const struct cris_support_reg cris_support_regs[] =
                    127: {
                    128:   {"s0", 0},
                    129:   {"s1", 1},
                    130:   {"s2", 2},
                    131:   {"s3", 3},
                    132:   {"s4", 4},
                    133:   {"s5", 5},
                    134:   {"s6", 6},
                    135:   {"s7", 7},
                    136:   {"s8", 8},
                    137:   {"s9", 9},
                    138:   {"s10", 10},
                    139:   {"s11", 11},
                    140:   {"s12", 12},
                    141:   {"s13", 13},
                    142:   {"s14", 14},
                    143:   {"s15", 15},
                    144:   {NULL, 0}
                    145: };
                    146: 
                    147: /* All CRIS opcodes are 16 bits.
                    148: 
                    149:    - The match component is a mask saying which bits must match a
                    150:      particular opcode in order for an instruction to be an instance
                    151:      of that opcode.
                    152: 
                    153:    - The args component is a string containing characters symbolically
                    154:      matching the operands of an instruction.  Used for both assembly
                    155:      and disassembly.
                    156: 
                    157:      Operand-matching characters:
                    158:      [ ] , space
                    159:         Verbatim.
                    160:      A The string "ACR" (case-insensitive).
                    161:      B Not really an operand.  It causes a "BDAP -size,SP" prefix to be
                    162:        output for the PUSH alias-instructions and recognizes a push-
                    163:        prefix at disassembly.  This letter isn't recognized for v32.
                    164:        Must be followed by a R or P letter.
                    165:      ! Non-match pattern, will not match if there's a prefix insn.
                    166:      b Non-matching operand, used for branches with 16-bit
                    167:        displacement. Only recognized by the disassembler.
                    168:      c 5-bit unsigned immediate in bits <4:0>.
                    169:      C 4-bit unsigned immediate in bits <3:0>.
                    170:      d  At assembly, optionally (as in put other cases before this one)
                    171:        ".d" or ".D" at the start of the operands, followed by one space
                    172:        character.  At disassembly, nothing.
                    173:      D General register in bits <15:12> and <3:0>.
                    174:      f List of flags in bits <15:12> and <3:0>.
                    175:      i 6-bit signed immediate in bits <5:0>.
                    176:      I 6-bit unsigned immediate in bits <5:0>.
                    177:      M Size modifier (B, W or D) for CLEAR instructions.
                    178:      m Size modifier (B, W or D) in bits <5:4>
                    179:      N  A 32-bit dword, like in the difference between s and y.
                    180:         This has no effect on bits in the opcode.  Can also be expressed
                    181:        as "[pc+]" in input.
                    182:      n  As N, but PC-relative (to the start of the instruction).
                    183:      o [-128..127] word offset in bits <7:1> and <0>.  Used by 8-bit
                    184:        branch instructions.
                    185:      O [-128..127] offset in bits <7:0>.  Also matches a comma and a
                    186:        general register after the expression, in bits <15:12>.  Used
                    187:        only for the BDAP prefix insn (in v32 the ADDOQ insn; same opcode).
                    188:      P Special register in bits <15:12>.
                    189:      p Indicates that the insn is a prefix insn.  Must be first
                    190:        character.
                    191:      Q  As O, but don't relax; force an 8-bit offset.
                    192:      R General register in bits <15:12>.
                    193:      r General register in bits <3:0>.
                    194:      S Source operand in bit <10> and a prefix; a 3-operand prefix
                    195:        without side-effect.
                    196:      s Source operand in bits <10> and <3:0>, optionally with a
                    197:        side-effect prefix, except [pc] (the name, not R15 as in ACR)
                    198:        isn't allowed for v32 and higher.
                    199:      T  Support register in bits <15:12>.
                    200:      u  4-bit (PC-relative) unsigned immediate word offset in bits <3:0>.
                    201:      U  Relaxes to either u or n, instruction is assumed LAPCQ or LAPC.
                    202:        Not recognized at disassembly.
                    203:      x Register-dot-modifier, for example "r5.w" in bits <15:12> and <5:4>.
                    204:      y Like 's' but do not allow an integer at assembly.
                    205:      Y The difference s-y; only an integer is allowed.
                    206:      z Size modifier (B or W) in bit <4>.  */
                    207: 
                    208: 
                    209: /* Please note the order of the opcodes in this table is significant.
                    210:    The assembler requires that all instances of the same mnemonic must
                    211:    be consecutive.  If they aren't, the assembler might not recognize
                    212:    them, or may indicate an internal error.
                    213: 
                    214:    The disassembler should not normally care about the order of the
                    215:    opcodes, but will prefer an earlier alternative if the "match-score"
                    216:    (see cris-dis.c) is computed as equal.
                    217: 
                    218:    It should not be significant for proper execution that this table is
                    219:    in alphabetical order, but please follow that convention for an easy
                    220:    overview.  */
                    221: 
                    222: const struct cris_opcode
                    223: cris_opcodes[] =
                    224: {
                    225:   {"abs",     0x06B0, 0x0940,            "r,R",     0, SIZE_NONE,     0,
                    226:    cris_abs_op},
                    227: 
                    228:   {"add",     0x0600, 0x09c0,            "m r,R",   0, SIZE_NONE,     0,
                    229:    cris_reg_mode_add_sub_cmp_and_or_move_op},
                    230: 
                    231:   {"add",     0x0A00, 0x01c0,            "m s,R",   0, SIZE_FIELD,    0,
                    232:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
                    233: 
                    234:   {"add",     0x0A00, 0x01c0,            "m S,D",   0, SIZE_NONE,
                    235:    cris_ver_v0_10,
                    236:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
                    237: 
                    238:   {"add",     0x0a00, 0x05c0,            "m S,R,r", 0, SIZE_NONE,
                    239:    cris_ver_v0_10,
                    240:    cris_three_operand_add_sub_cmp_and_or_op},
                    241: 
                    242:   {"add",     0x0A00, 0x01c0,            "m s,R",   0, SIZE_FIELD,
                    243:    cris_ver_v32p,
                    244:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
                    245: 
                    246:   {"addc",    0x0570, 0x0A80,            "r,R",     0, SIZE_FIX_32,
                    247:    cris_ver_v32p,
                    248:    cris_not_implemented_op},
                    249: 
                    250:   {"addc",    0x09A0, 0x0250,            "s,R",     0, SIZE_FIX_32,
                    251:    cris_ver_v32p,
                    252:    cris_not_implemented_op},
                    253: 
                    254:   {"addi",    0x0540, 0x0A80,            "x,r,A",   0, SIZE_NONE,
                    255:    cris_ver_v32p,
                    256:    cris_addi_op},
                    257: 
                    258:   {"addi",    0x0500, 0x0Ac0,            "x,r",     0, SIZE_NONE,     0,
                    259:    cris_addi_op},
                    260: 
                    261:   /* This collates after "addo", but we want to disassemble as "addoq",
                    262:      not "addo".  */
                    263:   {"addoq",   0x0100, 0x0E00,            "Q,A",     0, SIZE_NONE,
                    264:    cris_ver_v32p,
                    265:    cris_not_implemented_op},
                    266: 
                    267:   {"addo",    0x0940, 0x0280,            "m s,R,A", 0, SIZE_FIELD_SIGNED,
                    268:    cris_ver_v32p,
                    269:    cris_not_implemented_op},
                    270: 
                    271:   /* This must be located after the insn above, lest we misinterpret
                    272:      "addo.b -1,r0,acr" as "addo .b-1,r0,acr".  FIXME: Sounds like a
                    273:      parser bug.  */
                    274:   {"addo",   0x0100, 0x0E00,             "O,A",     0, SIZE_NONE,
                    275:    cris_ver_v32p,
                    276:    cris_not_implemented_op},
                    277: 
                    278:   {"addq",    0x0200, 0x0Dc0,            "I,R",     0, SIZE_NONE,     0,
                    279:    cris_quick_mode_add_sub_op},
                    280: 
                    281:   {"adds",    0x0420, 0x0Bc0,            "z r,R",   0, SIZE_NONE,     0,
                    282:    cris_reg_mode_add_sub_cmp_and_or_move_op},
                    283: 
                    284:   /* FIXME: SIZE_FIELD_SIGNED and all necessary changes.  */
                    285:   {"adds",    0x0820, 0x03c0,            "z s,R",   0, SIZE_FIELD,    0,
                    286:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
                    287: 
                    288:   {"adds",    0x0820, 0x03c0,            "z S,D",   0, SIZE_NONE,
                    289:    cris_ver_v0_10,
                    290:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
                    291: 
                    292:   {"adds",    0x0820, 0x07c0,            "z S,R,r", 0, SIZE_NONE,
                    293:    cris_ver_v0_10,
                    294:    cris_three_operand_add_sub_cmp_and_or_op},
                    295: 
                    296:   {"addu",    0x0400, 0x0be0,            "z r,R",   0, SIZE_NONE,     0,
                    297:    cris_reg_mode_add_sub_cmp_and_or_move_op},
                    298: 
                    299:   /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes.  */
                    300:   {"addu",    0x0800, 0x03e0,            "z s,R",   0, SIZE_FIELD,    0,
                    301:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
                    302: 
                    303:   {"addu",    0x0800, 0x03e0,            "z S,D",   0, SIZE_NONE,
                    304:    cris_ver_v0_10,
                    305:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
                    306: 
                    307:   {"addu",    0x0800, 0x07e0,            "z S,R,r", 0, SIZE_NONE,
                    308:    cris_ver_v0_10,
                    309:    cris_three_operand_add_sub_cmp_and_or_op},
                    310: 
                    311:   {"and",     0x0700, 0x08C0,            "m r,R",   0, SIZE_NONE,     0,
                    312:    cris_reg_mode_add_sub_cmp_and_or_move_op},
                    313: 
                    314:   {"and",     0x0B00, 0x00C0,            "m s,R",   0, SIZE_FIELD,    0,
                    315:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
                    316: 
                    317:   {"and",     0x0B00, 0x00C0,            "m S,D",   0, SIZE_NONE,
                    318:    cris_ver_v0_10,
                    319:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
                    320: 
                    321:   {"and",     0x0B00, 0x04C0,            "m S,R,r", 0, SIZE_NONE,
                    322:    cris_ver_v0_10,
                    323:    cris_three_operand_add_sub_cmp_and_or_op},
                    324: 
                    325:   {"andq",    0x0300, 0x0CC0,            "i,R",     0, SIZE_NONE,     0,
                    326:    cris_quick_mode_and_cmp_move_or_op},
                    327: 
                    328:   {"asr",     0x0780, 0x0840,            "m r,R",   0, SIZE_NONE,     0,
                    329:    cris_asr_op},
                    330: 
                    331:   {"asrq",    0x03a0, 0x0c40,            "c,R",     0, SIZE_NONE,     0,
                    332:    cris_asrq_op},
                    333: 
                    334:   {"ax",      0x15B0, 0xEA4F,            "",        0, SIZE_NONE,     0,
                    335:    cris_ax_ei_setf_op},
                    336: 
                    337:   /* FIXME: Should use branch #defines.  */
                    338:   {"b",              0x0dff, 0x0200,             "b",       1, SIZE_NONE,     0,
                    339:    cris_sixteen_bit_offset_branch_op},
                    340: 
                    341:   {"ba",
                    342:    BA_QUICK_OPCODE,
                    343:    0x0F00+(0xF-CC_A)*0x1000,             "o",       1, SIZE_NONE,     0,
                    344:    cris_eight_bit_offset_branch_op},
                    345: 
                    346:   /* Needs to come after the usual "ba o", which might be relaxed to
                    347:      this one.  */
                    348:   {"ba",     BA_DWORD_OPCODE,
                    349:    0xffff & (~BA_DWORD_OPCODE),                  "n",       0, SIZE_FIX_32,
                    350:    cris_ver_v32p,
                    351:    cris_none_reg_mode_jump_op},
                    352: 
                    353:   {"bas",     0x0EBF, 0x0140,            "n,P",     0, SIZE_FIX_32,
                    354:    cris_ver_v32p,
                    355:    cris_none_reg_mode_jump_op},
                    356: 
                    357:   {"basc",     0x0EFF, 0x0100,           "n,P",     0, SIZE_FIX_32,
                    358:    cris_ver_v32p,
                    359:    cris_none_reg_mode_jump_op},
                    360: 
                    361:   {"bcc",
                    362:    BRANCH_QUICK_OPCODE+CC_CC*0x1000,
                    363:    0x0f00+(0xF-CC_CC)*0x1000,            "o",       1, SIZE_NONE,     0,
                    364:    cris_eight_bit_offset_branch_op},
                    365: 
                    366:   {"bcs",
                    367:    BRANCH_QUICK_OPCODE+CC_CS*0x1000,
                    368:    0x0f00+(0xF-CC_CS)*0x1000,            "o",       1, SIZE_NONE,     0,
                    369:    cris_eight_bit_offset_branch_op},
                    370: 
                    371:   {"bdap",
                    372:    BDAP_INDIR_OPCODE, BDAP_INDIR_Z_BITS,  "pm s,R",  0, SIZE_FIELD_SIGNED,
                    373:    cris_ver_v0_10,
                    374:    cris_bdap_prefix},
                    375: 
                    376:   {"bdap",
                    377:    BDAP_QUICK_OPCODE, BDAP_QUICK_Z_BITS,  "pO",             0, SIZE_NONE,
                    378:    cris_ver_v0_10,
                    379:    cris_quick_mode_bdap_prefix},
                    380: 
                    381:   {"beq",
                    382:    BRANCH_QUICK_OPCODE+CC_EQ*0x1000,
                    383:    0x0f00+(0xF-CC_EQ)*0x1000,            "o",       1, SIZE_NONE,     0,
                    384:    cris_eight_bit_offset_branch_op},
                    385: 
                    386:   /* This is deliberately put before "bext" to trump it, even though not
                    387:      in alphabetical order, since we don't do excluding version checks
                    388:      for v0..v10.  */
                    389:   {"bwf",
                    390:    BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
                    391:    0x0f00+(0xF-CC_EXT)*0x1000,           "o",       1, SIZE_NONE,
                    392:    cris_ver_v10,
                    393:    cris_eight_bit_offset_branch_op},
                    394: 
                    395:   {"bext",
                    396:    BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
                    397:    0x0f00+(0xF-CC_EXT)*0x1000,           "o",       1, SIZE_NONE,
                    398:    cris_ver_v0_3,
                    399:    cris_eight_bit_offset_branch_op},
                    400: 
                    401:   {"bge",
                    402:    BRANCH_QUICK_OPCODE+CC_GE*0x1000,
                    403:    0x0f00+(0xF-CC_GE)*0x1000,            "o",       1, SIZE_NONE,     0,
                    404:    cris_eight_bit_offset_branch_op},
                    405: 
                    406:   {"bgt",
                    407:    BRANCH_QUICK_OPCODE+CC_GT*0x1000,
                    408:    0x0f00+(0xF-CC_GT)*0x1000,            "o",       1, SIZE_NONE,     0,
                    409:    cris_eight_bit_offset_branch_op},
                    410: 
                    411:   {"bhi",
                    412:    BRANCH_QUICK_OPCODE+CC_HI*0x1000,
                    413:    0x0f00+(0xF-CC_HI)*0x1000,            "o",       1, SIZE_NONE,     0,
                    414:    cris_eight_bit_offset_branch_op},
                    415: 
                    416:   {"bhs",
                    417:    BRANCH_QUICK_OPCODE+CC_HS*0x1000,
                    418:    0x0f00+(0xF-CC_HS)*0x1000,            "o",       1, SIZE_NONE,     0,
                    419:    cris_eight_bit_offset_branch_op},
                    420: 
                    421:   {"biap", BIAP_OPCODE, BIAP_Z_BITS,     "pm r,R",  0, SIZE_NONE,
                    422:    cris_ver_v0_10,
                    423:    cris_biap_prefix},
                    424: 
                    425:   {"ble",
                    426:    BRANCH_QUICK_OPCODE+CC_LE*0x1000,
                    427:    0x0f00+(0xF-CC_LE)*0x1000,            "o",       1, SIZE_NONE,     0,
                    428:    cris_eight_bit_offset_branch_op},
                    429: 
                    430:   {"blo",
                    431:    BRANCH_QUICK_OPCODE+CC_LO*0x1000,
                    432:    0x0f00+(0xF-CC_LO)*0x1000,            "o",       1, SIZE_NONE,     0,
                    433:    cris_eight_bit_offset_branch_op},
                    434: 
                    435:   {"bls",
                    436:    BRANCH_QUICK_OPCODE+CC_LS*0x1000,
                    437:    0x0f00+(0xF-CC_LS)*0x1000,            "o",       1, SIZE_NONE,     0,
                    438:    cris_eight_bit_offset_branch_op},
                    439: 
                    440:   {"blt",
                    441:    BRANCH_QUICK_OPCODE+CC_LT*0x1000,
                    442:    0x0f00+(0xF-CC_LT)*0x1000,            "o",       1, SIZE_NONE,     0,
                    443:    cris_eight_bit_offset_branch_op},
                    444: 
                    445:   {"bmi",
                    446:    BRANCH_QUICK_OPCODE+CC_MI*0x1000,
                    447:    0x0f00+(0xF-CC_MI)*0x1000,            "o",       1, SIZE_NONE,     0,
                    448:    cris_eight_bit_offset_branch_op},
                    449: 
                    450:   {"bmod",    0x0ab0, 0x0140,            "s,R",     0, SIZE_FIX_32,
                    451:    cris_ver_sim_v0_10,
                    452:    cris_not_implemented_op},
                    453: 
                    454:   {"bmod",    0x0ab0, 0x0140,            "S,D",     0, SIZE_NONE,
                    455:    cris_ver_sim_v0_10,
                    456:    cris_not_implemented_op},
                    457: 
                    458:   {"bmod",    0x0ab0, 0x0540,            "S,R,r",   0, SIZE_NONE,
                    459:    cris_ver_sim_v0_10,
                    460:    cris_not_implemented_op},
                    461: 
                    462:   {"bne",
                    463:    BRANCH_QUICK_OPCODE+CC_NE*0x1000,
                    464:    0x0f00+(0xF-CC_NE)*0x1000,            "o",       1, SIZE_NONE,     0,
                    465:    cris_eight_bit_offset_branch_op},
                    466: 
                    467:   {"bound",   0x05c0, 0x0A00,            "m r,R",   0, SIZE_NONE,     0,
                    468:    cris_two_operand_bound_op},
                    469:   /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes.  */
                    470:   {"bound",   0x09c0, 0x0200,            "m s,R",   0, SIZE_FIELD,
                    471:    cris_ver_v0_10,
                    472:    cris_two_operand_bound_op},
                    473:   /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes.  */
                    474:   {"bound",   0x0dcf, 0x0200,            "m Y,R",   0, SIZE_FIELD,    0,
                    475:    cris_two_operand_bound_op},
                    476:   {"bound",   0x09c0, 0x0200,            "m S,D",   0, SIZE_NONE,
                    477:    cris_ver_v0_10,
                    478:    cris_two_operand_bound_op},
                    479:   {"bound",   0x09c0, 0x0600,            "m S,R,r", 0, SIZE_NONE,
                    480:    cris_ver_v0_10,
                    481:    cris_three_operand_bound_op},
                    482: 
                    483:   {"bpl",
                    484:    BRANCH_QUICK_OPCODE+CC_PL*0x1000,
                    485:    0x0f00+(0xF-CC_PL)*0x1000,            "o",       1, SIZE_NONE,     0,
                    486:    cris_eight_bit_offset_branch_op},
                    487: 
                    488:   {"break",   0xe930, 0x16c0,            "C",       0, SIZE_NONE,
                    489:    cris_ver_v3p,
                    490:    cris_break_op},
                    491: 
                    492:   {"bsb",
                    493:    BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
                    494:    0x0f00+(0xF-CC_EXT)*0x1000,           "o",       1, SIZE_NONE,
                    495:    cris_ver_v32p,
                    496:    cris_eight_bit_offset_branch_op},
                    497: 
                    498:   {"bsr",     0xBEBF, 0x4140,            "n",       0, SIZE_FIX_32,
                    499:    cris_ver_v32p,
                    500:    cris_none_reg_mode_jump_op},
                    501: 
                    502:   {"bsrc",     0xBEFF, 0x4100,           "n",       0, SIZE_FIX_32,
                    503:    cris_ver_v32p,
                    504:    cris_none_reg_mode_jump_op},
                    505: 
                    506:   {"bstore",  0x0af0, 0x0100,            "s,R",     0, SIZE_FIX_32,
                    507:    cris_ver_warning,
                    508:    cris_not_implemented_op},
                    509: 
                    510:   {"bstore",  0x0af0, 0x0100,            "S,D",     0, SIZE_NONE,
                    511:    cris_ver_warning,
                    512:    cris_not_implemented_op},
                    513: 
                    514:   {"bstore",  0x0af0, 0x0500,            "S,R,r",   0, SIZE_NONE,
                    515:    cris_ver_warning,
                    516:    cris_not_implemented_op},
                    517: 
                    518:   {"btst",    0x04F0, 0x0B00,            "r,R",     0, SIZE_NONE,     0,
                    519:    cris_btst_nop_op},
                    520:   {"btstq",   0x0380, 0x0C60,            "c,R",     0, SIZE_NONE,     0,
                    521:    cris_btst_nop_op},
                    522: 
                    523:   {"bvc",
                    524:    BRANCH_QUICK_OPCODE+CC_VC*0x1000,
                    525:    0x0f00+(0xF-CC_VC)*0x1000,            "o",       1, SIZE_NONE,     0,
                    526:    cris_eight_bit_offset_branch_op},
                    527: 
                    528:   {"bvs",
                    529:    BRANCH_QUICK_OPCODE+CC_VS*0x1000,
                    530:    0x0f00+(0xF-CC_VS)*0x1000,            "o",       1, SIZE_NONE,     0,
                    531:    cris_eight_bit_offset_branch_op},
                    532: 
                    533:   {"clear",   0x0670, 0x3980,            "M r",     0, SIZE_NONE,     0,
                    534:    cris_reg_mode_clear_op},
                    535: 
                    536:   {"clear",   0x0A70, 0x3180,            "M y",     0, SIZE_NONE,     0,
                    537:    cris_none_reg_mode_clear_test_op},
                    538: 
                    539:   {"clear",   0x0A70, 0x3180,            "M S",     0, SIZE_NONE,
                    540:    cris_ver_v0_10,
                    541:    cris_none_reg_mode_clear_test_op},
                    542: 
                    543:   {"clearf",  0x05F0, 0x0A00,            "f",       0, SIZE_NONE,     0,
                    544:    cris_clearf_di_op},
                    545: 
                    546:   {"cmp",     0x06C0, 0x0900,            "m r,R",   0, SIZE_NONE,     0,
                    547:    cris_reg_mode_add_sub_cmp_and_or_move_op},
                    548: 
                    549:   {"cmp",     0x0Ac0, 0x0100,            "m s,R",   0, SIZE_FIELD,    0,
                    550:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
                    551: 
                    552:   {"cmp",     0x0Ac0, 0x0100,            "m S,D",   0, SIZE_NONE,
                    553:    cris_ver_v0_10,
                    554:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
                    555: 
                    556:   {"cmpq",    0x02C0, 0x0D00,            "i,R",     0, SIZE_NONE,     0,
                    557:    cris_quick_mode_and_cmp_move_or_op},
                    558: 
                    559:   /* FIXME: SIZE_FIELD_SIGNED and all necessary changes.  */
                    560:   {"cmps",    0x08e0, 0x0300,            "z s,R",   0, SIZE_FIELD,    0,
                    561:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
                    562: 
                    563:   {"cmps",    0x08e0, 0x0300,            "z S,D",   0, SIZE_NONE,
                    564:    cris_ver_v0_10,
                    565:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
                    566: 
                    567:   /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes.  */
                    568:   {"cmpu",    0x08c0, 0x0320,            "z s,R" ,  0, SIZE_FIELD,    0,
                    569:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
                    570: 
                    571:   {"cmpu",    0x08c0, 0x0320,            "z S,D",   0, SIZE_NONE,
                    572:    cris_ver_v0_10,
                    573:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
                    574: 
                    575:   {"di",      0x25F0, 0xDA0F,            "",        0, SIZE_NONE,     0,
                    576:    cris_clearf_di_op},
                    577: 
                    578:   {"dip",     DIP_OPCODE, DIP_Z_BITS,    "ps",      0, SIZE_FIX_32,
                    579:    cris_ver_v0_10,
                    580:    cris_dip_prefix},
                    581: 
                    582:   {"div",     0x0980, 0x0640,            "m R,r",   0, SIZE_FIELD,    0,
                    583:    cris_not_implemented_op},
                    584: 
                    585:   {"dstep",   0x06f0, 0x0900,            "r,R",     0, SIZE_NONE,     0,
                    586:    cris_dstep_logshift_mstep_neg_not_op},
                    587: 
                    588:   {"ei",      0x25B0, 0xDA4F,            "",        0, SIZE_NONE,     0,
                    589:    cris_ax_ei_setf_op},
                    590: 
                    591:   {"fidxd",    0x0ab0, 0xf540,           "[r]",     0, SIZE_NONE,
                    592:    cris_ver_v32p,
                    593:    cris_not_implemented_op},
                    594: 
                    595:   {"fidxi",    0x0d30, 0xF2C0,           "[r]",     0, SIZE_NONE,
                    596:    cris_ver_v32p,
                    597:    cris_not_implemented_op},
                    598: 
                    599:   {"ftagd",    0x1AB0, 0xE540,           "[r]",     0, SIZE_NONE,
                    600:    cris_ver_v32p,
                    601:    cris_not_implemented_op},
                    602: 
                    603:   {"ftagi",    0x1D30, 0xE2C0,           "[r]",     0, SIZE_NONE,
                    604:    cris_ver_v32p,
                    605:    cris_not_implemented_op},
                    606: 
                    607:   {"halt",    0xF930, 0x06CF,            "",        0, SIZE_NONE,
                    608:    cris_ver_v32p,
                    609:    cris_not_implemented_op},
                    610: 
                    611:   {"jas",    0x09B0, 0x0640,             "r,P",     0, SIZE_NONE,
                    612:    cris_ver_v32p,
                    613:    cris_reg_mode_jump_op},
                    614: 
                    615:   {"jas",    0x0DBF, 0x0240,             "N,P",     0, SIZE_FIX_32,
                    616:    cris_ver_v32p,
                    617:    cris_reg_mode_jump_op},
                    618: 
                    619:   {"jasc",    0x0B30, 0x04C0,            "r,P",     0, SIZE_NONE,
                    620:    cris_ver_v32p,
                    621:    cris_reg_mode_jump_op},
                    622: 
                    623:   {"jasc",    0x0F3F, 0x00C0,            "N,P",     0, SIZE_FIX_32,
                    624:    cris_ver_v32p,
                    625:    cris_reg_mode_jump_op},
                    626: 
                    627:   {"jbrc",    0x69b0, 0x9640,            "r",       0, SIZE_NONE,
                    628:    cris_ver_v8_10,
                    629:    cris_reg_mode_jump_op},
                    630: 
                    631:   {"jbrc",    0x6930, 0x92c0,            "s",       0, SIZE_FIX_32,
                    632:    cris_ver_v8_10,
                    633:    cris_none_reg_mode_jump_op},
                    634: 
                    635:   {"jbrc",    0x6930, 0x92c0,            "S",       0, SIZE_NONE,
                    636:    cris_ver_v8_10,
                    637:    cris_none_reg_mode_jump_op},
                    638: 
                    639:   {"jir",     0xA9b0, 0x5640,            "r",       0, SIZE_NONE,
                    640:    cris_ver_v8_10,
                    641:    cris_reg_mode_jump_op},
                    642: 
                    643:   {"jir",     0xA930, 0x52c0,            "s",       0, SIZE_FIX_32,
                    644:    cris_ver_v8_10,
                    645:    cris_none_reg_mode_jump_op},
                    646: 
                    647:   {"jir",     0xA930, 0x52c0,            "S",       0, SIZE_NONE,
                    648:    cris_ver_v8_10,
                    649:    cris_none_reg_mode_jump_op},
                    650: 
                    651:   {"jirc",    0x29b0, 0xd640,            "r",       0, SIZE_NONE,
                    652:    cris_ver_v8_10,
                    653:    cris_reg_mode_jump_op},
                    654: 
                    655:   {"jirc",    0x2930, 0xd2c0,            "s",       0, SIZE_FIX_32,
                    656:    cris_ver_v8_10,
                    657:    cris_none_reg_mode_jump_op},
                    658: 
                    659:   {"jirc",    0x2930, 0xd2c0,            "S",       0, SIZE_NONE,
                    660:    cris_ver_v8_10,
                    661:    cris_none_reg_mode_jump_op},
                    662: 
                    663:   {"jsr",     0xB9b0, 0x4640,            "r",       0, SIZE_NONE,     0,
                    664:    cris_reg_mode_jump_op},
                    665: 
                    666:   {"jsr",     0xB930, 0x42c0,            "s",       0, SIZE_FIX_32,
                    667:    cris_ver_v0_10,
                    668:    cris_none_reg_mode_jump_op},
                    669: 
                    670:   {"jsr",     0xBDBF, 0x4240,            "N",       0, SIZE_FIX_32,
                    671:    cris_ver_v32p,
                    672:    cris_none_reg_mode_jump_op},
                    673: 
                    674:   {"jsr",     0xB930, 0x42c0,            "S",       0, SIZE_NONE,
                    675:    cris_ver_v0_10,
                    676:    cris_none_reg_mode_jump_op},
                    677: 
                    678:   {"jsrc",    0x39b0, 0xc640,            "r",       0, SIZE_NONE,
                    679:    cris_ver_v8_10,
                    680:    cris_reg_mode_jump_op},
                    681: 
                    682:   {"jsrc",    0x3930, 0xc2c0,            "s",       0, SIZE_FIX_32,
                    683:    cris_ver_v8_10,
                    684:    cris_none_reg_mode_jump_op},
                    685: 
                    686:   {"jsrc",    0x3930, 0xc2c0,            "S",       0, SIZE_NONE,
                    687:    cris_ver_v8_10,
                    688:    cris_none_reg_mode_jump_op},
                    689: 
                    690:   {"jsrc",    0xBB30, 0x44C0,            "r",       0, SIZE_NONE,
                    691:    cris_ver_v32p,
                    692:    cris_reg_mode_jump_op},
                    693: 
                    694:   {"jsrc",    0xBF3F, 0x40C0,            "N",       0, SIZE_FIX_32,
                    695:    cris_ver_v32p,
                    696:    cris_reg_mode_jump_op},
                    697: 
                    698:   {"jump",    0x09b0, 0xF640,            "r",       0, SIZE_NONE,     0,
                    699:    cris_reg_mode_jump_op},
                    700: 
                    701:   {"jump",
                    702:    JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS,  "s",      0, SIZE_FIX_32,
                    703:    cris_ver_v0_10,
                    704:    cris_none_reg_mode_jump_op},
                    705: 
                    706:   {"jump",
                    707:    JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS,  "S",      0, SIZE_NONE,
                    708:    cris_ver_v0_10,
                    709:    cris_none_reg_mode_jump_op},
                    710: 
                    711:   {"jump",    0x09F0, 0x060F,            "P",       0, SIZE_NONE,
                    712:    cris_ver_v32p,
                    713:    cris_none_reg_mode_jump_op},
                    714: 
                    715:   {"jump",
                    716:    JUMP_PC_INCR_OPCODE_V32,
                    717:    (0xffff & ~JUMP_PC_INCR_OPCODE_V32),          "N",       0, SIZE_FIX_32,
                    718:    cris_ver_v32p,
                    719:    cris_none_reg_mode_jump_op},
                    720: 
                    721:   {"jmpu",    0x8930, 0x72c0,            "s",       0, SIZE_FIX_32,
                    722:    cris_ver_v10,
                    723:    cris_none_reg_mode_jump_op},
                    724: 
                    725:   {"jmpu",    0x8930, 0x72c0,             "S",      0, SIZE_NONE,
                    726:    cris_ver_v10,
                    727:    cris_none_reg_mode_jump_op},
                    728: 
                    729:   {"lapc",    0x0970, 0x0680,            "U,R",    0, SIZE_NONE,
                    730:    cris_ver_v32p,
                    731:    cris_not_implemented_op},
                    732: 
                    733:   {"lapc",    0x0D7F, 0x0280,            "dn,R",    0, SIZE_FIX_32,
                    734:    cris_ver_v32p,
                    735:    cris_not_implemented_op},
                    736: 
                    737:   {"lapcq",   0x0970, 0x0680,            "u,R",     0, SIZE_NONE,
                    738:    cris_ver_v32p,
                    739:    cris_addi_op},
                    740: 
                    741:   {"lsl",     0x04C0, 0x0B00,            "m r,R",   0, SIZE_NONE,     0,
                    742:    cris_dstep_logshift_mstep_neg_not_op},
                    743: 
                    744:   {"lslq",    0x03c0, 0x0C20,            "c,R",     0, SIZE_NONE,     0,
                    745:    cris_dstep_logshift_mstep_neg_not_op},
                    746: 
                    747:   {"lsr",     0x07C0, 0x0800,            "m r,R",   0, SIZE_NONE,     0,
                    748:    cris_dstep_logshift_mstep_neg_not_op},
                    749: 
                    750:   {"lsrq",    0x03e0, 0x0C00,            "c,R",     0, SIZE_NONE,     0,
                    751:    cris_dstep_logshift_mstep_neg_not_op},
                    752: 
                    753:   {"lz",      0x0730, 0x08C0,            "r,R",     0, SIZE_NONE,
                    754:    cris_ver_v3p,
                    755:    cris_not_implemented_op},
                    756: 
                    757:   {"mcp",      0x07f0, 0x0800,           "P,r",     0, SIZE_NONE,
                    758:    cris_ver_v32p,
                    759:    cris_not_implemented_op},
                    760: 
                    761:   {"move",    0x0640, 0x0980,            "m r,R",   0, SIZE_NONE,     0,
                    762:    cris_reg_mode_add_sub_cmp_and_or_move_op},
                    763: 
                    764:   {"move",    0x0A40, 0x0180,            "m s,R",   0, SIZE_FIELD,    0,
                    765:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
                    766: 
                    767:   {"move",    0x0A40, 0x0180,            "m S,D",   0, SIZE_NONE,
                    768:    cris_ver_v0_10,
                    769:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
                    770: 
                    771:   {"move",    0x0630, 0x09c0,            "r,P",     0, SIZE_NONE,     0,
                    772:    cris_move_to_preg_op},
                    773: 
                    774:   {"move",    0x0670, 0x0980,            "P,r",     0, SIZE_NONE,     0,
                    775:    cris_reg_mode_move_from_preg_op},
                    776: 
                    777:   {"move",    0x0BC0, 0x0000,            "m R,y",   0, SIZE_FIELD,    0,
                    778:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
                    779: 
                    780:   {"move",    0x0BC0, 0x0000,            "m D,S",   0, SIZE_NONE,
                    781:    cris_ver_v0_10,
                    782:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
                    783: 
                    784:   {"move",
                    785:    MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS,
                    786:    "s,P",   0, SIZE_SPEC_REG, 0,
                    787:    cris_move_to_preg_op},
                    788: 
                    789:   {"move",    0x0A30, 0x01c0,            "S,P",     0, SIZE_NONE,
                    790:    cris_ver_v0_10,
                    791:    cris_move_to_preg_op},
                    792: 
                    793:   {"move",    0x0A70, 0x0180,            "P,y",     0, SIZE_SPEC_REG, 0,
                    794:    cris_none_reg_mode_move_from_preg_op},
                    795: 
                    796:   {"move",    0x0A70, 0x0180,            "P,S",     0, SIZE_NONE,
                    797:    cris_ver_v0_10,
                    798:    cris_none_reg_mode_move_from_preg_op},
                    799: 
                    800:   {"move",    0x0B70, 0x0480,            "r,T",     0, SIZE_NONE,
                    801:    cris_ver_v32p,
                    802:    cris_not_implemented_op},
                    803: 
                    804:   {"move",    0x0F70, 0x0080,            "T,r",     0, SIZE_NONE,
                    805:    cris_ver_v32p,
                    806:    cris_not_implemented_op},
                    807: 
                    808:   {"movem",   0x0BF0, 0x0000,            "R,y",     0, SIZE_FIX_32,   0,
                    809:    cris_move_reg_to_mem_movem_op},
                    810: 
                    811:   {"movem",   0x0BF0, 0x0000,            "D,S",     0, SIZE_NONE,
                    812:    cris_ver_v0_10,
                    813:    cris_move_reg_to_mem_movem_op},
                    814: 
                    815:   {"movem",   0x0BB0, 0x0040,            "s,R",     0, SIZE_FIX_32,   0,
                    816:    cris_move_mem_to_reg_movem_op},
                    817: 
                    818:   {"movem",   0x0BB0, 0x0040,            "S,D",     0, SIZE_NONE,
                    819:    cris_ver_v0_10,
                    820:    cris_move_mem_to_reg_movem_op},
                    821: 
                    822:   {"moveq",   0x0240, 0x0D80,            "i,R",     0, SIZE_NONE,     0,
                    823:    cris_quick_mode_and_cmp_move_or_op},
                    824: 
                    825:   {"movs",    0x0460, 0x0B80,            "z r,R",   0, SIZE_NONE,     0,
                    826:    cris_reg_mode_add_sub_cmp_and_or_move_op},
                    827: 
                    828:   /* FIXME: SIZE_FIELD_SIGNED and all necessary changes.  */
                    829:   {"movs",    0x0860, 0x0380,            "z s,R",   0, SIZE_FIELD,    0,
                    830:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
                    831: 
                    832:   {"movs",    0x0860, 0x0380,            "z S,D",   0, SIZE_NONE,
                    833:    cris_ver_v0_10,
                    834:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
                    835: 
                    836:   {"movu",    0x0440, 0x0Ba0,            "z r,R",   0, SIZE_NONE,     0,
                    837:    cris_reg_mode_add_sub_cmp_and_or_move_op},
                    838: 
                    839:   /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes.  */
                    840:   {"movu",    0x0840, 0x03a0,            "z s,R",   0, SIZE_FIELD,    0,
                    841:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
                    842: 
                    843:   {"movu",    0x0840, 0x03a0,            "z S,D",   0, SIZE_NONE,
                    844:    cris_ver_v0_10,
                    845:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
                    846: 
                    847:   {"mstep",   0x07f0, 0x0800,            "r,R",     0, SIZE_NONE,
                    848:    cris_ver_v0_10,
                    849:    cris_dstep_logshift_mstep_neg_not_op},
                    850: 
                    851:   {"muls",    0x0d00, 0x02c0,            "m r,R",   0, SIZE_NONE,
                    852:    cris_ver_v10p,
                    853:    cris_muls_op},
                    854: 
                    855:   {"mulu",    0x0900, 0x06c0,            "m r,R",   0, SIZE_NONE,
                    856:    cris_ver_v10p,
                    857:    cris_mulu_op},
                    858: 
                    859:   {"neg",     0x0580, 0x0A40,            "m r,R",   0, SIZE_NONE,     0,
                    860:    cris_dstep_logshift_mstep_neg_not_op},
                    861: 
                    862:   {"nop",     NOP_OPCODE, NOP_Z_BITS,    "",        0, SIZE_NONE,
                    863:    cris_ver_v0_10,
                    864:    cris_btst_nop_op},
                    865: 
                    866:   {"nop",     NOP_OPCODE_V32, NOP_Z_BITS_V32, "",    0, SIZE_NONE,
                    867:    cris_ver_v32p,
                    868:    cris_btst_nop_op},
                    869: 
                    870:   {"not",     0x8770, 0x7880,            "r",       0, SIZE_NONE,     0,
                    871:    cris_dstep_logshift_mstep_neg_not_op},
                    872: 
                    873:   {"or",      0x0740, 0x0880,            "m r,R",   0, SIZE_NONE,     0,
                    874:    cris_reg_mode_add_sub_cmp_and_or_move_op},
                    875: 
                    876:   {"or",      0x0B40, 0x0080,            "m s,R",   0, SIZE_FIELD,    0,
                    877:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
                    878: 
                    879:   {"or",      0x0B40, 0x0080,            "m S,D",   0, SIZE_NONE,
                    880:    cris_ver_v0_10,
                    881:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
                    882: 
                    883:   {"or",      0x0B40, 0x0480,            "m S,R,r", 0, SIZE_NONE,
                    884:    cris_ver_v0_10,
                    885:    cris_three_operand_add_sub_cmp_and_or_op},
                    886: 
                    887:   {"orq",     0x0340, 0x0C80,            "i,R",     0, SIZE_NONE,     0,
                    888:    cris_quick_mode_and_cmp_move_or_op},
                    889: 
                    890:   {"pop",     0x0E6E, 0x0191,            "!R",      0, SIZE_NONE,
                    891:    cris_ver_v0_10,
                    892:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
                    893: 
                    894:   {"pop",     0x0e3e, 0x01c1,            "!P",      0, SIZE_NONE,
                    895:    cris_ver_v0_10,
                    896:    cris_none_reg_mode_move_from_preg_op},
                    897: 
                    898:   {"push",    0x0FEE, 0x0011,            "BR",      0, SIZE_NONE,
                    899:    cris_ver_v0_10,
                    900:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
                    901: 
                    902:   {"push",    0x0E7E, 0x0181,            "BP",      0, SIZE_NONE,
                    903:    cris_ver_v0_10,
                    904:    cris_move_to_preg_op},
                    905: 
                    906:   {"rbf",     0x3b30, 0xc0c0,            "y",       0, SIZE_NONE,
                    907:    cris_ver_v10,
                    908:    cris_not_implemented_op},
                    909: 
                    910:   {"rbf",     0x3b30, 0xc0c0,            "S",       0, SIZE_NONE,
                    911:    cris_ver_v10,
                    912:    cris_not_implemented_op},
                    913: 
                    914:   {"rfe",     0x2930, 0xD6CF,            "",        0, SIZE_NONE,
                    915:    cris_ver_v32p,
                    916:    cris_not_implemented_op},
                    917: 
                    918:   {"rfg",     0x4930, 0xB6CF,            "",        0, SIZE_NONE,
                    919:    cris_ver_v32p,
                    920:    cris_not_implemented_op},
                    921: 
                    922:   {"rfn",     0x5930, 0xA6CF,            "",        0, SIZE_NONE,
                    923:    cris_ver_v32p,
                    924:    cris_not_implemented_op},
                    925: 
                    926:   {"ret",     0xB67F, 0x4980,            "",        1, SIZE_NONE,
                    927:    cris_ver_v0_10,
                    928:    cris_reg_mode_move_from_preg_op},
                    929: 
                    930:   {"ret",     0xB9F0, 0x460F,            "",        1, SIZE_NONE,
                    931:    cris_ver_v32p,
                    932:    cris_reg_mode_move_from_preg_op},
                    933: 
                    934:   {"retb",    0xe67f, 0x1980,            "",        1, SIZE_NONE,
                    935:    cris_ver_v0_10,
                    936:    cris_reg_mode_move_from_preg_op},
                    937: 
                    938:   {"rete",     0xA9F0, 0x560F,           "",        1, SIZE_NONE,
                    939:    cris_ver_v32p,
                    940:    cris_reg_mode_move_from_preg_op},
                    941: 
                    942:   {"reti",    0xA67F, 0x5980,            "",        1, SIZE_NONE,
                    943:    cris_ver_v0_10,
                    944:    cris_reg_mode_move_from_preg_op},
                    945: 
                    946:   {"retn",     0xC9F0, 0x360F,           "",        1, SIZE_NONE,
                    947:    cris_ver_v32p,
                    948:    cris_reg_mode_move_from_preg_op},
                    949: 
                    950:   {"sbfs",    0x3b70, 0xc080,            "y",       0, SIZE_NONE,
                    951:    cris_ver_v10,
                    952:    cris_not_implemented_op},
                    953: 
                    954:   {"sbfs",    0x3b70, 0xc080,            "S",       0, SIZE_NONE,
                    955:    cris_ver_v10,
                    956:    cris_not_implemented_op},
                    957: 
                    958:   {"sa",
                    959:    0x0530+CC_A*0x1000,
                    960:    0x0AC0+(0xf-CC_A)*0x1000,             "r",       0, SIZE_NONE,     0,
                    961:    cris_scc_op},
                    962: 
                    963:   {"ssb",
                    964:    0x0530+CC_EXT*0x1000,
                    965:    0x0AC0+(0xf-CC_EXT)*0x1000,           "r",       0, SIZE_NONE,
                    966:    cris_ver_v32p,
                    967:    cris_scc_op},
                    968: 
                    969:   {"scc",
                    970:    0x0530+CC_CC*0x1000,
                    971:    0x0AC0+(0xf-CC_CC)*0x1000,            "r",       0, SIZE_NONE,     0,
                    972:    cris_scc_op},
                    973: 
                    974:   {"scs",
                    975:    0x0530+CC_CS*0x1000,
                    976:    0x0AC0+(0xf-CC_CS)*0x1000,            "r",       0, SIZE_NONE,     0,
                    977:    cris_scc_op},
                    978: 
                    979:   {"seq",
                    980:    0x0530+CC_EQ*0x1000,
                    981:    0x0AC0+(0xf-CC_EQ)*0x1000,            "r",       0, SIZE_NONE,     0,
                    982:    cris_scc_op},
                    983: 
                    984:   {"setf",    0x05b0, 0x0A40,            "f",       0, SIZE_NONE,     0,
                    985:    cris_ax_ei_setf_op},
                    986: 
                    987:   {"sfe",    0x3930, 0xC6CF,             "",        0, SIZE_NONE,
                    988:    cris_ver_v32p,
                    989:    cris_not_implemented_op},
                    990: 
                    991:   /* Need to have "swf" in front of "sext" so it is the one displayed in
                    992:      disassembly.  */
                    993:   {"swf",
                    994:    0x0530+CC_EXT*0x1000,
                    995:    0x0AC0+(0xf-CC_EXT)*0x1000,           "r",       0, SIZE_NONE,
                    996:    cris_ver_v10,
                    997:    cris_scc_op},
                    998: 
                    999:   {"sext",
                   1000:    0x0530+CC_EXT*0x1000,
                   1001:    0x0AC0+(0xf-CC_EXT)*0x1000,           "r",       0, SIZE_NONE,
                   1002:    cris_ver_v0_3,
                   1003:    cris_scc_op},
                   1004: 
                   1005:   {"sge",
                   1006:    0x0530+CC_GE*0x1000,
                   1007:    0x0AC0+(0xf-CC_GE)*0x1000,            "r",       0, SIZE_NONE,     0,
                   1008:    cris_scc_op},
                   1009: 
                   1010:   {"sgt",
                   1011:    0x0530+CC_GT*0x1000,
                   1012:    0x0AC0+(0xf-CC_GT)*0x1000,            "r",       0, SIZE_NONE,     0,
                   1013:    cris_scc_op},
                   1014: 
                   1015:   {"shi",
                   1016:    0x0530+CC_HI*0x1000,
                   1017:    0x0AC0+(0xf-CC_HI)*0x1000,            "r",       0, SIZE_NONE,     0,
                   1018:    cris_scc_op},
                   1019: 
                   1020:   {"shs",
                   1021:    0x0530+CC_HS*0x1000,
                   1022:    0x0AC0+(0xf-CC_HS)*0x1000,            "r",       0, SIZE_NONE,     0,
                   1023:    cris_scc_op},
                   1024: 
                   1025:   {"sle",
                   1026:    0x0530+CC_LE*0x1000,
                   1027:    0x0AC0+(0xf-CC_LE)*0x1000,            "r",       0, SIZE_NONE,     0,
                   1028:    cris_scc_op},
                   1029: 
                   1030:   {"slo",
                   1031:    0x0530+CC_LO*0x1000,
                   1032:    0x0AC0+(0xf-CC_LO)*0x1000,            "r",       0, SIZE_NONE,     0,
                   1033:    cris_scc_op},
                   1034: 
                   1035:   {"sls",
                   1036:    0x0530+CC_LS*0x1000,
                   1037:    0x0AC0+(0xf-CC_LS)*0x1000,            "r",       0, SIZE_NONE,     0,
                   1038:    cris_scc_op},
                   1039: 
                   1040:   {"slt",
                   1041:    0x0530+CC_LT*0x1000,
                   1042:    0x0AC0+(0xf-CC_LT)*0x1000,            "r",       0, SIZE_NONE,     0,
                   1043:    cris_scc_op},
                   1044: 
                   1045:   {"smi",
                   1046:    0x0530+CC_MI*0x1000,
                   1047:    0x0AC0+(0xf-CC_MI)*0x1000,            "r",       0, SIZE_NONE,     0,
                   1048:    cris_scc_op},
                   1049: 
                   1050:   {"sne",
                   1051:    0x0530+CC_NE*0x1000,
                   1052:    0x0AC0+(0xf-CC_NE)*0x1000,            "r",       0, SIZE_NONE,     0,
                   1053:    cris_scc_op},
                   1054: 
                   1055:   {"spl",
                   1056:    0x0530+CC_PL*0x1000,
                   1057:    0x0AC0+(0xf-CC_PL)*0x1000,            "r",       0, SIZE_NONE,     0,
                   1058:    cris_scc_op},
                   1059: 
                   1060:   {"sub",     0x0680, 0x0940,            "m r,R",   0, SIZE_NONE,     0,
                   1061:    cris_reg_mode_add_sub_cmp_and_or_move_op},
                   1062: 
                   1063:   {"sub",     0x0a80, 0x0140,            "m s,R",   0, SIZE_FIELD,    0,
                   1064:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
                   1065: 
                   1066:   {"sub",     0x0a80, 0x0140,            "m S,D",   0, SIZE_NONE,
                   1067:    cris_ver_v0_10,
                   1068:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
                   1069: 
                   1070:   {"sub",     0x0a80, 0x0540,            "m S,R,r", 0, SIZE_NONE,
                   1071:    cris_ver_v0_10,
                   1072:    cris_three_operand_add_sub_cmp_and_or_op},
                   1073: 
                   1074:   {"subq",    0x0280, 0x0d40,            "I,R",     0, SIZE_NONE,     0,
                   1075:    cris_quick_mode_add_sub_op},
                   1076: 
                   1077:   {"subs",    0x04a0, 0x0b40,            "z r,R",   0, SIZE_NONE,     0,
                   1078:    cris_reg_mode_add_sub_cmp_and_or_move_op},
                   1079: 
                   1080:   /* FIXME: SIZE_FIELD_SIGNED and all necessary changes.  */
                   1081:   {"subs",    0x08a0, 0x0340,            "z s,R",   0, SIZE_FIELD,    0,
                   1082:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
                   1083: 
                   1084:   {"subs",    0x08a0, 0x0340,            "z S,D",   0, SIZE_NONE,
                   1085:    cris_ver_v0_10,
                   1086:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
                   1087: 
                   1088:   {"subs",    0x08a0, 0x0740,            "z S,R,r", 0, SIZE_NONE,
                   1089:    cris_ver_v0_10,
                   1090:    cris_three_operand_add_sub_cmp_and_or_op},
                   1091: 
                   1092:   {"subu",    0x0480, 0x0b60,            "z r,R",   0, SIZE_NONE,     0,
                   1093:    cris_reg_mode_add_sub_cmp_and_or_move_op},
                   1094: 
                   1095:   /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes.  */
                   1096:   {"subu",    0x0880, 0x0360,            "z s,R",   0, SIZE_FIELD,    0,
                   1097:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
                   1098: 
                   1099:   {"subu",    0x0880, 0x0360,            "z S,D",   0, SIZE_NONE,
                   1100:    cris_ver_v0_10,
                   1101:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
                   1102: 
                   1103:   {"subu",    0x0880, 0x0760,            "z S,R,r", 0, SIZE_NONE,
                   1104:    cris_ver_v0_10,
                   1105:    cris_three_operand_add_sub_cmp_and_or_op},
                   1106: 
                   1107:   {"svc",
                   1108:    0x0530+CC_VC*0x1000,
                   1109:    0x0AC0+(0xf-CC_VC)*0x1000,            "r",       0, SIZE_NONE,     0,
                   1110:    cris_scc_op},
                   1111: 
                   1112:   {"svs",
                   1113:    0x0530+CC_VS*0x1000,
                   1114:    0x0AC0+(0xf-CC_VS)*0x1000,            "r",       0, SIZE_NONE,     0,
                   1115:    cris_scc_op},
                   1116: 
                   1117:   /* The insn "swapn" is the same as "not" and will be disassembled as
                   1118:      such, but the swap* family of mnmonics are generally v8-and-higher
                   1119:      only, so count it in.  */
                   1120:   {"swapn",   0x8770, 0x7880,            "r",       0, SIZE_NONE,
                   1121:    cris_ver_v8p,
                   1122:    cris_not_implemented_op},
                   1123: 
                   1124:   {"swapw",   0x4770, 0xb880,            "r",       0, SIZE_NONE,
                   1125:    cris_ver_v8p,
                   1126:    cris_not_implemented_op},
                   1127: 
                   1128:   {"swapnw",  0xc770, 0x3880,            "r",       0, SIZE_NONE,
                   1129:    cris_ver_v8p,
                   1130:    cris_not_implemented_op},
                   1131: 
                   1132:   {"swapb",   0x2770, 0xd880,            "r",       0, SIZE_NONE,
                   1133:    cris_ver_v8p,
                   1134:    cris_not_implemented_op},
                   1135: 
                   1136:   {"swapnb",  0xA770, 0x5880,            "r",       0, SIZE_NONE,
                   1137:    cris_ver_v8p,
                   1138:    cris_not_implemented_op},
                   1139: 
                   1140:   {"swapwb",  0x6770, 0x9880,            "r",       0, SIZE_NONE,
                   1141:    cris_ver_v8p,
                   1142:    cris_not_implemented_op},
                   1143: 
                   1144:   {"swapnwb", 0xE770, 0x1880,            "r",       0, SIZE_NONE,
                   1145:    cris_ver_v8p,
                   1146:    cris_not_implemented_op},
                   1147: 
                   1148:   {"swapr",   0x1770, 0xe880,            "r",       0, SIZE_NONE,
                   1149:    cris_ver_v8p,
                   1150:    cris_not_implemented_op},
                   1151: 
                   1152:   {"swapnr",  0x9770, 0x6880,            "r",       0, SIZE_NONE,
                   1153:    cris_ver_v8p,
                   1154:    cris_not_implemented_op},
                   1155: 
                   1156:   {"swapwr",  0x5770, 0xa880,            "r",       0, SIZE_NONE,
                   1157:    cris_ver_v8p,
                   1158:    cris_not_implemented_op},
                   1159: 
                   1160:   {"swapnwr", 0xd770, 0x2880,            "r",       0, SIZE_NONE,
                   1161:    cris_ver_v8p,
                   1162:    cris_not_implemented_op},
                   1163: 
                   1164:   {"swapbr",  0x3770, 0xc880,            "r",       0, SIZE_NONE,
                   1165:    cris_ver_v8p,
                   1166:    cris_not_implemented_op},
                   1167: 
                   1168:   {"swapnbr", 0xb770, 0x4880,            "r",       0, SIZE_NONE,
                   1169:    cris_ver_v8p,
                   1170:    cris_not_implemented_op},
                   1171: 
                   1172:   {"swapwbr", 0x7770, 0x8880,            "r",       0, SIZE_NONE,
                   1173:    cris_ver_v8p,
                   1174:    cris_not_implemented_op},
                   1175: 
                   1176:   {"swapnwbr", 0xf770, 0x0880,           "r",       0, SIZE_NONE,
                   1177:    cris_ver_v8p,
                   1178:    cris_not_implemented_op},
                   1179: 
                   1180:   {"test",    0x0640, 0x0980,            "m D",     0, SIZE_NONE,
                   1181:    cris_ver_v0_10,
                   1182:    cris_reg_mode_test_op},
                   1183: 
                   1184:   {"test",    0x0b80, 0xf040,            "m y",     0, SIZE_FIELD,    0,
                   1185:    cris_none_reg_mode_clear_test_op},
                   1186: 
                   1187:   {"test",    0x0b80, 0xf040,            "m S",     0, SIZE_NONE,
                   1188:    cris_ver_v0_10,
                   1189:    cris_none_reg_mode_clear_test_op},
                   1190: 
                   1191:   {"xor",     0x07B0, 0x0840,            "r,R",     0, SIZE_NONE,     0,
                   1192:    cris_xor_op},
                   1193: 
                   1194:   {NULL, 0, 0, NULL, 0, 0, 0, cris_not_implemented_op}
                   1195: };
                   1196: 
                   1197: /* Condition-names, indexed by the CC_* numbers as found in cris.h. */
                   1198: const char * const
                   1199: cris_cc_strings[] =
                   1200: {
                   1201:   "hs",
                   1202:   "lo",
                   1203:   "ne",
                   1204:   "eq",
                   1205:   "vc",
                   1206:   "vs",
                   1207:   "pl",
                   1208:   "mi",
                   1209:   "ls",
                   1210:   "hi",
                   1211:   "ge",
                   1212:   "lt",
                   1213:   "gt",
                   1214:   "le",
                   1215:   "a",
                   1216:   /* This is a placeholder.  In v0, this would be "ext".  In v32, this
                   1217:      is "sb".  See cris_conds15.  */
                   1218:   "wf"
                   1219: };
                   1220: 
                   1221: /* Different names and semantics for condition 1111 (0xf).  */
                   1222: const struct cris_cond15 cris_cond15s[] =
                   1223: {
                   1224:   /* FIXME: In what version did condition "ext" disappear?  */
                   1225:   {"ext", cris_ver_v0_3},
                   1226:   {"wf", cris_ver_v10},
                   1227:   {"sb", cris_ver_v32p},
                   1228:   {NULL, 0}
                   1229: };
                   1230: 
                   1231: 
                   1232: /*
                   1233:  * Local variables:
                   1234:  * eval: (c-set-style "gnu")
                   1235:  * indent-tabs-mode: t
                   1236:  * End:
                   1237:  */
                   1238: 
                   1239: 
                   1240: /* No instruction will be disassembled longer than this.  In theory, and
                   1241:    in silicon, address prefixes can be cascaded.  In practice, cascading
                   1242:    is not used by GCC, and not supported by the assembler.  */
                   1243: #ifndef MAX_BYTES_PER_CRIS_INSN
                   1244: #define MAX_BYTES_PER_CRIS_INSN 8
                   1245: #endif
                   1246: 
                   1247: /* Whether or not to decode prefixes, folding it into the following
                   1248:    instruction.  FIXME: Make this optional later.  */
                   1249: #ifndef PARSE_PREFIX
                   1250: #define PARSE_PREFIX 1
                   1251: #endif
                   1252: 
                   1253: /* Sometimes we prefix all registers with this character.  */
                   1254: #define REGISTER_PREFIX_CHAR '$'
                   1255: 
                   1256: /* Whether or not to trace the following sequence:
                   1257:    sub* X,r%d
                   1258:    bound* Y,r%d
                   1259:    adds.w [pc+r%d.w],pc
                   1260: 
                   1261:    This is the assembly form of a switch-statement in C.
                   1262:    The "sub is optional.  If there is none, then X will be zero.
                   1263:    X is the value of the first case,
                   1264:    Y is the number of cases (including default).
                   1265: 
                   1266:    This results in case offsets printed on the form:
                   1267:     case N: -> case_address
                   1268:    where N is an estimation on the corresponding 'case' operand in C,
                   1269:    and case_address is where execution of that case continues after the
                   1270:    sequence presented above.
                   1271: 
                   1272:    The old style of output was to print the offsets as instructions,
                   1273:    which made it hard to follow "case"-constructs in the disassembly,
                   1274:    and caused a lot of annoying warnings about undefined instructions.
                   1275: 
                   1276:    FIXME: Make this optional later.  */
                   1277: #ifndef TRACE_CASE
                   1278: #define TRACE_CASE (disdata->trace_case)
                   1279: #endif
                   1280: 
                   1281: enum cris_disass_family
                   1282:  { cris_dis_v0_v10, cris_dis_common_v10_v32, cris_dis_v32 };
                   1283: 
                   1284: /* Stored in the disasm_info->private_data member.  */
                   1285: struct cris_disasm_data
                   1286: {
                   1287:   /* Whether to print something less confusing if we find something
                   1288:      matching a switch-construct.  */
                   1289:   bfd_boolean trace_case;
                   1290: 
                   1291:   /* Whether this code is flagged as crisv32.  FIXME: Should be an enum
                   1292:      that includes "compatible".  */
                   1293:   enum cris_disass_family distype;
                   1294: };
                   1295: 
                   1296: /* Value of first element in switch.  */
                   1297: static long case_offset = 0;
                   1298: 
                   1299: /* How many more case-offsets to print.  */
                   1300: static long case_offset_counter = 0;
                   1301: 
                   1302: /* Number of case offsets.  */
                   1303: static long no_of_case_offsets = 0;
                   1304: 
                   1305: /* Candidate for next case_offset.  */
                   1306: static long last_immediate = 0;
                   1307: 
                   1308: static int cris_constraint
                   1309:   (const char *, unsigned, unsigned, struct cris_disasm_data *);
                   1310: 
                   1311: /* Parse disassembler options and store state in info.  FIXME: For the
                   1312:    time being, we abuse static variables.  */
                   1313: 
                   1314: static bfd_boolean
                   1315: cris_parse_disassembler_options (disassemble_info *info,
                   1316:                                 enum cris_disass_family distype)
                   1317: {
                   1318:   struct cris_disasm_data *disdata;
                   1319: 
                   1320:   info->private_data = calloc (1, sizeof (struct cris_disasm_data));
                   1321:   disdata = (struct cris_disasm_data *) info->private_data;
                   1322:   if (disdata == NULL)
                   1323:     return FALSE;
                   1324: 
                   1325:   /* Default true.  */
                   1326:   disdata->trace_case
                   1327:     = (info->disassembler_options == NULL
                   1328:        || (strcmp (info->disassembler_options, "nocase") != 0));
                   1329: 
                   1330:   disdata->distype = distype;
                   1331:   return TRUE;
                   1332: }
                   1333: 
                   1334: static const struct cris_spec_reg *
                   1335: spec_reg_info (unsigned int sreg, enum cris_disass_family distype)
                   1336: {
                   1337:   int i;
                   1338: 
                   1339:   for (i = 0; cris_spec_regs[i].name != NULL; i++)
                   1340:     {
                   1341:       if (cris_spec_regs[i].number == sreg)
                   1342:        {
                   1343:          if (distype == cris_dis_v32)
                   1344:            switch (cris_spec_regs[i].applicable_version)
                   1345:              {
                   1346:              case cris_ver_warning:
                   1347:              case cris_ver_version_all:
                   1348:              case cris_ver_v3p:
                   1349:              case cris_ver_v8p:
                   1350:              case cris_ver_v10p:
                   1351:              case cris_ver_v32p:
                   1352:                /* No ambiguous sizes or register names with CRISv32.  */
                   1353:                if (cris_spec_regs[i].warning == NULL)
                   1354:                  return &cris_spec_regs[i];
                   1355:              default:
                   1356:                ;
                   1357:              }
                   1358:          else if (cris_spec_regs[i].applicable_version != cris_ver_v32p)
                   1359:            return &cris_spec_regs[i];
                   1360:        }
                   1361:     }
                   1362: 
                   1363:   return NULL;
                   1364: }
                   1365: 
                   1366: /* Return the number of bits in the argument.  */
                   1367: 
                   1368: static int
                   1369: number_of_bits (unsigned int val)
                   1370: {
                   1371:   int bits;
                   1372: 
                   1373:   for (bits = 0; val != 0; val &= val - 1)
                   1374:     bits++;
                   1375: 
                   1376:   return bits;
                   1377: }
                   1378: 
                   1379: /* Get an entry in the opcode-table.  */
                   1380: 
                   1381: static const struct cris_opcode *
                   1382: get_opcode_entry (unsigned int insn,
                   1383:                  unsigned int prefix_insn,
                   1384:                  struct cris_disasm_data *disdata)
                   1385: {
                   1386:   /* For non-prefixed insns, we keep a table of pointers, indexed by the
                   1387:      insn code.  Each entry is initialized when found to be NULL.  */
                   1388:   static const struct cris_opcode **opc_table = NULL;
                   1389: 
                   1390:   const struct cris_opcode *max_matchedp = NULL;
                   1391:   const struct cris_opcode **prefix_opc_table = NULL;
                   1392: 
                   1393:   /* We hold a table for each prefix that need to be handled differently.  */
                   1394:   static const struct cris_opcode **dip_prefixes = NULL;
                   1395:   static const struct cris_opcode **bdapq_m1_prefixes = NULL;
                   1396:   static const struct cris_opcode **bdapq_m2_prefixes = NULL;
                   1397:   static const struct cris_opcode **bdapq_m4_prefixes = NULL;
                   1398:   static const struct cris_opcode **rest_prefixes = NULL;
                   1399: 
                   1400:   /* Allocate and clear the opcode-table.  */
                   1401:   if (opc_table == NULL)
                   1402:     {
1.1.1.2   root     1403:       opc_table = qemu_malloc (65536 * sizeof (opc_table[0]));
1.1       root     1404: 
                   1405:       memset (opc_table, 0, 65536 * sizeof (const struct cris_opcode *));
                   1406: 
                   1407:       dip_prefixes
1.1.1.2   root     1408:        = qemu_malloc (65536 * sizeof (const struct cris_opcode **));
1.1       root     1409: 
                   1410:       memset (dip_prefixes, 0, 65536 * sizeof (dip_prefixes[0]));
                   1411: 
                   1412:       bdapq_m1_prefixes
1.1.1.2   root     1413:        = qemu_malloc (65536 * sizeof (const struct cris_opcode **));
1.1       root     1414: 
                   1415:       memset (bdapq_m1_prefixes, 0, 65536 * sizeof (bdapq_m1_prefixes[0]));
                   1416: 
                   1417:       bdapq_m2_prefixes
1.1.1.2   root     1418:        = qemu_malloc (65536 * sizeof (const struct cris_opcode **));
1.1       root     1419: 
                   1420:       memset (bdapq_m2_prefixes, 0, 65536 * sizeof (bdapq_m2_prefixes[0]));
                   1421: 
                   1422:       bdapq_m4_prefixes
1.1.1.2   root     1423:        = qemu_malloc (65536 * sizeof (const struct cris_opcode **));
1.1       root     1424: 
                   1425:       memset (bdapq_m4_prefixes, 0, 65536 * sizeof (bdapq_m4_prefixes[0]));
                   1426: 
                   1427:       rest_prefixes
1.1.1.2   root     1428:        = qemu_malloc (65536 * sizeof (const struct cris_opcode **));
1.1       root     1429: 
                   1430:       memset (rest_prefixes, 0, 65536 * sizeof (rest_prefixes[0]));
                   1431:     }
                   1432: 
                   1433:   /* Get the right table if this is a prefix.
                   1434:      This code is connected to cris_constraints in that it knows what
                   1435:      prefixes play a role in recognition of patterns; the necessary
                   1436:      state is reflected by which table is used.  If constraints
                   1437:      involving match or non-match of prefix insns are changed, then this
                   1438:      probably needs changing too.  */
                   1439:   if (prefix_insn != NO_CRIS_PREFIX)
                   1440:     {
                   1441:       const struct cris_opcode *popcodep
                   1442:        = (opc_table[prefix_insn] != NULL
                   1443:           ? opc_table[prefix_insn]
                   1444:           : get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata));
                   1445: 
                   1446:       if (popcodep == NULL)
                   1447:        return NULL;
                   1448: 
                   1449:       if (popcodep->match == BDAP_QUICK_OPCODE)
                   1450:        {
                   1451:          /* Since some offsets are recognized with "push" macros, we
                   1452:             have to have different tables for them.  */
                   1453:          int offset = (prefix_insn & 255);
                   1454: 
                   1455:          if (offset > 127)
                   1456:            offset -= 256;
                   1457: 
                   1458:          switch (offset)
                   1459:            {
                   1460:            case -4:
                   1461:              prefix_opc_table = bdapq_m4_prefixes;
                   1462:              break;
                   1463: 
                   1464:            case -2:
                   1465:              prefix_opc_table = bdapq_m2_prefixes;
                   1466:              break;
                   1467: 
                   1468:            case -1:
                   1469:              prefix_opc_table = bdapq_m1_prefixes;
                   1470:              break;
                   1471: 
                   1472:            default:
                   1473:              prefix_opc_table = rest_prefixes;
                   1474:              break;
                   1475:            }
                   1476:        }
                   1477:       else if (popcodep->match == DIP_OPCODE)
                   1478:        /* We don't allow postincrement when the prefix is DIP, so use a
                   1479:           different table for DIP.  */
                   1480:        prefix_opc_table = dip_prefixes;
                   1481:       else
                   1482:        prefix_opc_table = rest_prefixes;
                   1483:     }
                   1484: 
                   1485:   if (prefix_insn != NO_CRIS_PREFIX
                   1486:       && prefix_opc_table[insn] != NULL)
                   1487:     max_matchedp = prefix_opc_table[insn];
                   1488:   else if (prefix_insn == NO_CRIS_PREFIX && opc_table[insn] != NULL)
                   1489:     max_matchedp = opc_table[insn];
                   1490:   else
                   1491:     {
                   1492:       const struct cris_opcode *opcodep;
                   1493:       int max_level_of_match = -1;
                   1494: 
                   1495:       for (opcodep = cris_opcodes;
                   1496:           opcodep->name != NULL;
                   1497:           opcodep++)
                   1498:        {
                   1499:          int level_of_match;
                   1500: 
                   1501:          if (disdata->distype == cris_dis_v32)
                   1502:            {
                   1503:              switch (opcodep->applicable_version)
                   1504:                {
                   1505:                case cris_ver_version_all:
                   1506:                  break;
                   1507: 
                   1508:                case cris_ver_v0_3:
                   1509:                case cris_ver_v0_10:
                   1510:                case cris_ver_v3_10:
                   1511:                case cris_ver_sim_v0_10:
                   1512:                case cris_ver_v8_10:
                   1513:                case cris_ver_v10:
                   1514:                case cris_ver_warning:
                   1515:                  continue;
                   1516: 
                   1517:                case cris_ver_v3p:
                   1518:                case cris_ver_v8p:
                   1519:                case cris_ver_v10p:
                   1520:                case cris_ver_v32p:
                   1521:                  break;
                   1522: 
                   1523:                case cris_ver_v8:
                   1524:                  abort ();
                   1525:                default:
                   1526:                  abort ();
                   1527:                }
                   1528:            }
                   1529:          else
                   1530:            {
                   1531:              switch (opcodep->applicable_version)
                   1532:                {
                   1533:                case cris_ver_version_all:
                   1534:                case cris_ver_v0_3:
                   1535:                case cris_ver_v3p:
                   1536:                case cris_ver_v0_10:
                   1537:                case cris_ver_v8p:
                   1538:                case cris_ver_v8_10:
                   1539:                case cris_ver_v10:
                   1540:                case cris_ver_sim_v0_10:
                   1541:                case cris_ver_v10p:
                   1542:                case cris_ver_warning:
                   1543:                  break;
                   1544: 
                   1545:                case cris_ver_v32p:
                   1546:                  continue;
                   1547: 
                   1548:                case cris_ver_v8:
                   1549:                  abort ();
                   1550:                default:
                   1551:                  abort ();
                   1552:                }
                   1553:            }
                   1554: 
                   1555:          /* We give a double lead for bits matching the template in
                   1556:             cris_opcodes.  Not even, because then "move p8,r10" would
                   1557:             be given 2 bits lead over "clear.d r10".  When there's a
                   1558:             tie, the first entry in the table wins.  This is
                   1559:             deliberate, to avoid a more complicated recognition
                   1560:             formula.  */
                   1561:          if ((opcodep->match & insn) == opcodep->match
                   1562:              && (opcodep->lose & insn) == 0
                   1563:              && ((level_of_match
                   1564:                   = cris_constraint (opcodep->args,
                   1565:                                      insn,
                   1566:                                      prefix_insn,
                   1567:                                      disdata))
                   1568:                  >= 0)
                   1569:              && ((level_of_match
                   1570:                   += 2 * number_of_bits (opcodep->match
                   1571:                                          | opcodep->lose))
                   1572:                          > max_level_of_match))
                   1573:                    {
                   1574:                      max_matchedp = opcodep;
                   1575:                      max_level_of_match = level_of_match;
                   1576: 
                   1577:                      /* If there was a full match, never mind looking
                   1578:                         further.  */
                   1579:                      if (level_of_match >= 2 * 16)
                   1580:                        break;
                   1581:                    }
                   1582:                }
                   1583:       /* Fill in the new entry.
                   1584: 
                   1585:         If there are changes to the opcode-table involving prefixes, and
                   1586:         disassembly then does not work correctly, try removing the
                   1587:         else-clause below that fills in the prefix-table.  If that
                   1588:         helps, you need to change the prefix_opc_table setting above, or
                   1589:         something related.  */
                   1590:       if (prefix_insn == NO_CRIS_PREFIX)
                   1591:        opc_table[insn] = max_matchedp;
                   1592:       else
                   1593:        prefix_opc_table[insn] = max_matchedp;
                   1594:     }
                   1595: 
                   1596:   return max_matchedp;
                   1597: }
                   1598: 
                   1599: /* Return -1 if the constraints of a bitwise-matched instruction say
                   1600:    that there is no match.  Otherwise return a nonnegative number
                   1601:    indicating the confidence in the match (higher is better).  */
                   1602: 
                   1603: static int
                   1604: cris_constraint (const char *cs,
                   1605:                 unsigned int insn,
                   1606:                 unsigned int prefix_insn,
                   1607:                 struct cris_disasm_data *disdata)
                   1608: {
                   1609:   int retval = 0;
                   1610:   int tmp;
                   1611:   int prefix_ok = 0;
                   1612:   const char *s;
                   1613: 
                   1614:   for (s = cs; *s; s++)
                   1615:     switch (*s)
                   1616:       {
                   1617:       case '!':
                   1618:        /* Do not recognize "pop" if there's a prefix and then only for
                   1619:            v0..v10.  */
                   1620:        if (prefix_insn != NO_CRIS_PREFIX
                   1621:            || disdata->distype != cris_dis_v0_v10)
                   1622:          return -1;
                   1623:        break;
                   1624: 
                   1625:       case 'U':
                   1626:        /* Not recognized at disassembly.  */
                   1627:        return -1;
                   1628: 
                   1629:       case 'M':
                   1630:        /* Size modifier for "clear", i.e. special register 0, 4 or 8.
                   1631:           Check that it is one of them.  Only special register 12 could
                   1632:           be mismatched, but checking for matches is more logical than
                   1633:           checking for mismatches when there are only a few cases.  */
                   1634:        tmp = ((insn >> 12) & 0xf);
                   1635:        if (tmp != 0 && tmp != 4 && tmp != 8)
                   1636:          return -1;
                   1637:        break;
                   1638: 
                   1639:       case 'm':
                   1640:        if ((insn & 0x30) == 0x30)
                   1641:          return -1;
                   1642:        break;
                   1643: 
                   1644:       case 'S':
                   1645:        /* A prefix operand without side-effect.  */
                   1646:        if (prefix_insn != NO_CRIS_PREFIX && (insn & 0x400) == 0)
                   1647:          {
                   1648:            prefix_ok = 1;
                   1649:            break;
                   1650:          }
                   1651:        else
                   1652:          return -1;
                   1653: 
                   1654:       case 's':
                   1655:       case 'y':
                   1656:       case 'Y':
                   1657:        /* If this is a prefixed insn with postincrement (side-effect),
                   1658:           the prefix must not be DIP.  */
                   1659:        if (prefix_insn != NO_CRIS_PREFIX)
                   1660:          {
                   1661:            if (insn & 0x400)
                   1662:              {
                   1663:                const struct cris_opcode *prefix_opcodep
                   1664:                  = get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata);
                   1665: 
                   1666:                if (prefix_opcodep->match == DIP_OPCODE)
                   1667:                  return -1;
                   1668:              }
                   1669: 
                   1670:            prefix_ok = 1;
                   1671:          }
                   1672:        break;
                   1673: 
                   1674:       case 'B':
                   1675:        /* If we don't fall through, then the prefix is ok.  */
                   1676:        prefix_ok = 1;
                   1677: 
                   1678:        /* A "push" prefix.  Check for valid "push" size.
                   1679:           In case of special register, it may be != 4.  */
                   1680:        if (prefix_insn != NO_CRIS_PREFIX)
                   1681:          {
                   1682:            /* Match the prefix insn to BDAPQ.  */
                   1683:            const struct cris_opcode *prefix_opcodep
                   1684:              = get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata);
                   1685: 
                   1686:            if (prefix_opcodep->match == BDAP_QUICK_OPCODE)
                   1687:              {
                   1688:                int pushsize = (prefix_insn & 255);
                   1689: 
                   1690:                if (pushsize > 127)
                   1691:                  pushsize -= 256;
                   1692: 
                   1693:                if (s[1] == 'P')
                   1694:                  {
                   1695:                    unsigned int spec_reg = (insn >> 12) & 15;
                   1696:                    const struct cris_spec_reg *sregp
                   1697:                      = spec_reg_info (spec_reg, disdata->distype);
                   1698: 
                   1699:                    /* For a special-register, the "prefix size" must
                   1700:                       match the size of the register.  */
                   1701:                    if (sregp && sregp->reg_size == (unsigned int) -pushsize)
                   1702:                      break;
                   1703:                  }
                   1704:                else if (s[1] == 'R')
                   1705:                  {
                   1706:                    if ((insn & 0x30) == 0x20 && pushsize == -4)
                   1707:                      break;
                   1708:                  }
                   1709:                /* FIXME:  Should abort here; next constraint letter
                   1710:                   *must* be 'P' or 'R'.  */
                   1711:              }
                   1712:          }
                   1713:        return -1;
                   1714: 
                   1715:       case 'D':
                   1716:        retval = (((insn >> 12) & 15) == (insn & 15));
                   1717:        if (!retval)
                   1718:          return -1;
                   1719:        else
                   1720:          retval += 4;
                   1721:        break;
                   1722: 
                   1723:       case 'P':
                   1724:        {
                   1725:          const struct cris_spec_reg *sregp
                   1726:            = spec_reg_info ((insn >> 12) & 15, disdata->distype);
                   1727: 
                   1728:          /* Since we match four bits, we will give a value of 4-1 = 3
                   1729:             in a match.  If there is a corresponding exact match of a
                   1730:             special register in another pattern, it will get a value of
                   1731:             4, which will be higher.  This should be correct in that an
                   1732:             exact pattern would match better than a general pattern.
                   1733: 
                   1734:             Note that there is a reason for not returning zero; the
                   1735:             pattern for "clear" is partly  matched in the bit-pattern
                   1736:             (the two lower bits must be zero), while the bit-pattern
                   1737:             for a move from a special register is matched in the
                   1738:             register constraint.  */
                   1739: 
                   1740:          if (sregp != NULL)
                   1741:            {
                   1742:              retval += 3;
                   1743:              break;
                   1744:            }
                   1745:          else
                   1746:            return -1;
                   1747:        }
                   1748:       }
                   1749: 
                   1750:   if (prefix_insn != NO_CRIS_PREFIX && ! prefix_ok)
                   1751:     return -1;
                   1752: 
                   1753:   return retval;
                   1754: }
                   1755: 
                   1756: /* Format number as hex with a leading "0x" into outbuffer.  */
                   1757: 
                   1758: static char *
                   1759: format_hex (unsigned long number,
                   1760:            char *outbuffer,
                   1761:            struct cris_disasm_data *disdata)
                   1762: {
                   1763:   /* Truncate negative numbers on >32-bit hosts.  */
                   1764:   number &= 0xffffffff;
                   1765: 
                   1766:   sprintf (outbuffer, "0x%lx", number);
                   1767: 
                   1768:   /* Save this value for the "case" support.  */
                   1769:   if (TRACE_CASE)
                   1770:     last_immediate = number;
                   1771: 
                   1772:   return outbuffer + strlen (outbuffer);
                   1773: }
                   1774: 
                   1775: /* Format number as decimal into outbuffer.  Parameter signedp says
                   1776:    whether the number should be formatted as signed (!= 0) or
                   1777:    unsigned (== 0).  */
                   1778: 
                   1779: static char *
                   1780: format_dec (long number, char *outbuffer, int signedp)
                   1781: {
                   1782:   last_immediate = number;
                   1783:   sprintf (outbuffer, signedp ? "%ld" : "%lu", number);
                   1784: 
                   1785:   return outbuffer + strlen (outbuffer);
                   1786: }
                   1787: 
                   1788: /* Format the name of the general register regno into outbuffer.  */
                   1789: 
                   1790: static char *
                   1791: format_reg (struct cris_disasm_data *disdata,
                   1792:            int regno,
                   1793:            char *outbuffer_start,
                   1794:            bfd_boolean with_reg_prefix)
                   1795: {
                   1796:   char *outbuffer = outbuffer_start;
                   1797: 
                   1798:   if (with_reg_prefix)
                   1799:     *outbuffer++ = REGISTER_PREFIX_CHAR;
                   1800: 
                   1801:   switch (regno)
                   1802:     {
                   1803:     case 15:
                   1804:       /* For v32, there is no context in which we output PC.  */
                   1805:       if (disdata->distype == cris_dis_v32)
                   1806:        strcpy (outbuffer, "acr");
                   1807:       else
                   1808:        strcpy (outbuffer, "pc");
                   1809:       break;
                   1810: 
                   1811:     case 14:
                   1812:       strcpy (outbuffer, "sp");
                   1813:       break;
                   1814: 
                   1815:     default:
                   1816:       sprintf (outbuffer, "r%d", regno);
                   1817:       break;
                   1818:     }
                   1819: 
                   1820:   return outbuffer_start + strlen (outbuffer_start);
                   1821: }
                   1822: 
                   1823: /* Format the name of a support register into outbuffer.  */
                   1824: 
                   1825: static char *
                   1826: format_sup_reg (unsigned int regno,
                   1827:                char *outbuffer_start,
                   1828:                bfd_boolean with_reg_prefix)
                   1829: {
                   1830:   char *outbuffer = outbuffer_start;
                   1831:   int i;
                   1832: 
                   1833:   if (with_reg_prefix)
                   1834:     *outbuffer++ = REGISTER_PREFIX_CHAR;
                   1835: 
                   1836:   for (i = 0; cris_support_regs[i].name != NULL; i++)
                   1837:     if (cris_support_regs[i].number == regno)
                   1838:       {
                   1839:        sprintf (outbuffer, "%s", cris_support_regs[i].name);
                   1840:        return outbuffer_start + strlen (outbuffer_start);
                   1841:       }
                   1842: 
                   1843:   /* There's supposed to be register names covering all numbers, though
                   1844:      some may be generic names.  */
                   1845:   sprintf (outbuffer, "format_sup_reg-BUG");
                   1846:   return outbuffer_start + strlen (outbuffer_start);
                   1847: }
                   1848: 
                   1849: /* Return the length of an instruction.  */
                   1850: 
                   1851: static unsigned
                   1852: bytes_to_skip (unsigned int insn,
                   1853:               const struct cris_opcode *matchedp,
                   1854:               enum cris_disass_family distype,
                   1855:               const struct cris_opcode *prefix_matchedp)
                   1856: {
                   1857:   /* Each insn is a word plus "immediate" operands.  */
                   1858:   unsigned to_skip = 2;
                   1859:   const char *template = matchedp->args;
                   1860:   const char *s;
                   1861: 
                   1862:   for (s = template; *s; s++)
                   1863:     if ((*s == 's' || *s == 'N' || *s == 'Y')
                   1864:        && (insn & 0x400) && (insn & 15) == 15
                   1865:        && prefix_matchedp == NULL)
                   1866:       {
                   1867:        /* Immediate via [pc+], so we have to check the size of the
                   1868:           operand.  */
                   1869:        int mode_size = 1 << ((insn >> 4) & (*template == 'z' ? 1 : 3));
                   1870: 
                   1871:        if (matchedp->imm_oprnd_size == SIZE_FIX_32)
                   1872:          to_skip += 4;
                   1873:        else if (matchedp->imm_oprnd_size == SIZE_SPEC_REG)
                   1874:          {
                   1875:            const struct cris_spec_reg *sregp
                   1876:              = spec_reg_info ((insn >> 12) & 15, distype);
                   1877: 
                   1878:            /* FIXME: Improve error handling; should have been caught
                   1879:               earlier.  */
                   1880:            if (sregp == NULL)
                   1881:              return 2;
                   1882: 
                   1883:            /* PC is incremented by two, not one, for a byte.  Except on
                   1884:               CRISv32, where constants are always DWORD-size for
                   1885:               special registers.  */
                   1886:            to_skip +=
                   1887:              distype == cris_dis_v32 ? 4 : (sregp->reg_size + 1) & ~1;
                   1888:          }
                   1889:        else
                   1890:          to_skip += (mode_size + 1) & ~1;
                   1891:       }
                   1892:     else if (*s == 'n')
                   1893:       to_skip += 4;
                   1894:     else if (*s == 'b')
                   1895:       to_skip += 2;
                   1896: 
                   1897:   return to_skip;
                   1898: }
                   1899: 
                   1900: /* Print condition code flags.  */
                   1901: 
                   1902: static char *
                   1903: print_flags (struct cris_disasm_data *disdata, unsigned int insn, char *cp)
                   1904: {
                   1905:   /* Use the v8 (Etrax 100) flag definitions for disassembly.
                   1906:      The differences with v0 (Etrax 1..4) vs. Svinto are:
                   1907:       v0 'd' <=> v8 'm'
                   1908:       v0 'e' <=> v8 'b'.
                   1909:      FIXME: Emit v0..v3 flag names somehow.  */
                   1910:   static const char v8_fnames[] = "cvznxibm";
                   1911:   static const char v32_fnames[] = "cvznxiup";
                   1912:   const char *fnames
                   1913:     = disdata->distype == cris_dis_v32 ? v32_fnames : v8_fnames;
                   1914: 
                   1915:   unsigned char flagbits = (((insn >> 8) & 0xf0) | (insn & 15));
                   1916:   int i;
                   1917: 
                   1918:   for (i = 0; i < 8; i++)
                   1919:     if (flagbits & (1 << i))
                   1920:       *cp++ = fnames[i];
                   1921: 
                   1922:   return cp;
                   1923: }
                   1924: 
                   1925: /* Print out an insn with its operands, and update the info->insn_type
                   1926:    fields.  The prefix_opcodep and the rest hold a prefix insn that is
                   1927:    supposed to be output as an address mode.  */
                   1928: 
                   1929: static void
                   1930: print_with_operands (const struct cris_opcode *opcodep,
                   1931:                     unsigned int insn,
                   1932:                     unsigned char *buffer,
                   1933:                     bfd_vma addr,
                   1934:                     disassemble_info *info,
                   1935:                     /* If a prefix insn was before this insn (and is supposed
                   1936:                        to be output as an address), here is a description of
                   1937:                        it.  */
                   1938:                     const struct cris_opcode *prefix_opcodep,
                   1939:                     unsigned int prefix_insn,
                   1940:                     unsigned char *prefix_buffer,
                   1941:                     bfd_boolean with_reg_prefix)
                   1942: {
                   1943:   /* Get a buffer of somewhat reasonable size where we store
                   1944:      intermediate parts of the insn.  */
                   1945:   char temp[sizeof (".d [$r13=$r12-2147483648],$r10") * 2];
                   1946:   char *tp = temp;
                   1947:   static const char mode_char[] = "bwd?";
                   1948:   const char *s;
                   1949:   const char *cs;
                   1950:   struct cris_disasm_data *disdata
                   1951:     = (struct cris_disasm_data *) info->private_data;
                   1952: 
                   1953:   /* Print out the name first thing we do.  */
                   1954:   (*info->fprintf_func) (info->stream, "%s", opcodep->name);
                   1955: 
                   1956:   cs = opcodep->args;
                   1957:   s = cs;
                   1958: 
                   1959:   /* Ignore any prefix indicator.  */
                   1960:   if (*s == 'p')
                   1961:     s++;
                   1962: 
                   1963:   if (*s == 'm' || *s == 'M' || *s == 'z')
                   1964:     {
                   1965:       *tp++ = '.';
                   1966: 
                   1967:       /* Get the size-letter.  */
                   1968:       *tp++ = *s == 'M'
                   1969:        ? (insn & 0x8000 ? 'd'
                   1970:           : insn & 0x4000 ? 'w' : 'b')
                   1971:        : mode_char[(insn >> 4) & (*s == 'z' ? 1 : 3)];
                   1972: 
                   1973:       /* Ignore the size and the space character that follows.  */
                   1974:       s += 2;
                   1975:     }
                   1976: 
                   1977:   /* Add a space if this isn't a long-branch, because for those will add
                   1978:      the condition part of the name later.  */
                   1979:   if (opcodep->match != (BRANCH_PC_LOW + BRANCH_INCR_HIGH * 256))
                   1980:     *tp++ = ' ';
                   1981: 
                   1982:   /* Fill in the insn-type if deducible from the name (and there's no
                   1983:      better way).  */
                   1984:   if (opcodep->name[0] == 'j')
                   1985:     {
                   1986:       if (CONST_STRNEQ (opcodep->name, "jsr"))
                   1987:        /* It's "jsr" or "jsrc".  */
                   1988:        info->insn_type = dis_jsr;
                   1989:       else
                   1990:        /* Any other jump-type insn is considered a branch.  */
                   1991:        info->insn_type = dis_branch;
                   1992:     }
                   1993: 
                   1994:   /* We might know some more fields right now.  */
                   1995:   info->branch_delay_insns = opcodep->delayed;
                   1996: 
                   1997:   /* Handle operands.  */
                   1998:   for (; *s; s++)
                   1999:     {
                   2000:     switch (*s)
                   2001:       {
                   2002:       case 'T':
                   2003:        tp = format_sup_reg ((insn >> 12) & 15, tp, with_reg_prefix);
                   2004:        break;
                   2005: 
                   2006:       case 'A':
                   2007:        if (with_reg_prefix)
                   2008:          *tp++ = REGISTER_PREFIX_CHAR;
                   2009:        *tp++ = 'a';
                   2010:        *tp++ = 'c';
                   2011:        *tp++ = 'r';
                   2012:        break;
                   2013: 
                   2014:       case '[':
                   2015:       case ']':
                   2016:       case ',':
                   2017:        *tp++ = *s;
                   2018:        break;
                   2019: 
                   2020:       case '!':
                   2021:        /* Ignore at this point; used at earlier stages to avoid
                   2022:           recognition if there's a prefix at something that in other
                   2023:           ways looks like a "pop".  */
                   2024:        break;
                   2025: 
                   2026:       case 'd':
                   2027:        /* Ignore.  This is an optional ".d " on the large one of
                   2028:           relaxable insns.  */
                   2029:        break;
                   2030: 
                   2031:       case 'B':
                   2032:        /* This was the prefix that made this a "push".  We've already
                   2033:           handled it by recognizing it, so signal that the prefix is
                   2034:           handled by setting it to NULL.  */
                   2035:        prefix_opcodep = NULL;
                   2036:        break;
                   2037: 
                   2038:       case 'D':
                   2039:       case 'r':
                   2040:        tp = format_reg (disdata, insn & 15, tp, with_reg_prefix);
                   2041:        break;
                   2042: 
                   2043:       case 'R':
                   2044:        tp = format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix);
                   2045:        break;
                   2046: 
                   2047:       case 'n':
                   2048:        {
                   2049:          /* Like N but pc-relative to the start of the insn.  */
                   2050:          unsigned long number
                   2051:            = (buffer[2] + buffer[3] * 256 + buffer[4] * 65536
                   2052:               + buffer[5] * 0x1000000 + addr);
                   2053: 
                   2054:          /* Finish off and output previous formatted bytes.  */
                   2055:          *tp = 0;
                   2056:          if (temp[0])
                   2057:            (*info->fprintf_func) (info->stream, "%s", temp);
                   2058:          tp = temp;
                   2059: 
                   2060:          (*info->print_address_func) ((bfd_vma) number, info);
                   2061:        }
                   2062:        break;
                   2063: 
                   2064:       case 'u':
                   2065:        {
                   2066:          /* Like n but the offset is bits <3:0> in the instruction.  */
                   2067:          unsigned long number = (buffer[0] & 0xf) * 2 + addr;
                   2068: 
                   2069:          /* Finish off and output previous formatted bytes.  */
                   2070:          *tp = 0;
                   2071:          if (temp[0])
                   2072:            (*info->fprintf_func) (info->stream, "%s", temp);
                   2073:          tp = temp;
                   2074: 
                   2075:          (*info->print_address_func) ((bfd_vma) number, info);
                   2076:        }
                   2077:        break;
                   2078: 
                   2079:       case 'N':
                   2080:       case 'y':
                   2081:       case 'Y':
                   2082:       case 'S':
                   2083:       case 's':
                   2084:        /* Any "normal" memory operand.  */
                   2085:        if ((insn & 0x400) && (insn & 15) == 15 && prefix_opcodep == NULL)
                   2086:          {
                   2087:            /* We're looking at [pc+], i.e. we need to output an immediate
                   2088:               number, where the size can depend on different things.  */
                   2089:            long number;
                   2090:            int signedp
                   2091:              = ((*cs == 'z' && (insn & 0x20))
                   2092:                 || opcodep->match == BDAP_QUICK_OPCODE);
                   2093:            int nbytes;
                   2094: 
                   2095:            if (opcodep->imm_oprnd_size == SIZE_FIX_32)
                   2096:              nbytes = 4;
                   2097:            else if (opcodep->imm_oprnd_size == SIZE_SPEC_REG)
                   2098:              {
                   2099:                const struct cris_spec_reg *sregp
                   2100:                  = spec_reg_info ((insn >> 12) & 15, disdata->distype);
                   2101: 
                   2102:                /* A NULL return should have been as a non-match earlier,
                   2103:                   so catch it as an internal error in the error-case
                   2104:                   below.  */
                   2105:                if (sregp == NULL)
                   2106:                  /* Whatever non-valid size.  */
                   2107:                  nbytes = 42;
                   2108:                else
                   2109:                  /* PC is always incremented by a multiple of two.
                   2110:                     For CRISv32, immediates are always 4 bytes for
                   2111:                     special registers.  */
                   2112:                  nbytes = disdata->distype == cris_dis_v32
                   2113:                    ? 4 : (sregp->reg_size + 1) & ~1;
                   2114:              }
                   2115:            else
                   2116:              {
                   2117:                int mode_size = 1 << ((insn >> 4) & (*cs == 'z' ? 1 : 3));
                   2118: 
                   2119:                if (mode_size == 1)
                   2120:                  nbytes = 2;
                   2121:                else
                   2122:                  nbytes = mode_size;
                   2123:              }
                   2124: 
                   2125:            switch (nbytes)
                   2126:              {
                   2127:              case 1:
                   2128:                number = buffer[2];
                   2129:                if (signedp && number > 127)
                   2130:                  number -= 256;
                   2131:                break;
                   2132: 
                   2133:              case 2:
                   2134:                number = buffer[2] + buffer[3] * 256;
                   2135:                if (signedp && number > 32767)
                   2136:                  number -= 65536;
                   2137:                break;
                   2138: 
                   2139:              case 4:
                   2140:                number
                   2141:                  = buffer[2] + buffer[3] * 256 + buffer[4] * 65536
                   2142:                  + buffer[5] * 0x1000000;
                   2143:                break;
                   2144: 
                   2145:              default:
                   2146:                strcpy (tp, "bug");
                   2147:                tp += 3;
                   2148:                number = 42;
                   2149:              }
                   2150: 
                   2151:            if ((*cs == 'z' && (insn & 0x20))
                   2152:                || (opcodep->match == BDAP_QUICK_OPCODE
                   2153:                    && (nbytes <= 2 || buffer[1 + nbytes] == 0)))
                   2154:              tp = format_dec (number, tp, signedp);
                   2155:            else
                   2156:              {
                   2157:                unsigned int highbyte = (number >> 24) & 0xff;
                   2158: 
                   2159:                /* Either output this as an address or as a number.  If it's
                   2160:                   a dword with the same high-byte as the address of the
                   2161:                   insn, assume it's an address, and also if it's a non-zero
                   2162:                   non-0xff high-byte.  If this is a jsr or a jump, then
                   2163:                   it's definitely an address.  */
                   2164:                if (nbytes == 4
                   2165:                    && (highbyte == ((addr >> 24) & 0xff)
                   2166:                        || (highbyte != 0 && highbyte != 0xff)
                   2167:                        || info->insn_type == dis_branch
                   2168:                        || info->insn_type == dis_jsr))
                   2169:                  {
                   2170:                    /* Finish off and output previous formatted bytes.  */
                   2171:                    *tp = 0;
                   2172:                    tp = temp;
                   2173:                    if (temp[0])
                   2174:                      (*info->fprintf_func) (info->stream, "%s", temp);
                   2175: 
                   2176:                    (*info->print_address_func) ((bfd_vma) number, info);
                   2177: 
                   2178:                    info->target = number;
                   2179:                  }
                   2180:                else
                   2181:                  tp = format_hex (number, tp, disdata);
                   2182:              }
                   2183:          }
                   2184:        else
                   2185:          {
                   2186:            /* Not an immediate number.  Then this is a (possibly
                   2187:               prefixed) memory operand.  */
                   2188:            if (info->insn_type != dis_nonbranch)
                   2189:              {
                   2190:                int mode_size
                   2191:                  = 1 << ((insn >> 4)
                   2192:                          & (opcodep->args[0] == 'z' ? 1 : 3));
                   2193:                int size;
                   2194:                info->insn_type = dis_dref;
                   2195:                info->flags |= CRIS_DIS_FLAG_MEMREF;
                   2196: 
                   2197:                if (opcodep->imm_oprnd_size == SIZE_FIX_32)
                   2198:                  size = 4;
                   2199:                else if (opcodep->imm_oprnd_size == SIZE_SPEC_REG)
                   2200:                  {
                   2201:                    const struct cris_spec_reg *sregp
                   2202:                      = spec_reg_info ((insn >> 12) & 15, disdata->distype);
                   2203: 
                   2204:                    /* FIXME: Improve error handling; should have been caught
                   2205:                       earlier.  */
                   2206:                    if (sregp == NULL)
                   2207:                      size = 4;
                   2208:                    else
                   2209:                      size = sregp->reg_size;
                   2210:                  }
                   2211:                else
                   2212:                  size = mode_size;
                   2213: 
                   2214:                info->data_size = size;
                   2215:              }
                   2216: 
                   2217:            *tp++ = '[';
                   2218: 
                   2219:            if (prefix_opcodep
                   2220:                /* We don't match dip with a postincremented field
                   2221:                   as a side-effect address mode.  */
                   2222:                && ((insn & 0x400) == 0
                   2223:                    || prefix_opcodep->match != DIP_OPCODE))
                   2224:              {
                   2225:                if (insn & 0x400)
                   2226:                  {
                   2227:                    tp = format_reg (disdata, insn & 15, tp, with_reg_prefix);
                   2228:                    *tp++ = '=';
                   2229:                  }
                   2230: 
                   2231: 
                   2232:                /* We mainly ignore the prefix format string when the
                   2233:                   address-mode syntax is output.  */
                   2234:                switch (prefix_opcodep->match)
                   2235:                  {
                   2236:                  case DIP_OPCODE:
                   2237:                    /* It's [r], [r+] or [pc+].  */
                   2238:                    if ((prefix_insn & 0x400) && (prefix_insn & 15) == 15)
                   2239:                      {
                   2240:                        /* It's [pc+].  This cannot possibly be anything
                   2241:                           but an address.  */
                   2242:                        unsigned long number
                   2243:                          = prefix_buffer[2] + prefix_buffer[3] * 256
                   2244:                          + prefix_buffer[4] * 65536
                   2245:                          + prefix_buffer[5] * 0x1000000;
                   2246: 
                   2247:                        info->target = (bfd_vma) number;
                   2248: 
                   2249:                        /* Finish off and output previous formatted
                   2250:                           data.  */
                   2251:                        *tp = 0;
                   2252:                        tp = temp;
                   2253:                        if (temp[0])
                   2254:                          (*info->fprintf_func) (info->stream, "%s", temp);
                   2255: 
                   2256:                        (*info->print_address_func) ((bfd_vma) number, info);
                   2257:                      }
                   2258:                    else
                   2259:                      {
                   2260:                        /* For a memref in an address, we use target2.
                   2261:                           In this case, target is zero.  */
                   2262:                        info->flags
                   2263:                          |= (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG
                   2264:                              | CRIS_DIS_FLAG_MEM_TARGET2_MEM);
                   2265: 
                   2266:                        info->target2 = prefix_insn & 15;
                   2267: 
                   2268:                        *tp++ = '[';
                   2269:                        tp = format_reg (disdata, prefix_insn & 15, tp,
                   2270:                                         with_reg_prefix);
                   2271:                        if (prefix_insn & 0x400)
                   2272:                          *tp++ = '+';
                   2273:                        *tp++ = ']';
                   2274:                      }
                   2275:                    break;
                   2276: 
                   2277:                  case BDAP_QUICK_OPCODE:
                   2278:                    {
                   2279:                      int number;
                   2280: 
                   2281:                      number = prefix_buffer[0];
                   2282:                      if (number > 127)
                   2283:                        number -= 256;
                   2284: 
                   2285:                      /* Output "reg+num" or, if num < 0, "reg-num".  */
                   2286:                      tp = format_reg (disdata, (prefix_insn >> 12) & 15, tp,
                   2287:                                       with_reg_prefix);
                   2288:                      if (number >= 0)
                   2289:                        *tp++ = '+';
                   2290:                      tp = format_dec (number, tp, 1);
                   2291: 
                   2292:                      info->flags |= CRIS_DIS_FLAG_MEM_TARGET_IS_REG;
                   2293:                      info->target = (prefix_insn >> 12) & 15;
                   2294:                      info->target2 = (bfd_vma) number;
                   2295:                      break;
                   2296:                    }
                   2297: 
                   2298:                  case BIAP_OPCODE:
                   2299:                    /* Output "r+R.m".  */
                   2300:                    tp = format_reg (disdata, prefix_insn & 15, tp,
                   2301:                                     with_reg_prefix);
                   2302:                    *tp++ = '+';
                   2303:                    tp = format_reg (disdata, (prefix_insn >> 12) & 15, tp,
                   2304:                                     with_reg_prefix);
                   2305:                    *tp++ = '.';
                   2306:                    *tp++ = mode_char[(prefix_insn >> 4) & 3];
                   2307: 
                   2308:                    info->flags
                   2309:                      |= (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG
                   2310:                          | CRIS_DIS_FLAG_MEM_TARGET_IS_REG
                   2311: 
                   2312:                          | ((prefix_insn & 0x8000)
                   2313:                             ? CRIS_DIS_FLAG_MEM_TARGET2_MULT4
                   2314:                             : ((prefix_insn & 0x8000)
                   2315:                                ? CRIS_DIS_FLAG_MEM_TARGET2_MULT2 : 0)));
                   2316: 
                   2317:                    /* Is it the casejump?  It's a "adds.w [pc+r%d.w],pc".  */
                   2318:                    if (insn == 0xf83f && (prefix_insn & ~0xf000) == 0x55f)
                   2319:                      /* Then start interpreting data as offsets.  */
                   2320:                      case_offset_counter = no_of_case_offsets;
                   2321:                    break;
                   2322: 
                   2323:                  case BDAP_INDIR_OPCODE:
                   2324:                    /* Output "r+s.m", or, if "s" is [pc+], "r+s" or
                   2325:                       "r-s".  */
                   2326:                    tp = format_reg (disdata, (prefix_insn >> 12) & 15, tp,
                   2327:                                     with_reg_prefix);
                   2328: 
                   2329:                    if ((prefix_insn & 0x400) && (prefix_insn & 15) == 15)
                   2330:                      {
                   2331:                        long number;
                   2332:                        unsigned int nbytes;
                   2333: 
                   2334:                        /* It's a value.  Get its size.  */
                   2335:                        int mode_size = 1 << ((prefix_insn >> 4) & 3);
                   2336: 
                   2337:                        if (mode_size == 1)
                   2338:                          nbytes = 2;
                   2339:                        else
                   2340:                          nbytes = mode_size;
                   2341: 
                   2342:                        switch (nbytes)
                   2343:                          {
                   2344:                          case 1:
                   2345:                            number = prefix_buffer[2];
                   2346:                            if (number > 127)
                   2347:                              number -= 256;
                   2348:                            break;
                   2349: 
                   2350:                          case 2:
                   2351:                            number = prefix_buffer[2] + prefix_buffer[3] * 256;
                   2352:                            if (number > 32767)
                   2353:                              number -= 65536;
                   2354:                            break;
                   2355: 
                   2356:                          case 4:
                   2357:                            number
                   2358:                              = prefix_buffer[2] + prefix_buffer[3] * 256
                   2359:                              + prefix_buffer[4] * 65536
                   2360:                              + prefix_buffer[5] * 0x1000000;
                   2361:                            break;
                   2362: 
                   2363:                          default:
                   2364:                            strcpy (tp, "bug");
                   2365:                            tp += 3;
                   2366:                            number = 42;
                   2367:                          }
                   2368: 
                   2369:                        info->flags |= CRIS_DIS_FLAG_MEM_TARGET_IS_REG;
                   2370:                        info->target2 = (bfd_vma) number;
                   2371: 
                   2372:                        /* If the size is dword, then assume it's an
                   2373:                           address.  */
                   2374:                        if (nbytes == 4)
                   2375:                          {
                   2376:                            /* Finish off and output previous formatted
                   2377:                               bytes.  */
                   2378:                            *tp++ = '+';
                   2379:                            *tp = 0;
                   2380:                            tp = temp;
                   2381:                            (*info->fprintf_func) (info->stream, "%s", temp);
                   2382: 
                   2383:                            (*info->print_address_func) ((bfd_vma) number, info);
                   2384:                          }
                   2385:                        else
                   2386:                          {
                   2387:                            if (number >= 0)
                   2388:                              *tp++ = '+';
                   2389:                            tp = format_dec (number, tp, 1);
                   2390:                          }
                   2391:                      }
                   2392:                    else
                   2393:                      {
                   2394:                        /* Output "r+[R].m" or "r+[R+].m".  */
                   2395:                        *tp++ = '+';
                   2396:                        *tp++ = '[';
                   2397:                        tp = format_reg (disdata, prefix_insn & 15, tp,
                   2398:                                         with_reg_prefix);
                   2399:                        if (prefix_insn & 0x400)
                   2400:                          *tp++ = '+';
                   2401:                        *tp++ = ']';
                   2402:                        *tp++ = '.';
                   2403:                        *tp++ = mode_char[(prefix_insn >> 4) & 3];
                   2404: 
                   2405:                        info->flags
                   2406:                          |= (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG
                   2407:                              | CRIS_DIS_FLAG_MEM_TARGET2_MEM
                   2408:                              | CRIS_DIS_FLAG_MEM_TARGET_IS_REG
                   2409: 
                   2410:                              | (((prefix_insn >> 4) == 2)
                   2411:                                 ? 0
                   2412:                                 : (((prefix_insn >> 4) & 3) == 1
                   2413:                                    ? CRIS_DIS_FLAG_MEM_TARGET2_MEM_WORD
                   2414:                                    : CRIS_DIS_FLAG_MEM_TARGET2_MEM_BYTE)));
                   2415:                      }
                   2416:                    break;
                   2417: 
                   2418:                  default:
                   2419:                    (*info->fprintf_func) (info->stream, "?prefix-bug");
                   2420:                  }
                   2421: 
                   2422:                /* To mark that the prefix is used, reset it.  */
                   2423:                prefix_opcodep = NULL;
                   2424:              }
                   2425:            else
                   2426:              {
                   2427:                tp = format_reg (disdata, insn & 15, tp, with_reg_prefix);
                   2428: 
                   2429:                info->flags |= CRIS_DIS_FLAG_MEM_TARGET_IS_REG;
                   2430:                info->target = insn & 15;
                   2431: 
                   2432:                if (insn & 0x400)
                   2433:                  *tp++ = '+';
                   2434:              }
                   2435:            *tp++ = ']';
                   2436:          }
                   2437:        break;
                   2438: 
                   2439:       case 'x':
                   2440:        tp = format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix);
                   2441:        *tp++ = '.';
                   2442:        *tp++ = mode_char[(insn >> 4) & 3];
                   2443:        break;
                   2444: 
                   2445:       case 'I':
                   2446:        tp = format_dec (insn & 63, tp, 0);
                   2447:        break;
                   2448: 
                   2449:       case 'b':
                   2450:        {
                   2451:          int where = buffer[2] + buffer[3] * 256;
                   2452: 
                   2453:          if (where > 32767)
                   2454:            where -= 65536;
                   2455: 
                   2456:          where += addr + ((disdata->distype == cris_dis_v32) ? 0 : 4);
                   2457: 
                   2458:          if (insn == BA_PC_INCR_OPCODE)
                   2459:            info->insn_type = dis_branch;
                   2460:          else
                   2461:            info->insn_type = dis_condbranch;
                   2462: 
                   2463:          info->target = (bfd_vma) where;
                   2464: 
                   2465:          *tp = 0;
                   2466:          tp = temp;
                   2467:          (*info->fprintf_func) (info->stream, "%s%s ",
                   2468:                                 temp, cris_cc_strings[insn >> 12]);
                   2469: 
                   2470:          (*info->print_address_func) ((bfd_vma) where, info);
                   2471:        }
                   2472:       break;
                   2473: 
                   2474:     case 'c':
                   2475:       tp = format_dec (insn & 31, tp, 0);
                   2476:       break;
                   2477: 
                   2478:     case 'C':
                   2479:       tp = format_dec (insn & 15, tp, 0);
                   2480:       break;
                   2481: 
                   2482:     case 'o':
                   2483:       {
                   2484:        long offset = insn & 0xfe;
                   2485:        bfd_vma target;
                   2486: 
                   2487:        if (insn & 1)
                   2488:          offset |= ~0xff;
                   2489: 
                   2490:        if (opcodep->match == BA_QUICK_OPCODE)
                   2491:          info->insn_type = dis_branch;
                   2492:        else
                   2493:          info->insn_type = dis_condbranch;
                   2494: 
                   2495:        target = addr + ((disdata->distype == cris_dis_v32) ? 0 : 2) + offset;
                   2496:        info->target = target;
                   2497:        *tp = 0;
                   2498:        tp = temp;
                   2499:        (*info->fprintf_func) (info->stream, "%s", temp);
                   2500:        (*info->print_address_func) (target, info);
                   2501:       }
                   2502:       break;
                   2503: 
                   2504:     case 'Q':
                   2505:     case 'O':
                   2506:       {
                   2507:        long number = buffer[0];
                   2508: 
                   2509:        if (number > 127)
                   2510:          number = number - 256;
                   2511: 
                   2512:        tp = format_dec (number, tp, 1);
                   2513:        *tp++ = ',';
                   2514:        tp = format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix);
                   2515:       }
                   2516:       break;
                   2517: 
                   2518:     case 'f':
                   2519:       tp = print_flags (disdata, insn, tp);
                   2520:       break;
                   2521: 
                   2522:     case 'i':
                   2523:       tp = format_dec ((insn & 32) ? (insn & 31) | ~31L : insn & 31, tp, 1);
                   2524:       break;
                   2525: 
                   2526:     case 'P':
                   2527:       {
                   2528:        const struct cris_spec_reg *sregp
                   2529:          = spec_reg_info ((insn >> 12) & 15, disdata->distype);
                   2530: 
                   2531:        if (sregp->name == NULL)
                   2532:          /* Should have been caught as a non-match eariler.  */
                   2533:          *tp++ = '?';
                   2534:        else
                   2535:          {
                   2536:            if (with_reg_prefix)
                   2537:              *tp++ = REGISTER_PREFIX_CHAR;
                   2538:            strcpy (tp, sregp->name);
                   2539:            tp += strlen (tp);
                   2540:          }
                   2541:       }
                   2542:       break;
                   2543: 
                   2544:     default:
                   2545:       strcpy (tp, "???");
                   2546:       tp += 3;
                   2547:     }
                   2548:   }
                   2549: 
                   2550:   *tp = 0;
                   2551: 
                   2552:   if (prefix_opcodep)
                   2553:     (*info->fprintf_func) (info->stream, " (OOPS unused prefix \"%s: %s\")",
                   2554:                           prefix_opcodep->name, prefix_opcodep->args);
                   2555: 
                   2556:   (*info->fprintf_func) (info->stream, "%s", temp);
                   2557: 
                   2558:   /* Get info for matching case-tables, if we don't have any active.
                   2559:      We assume that the last constant seen is used; either in the insn
                   2560:      itself or in a "move.d const,rN, sub.d rN,rM"-like sequence.  */
                   2561:   if (TRACE_CASE && case_offset_counter == 0)
                   2562:     {
                   2563:       if (CONST_STRNEQ (opcodep->name, "sub"))
                   2564:        case_offset = last_immediate;
                   2565: 
                   2566:       /* It could also be an "add", if there are negative case-values.  */
                   2567:       else if (CONST_STRNEQ (opcodep->name, "add"))
                   2568:        /* The first case is the negated operand to the add.  */
                   2569:        case_offset = -last_immediate;
                   2570: 
                   2571:       /* A bound insn will tell us the number of cases.  */
                   2572:       else if (CONST_STRNEQ (opcodep->name, "bound"))
                   2573:        no_of_case_offsets = last_immediate + 1;
                   2574: 
                   2575:       /* A jump or jsr or branch breaks the chain of insns for a
                   2576:         case-table, so assume default first-case again.  */
                   2577:       else if (info->insn_type == dis_jsr
                   2578:               || info->insn_type == dis_branch
                   2579:               || info->insn_type == dis_condbranch)
                   2580:        case_offset = 0;
                   2581:     }
                   2582: }
                   2583: 
                   2584: 
                   2585: /* Print the CRIS instruction at address memaddr on stream.  Returns
                   2586:    length of the instruction, in bytes.  Prefix register names with `$' if
                   2587:    WITH_REG_PREFIX.  */
                   2588: 
                   2589: static int
                   2590: print_insn_cris_generic (bfd_vma memaddr,
                   2591:                         disassemble_info *info,
                   2592:                         bfd_boolean with_reg_prefix)
                   2593: {
                   2594:   int nbytes;
                   2595:   unsigned int insn;
                   2596:   const struct cris_opcode *matchedp;
                   2597:   int advance = 0;
                   2598:   struct cris_disasm_data *disdata
                   2599:     = (struct cris_disasm_data *) info->private_data;
                   2600: 
                   2601:   /* No instruction will be disassembled as longer than this number of
                   2602:      bytes; stacked prefixes will not be expanded.  */
                   2603:   unsigned char buffer[MAX_BYTES_PER_CRIS_INSN];
                   2604:   unsigned char *bufp;
                   2605:   int status = 0;
                   2606:   bfd_vma addr;
                   2607: 
                   2608:   /* There will be an "out of range" error after the last instruction.
                   2609:      Reading pairs of bytes in decreasing number, we hope that we will get
                   2610:      at least the amount that we will consume.
                   2611: 
                   2612:      If we can't get any data, or we do not get enough data, we print
                   2613:      the error message.  */
                   2614: 
1.1.1.2   root     2615:   nbytes = info->buffer_length;
                   2616:   if (nbytes > MAX_BYTES_PER_CRIS_INSN)
                   2617:          nbytes = MAX_BYTES_PER_CRIS_INSN;
                   2618:   status = (*info->read_memory_func) (memaddr, buffer, nbytes, info);  
1.1       root     2619: 
                   2620:   /* If we did not get all we asked for, then clear the rest.
                   2621:      Hopefully this makes a reproducible result in case of errors.  */
                   2622:   if (nbytes != MAX_BYTES_PER_CRIS_INSN)
                   2623:     memset (buffer + nbytes, 0, MAX_BYTES_PER_CRIS_INSN - nbytes);
                   2624: 
                   2625:   addr = memaddr;
                   2626:   bufp = buffer;
                   2627: 
                   2628:   /* Set some defaults for the insn info.  */
                   2629:   info->insn_info_valid = 1;
                   2630:   info->branch_delay_insns = 0;
                   2631:   info->data_size = 0;
                   2632:   info->insn_type = dis_nonbranch;
                   2633:   info->flags = 0;
                   2634:   info->target = 0;
                   2635:   info->target2 = 0;
                   2636: 
                   2637:   /* If we got any data, disassemble it.  */
                   2638:   if (nbytes != 0)
                   2639:     {
                   2640:       matchedp = NULL;
                   2641: 
                   2642:       insn = bufp[0] + bufp[1] * 256;
                   2643: 
                   2644:       /* If we're in a case-table, don't disassemble the offsets.  */
                   2645:       if (TRACE_CASE && case_offset_counter != 0)
                   2646:        {
                   2647:          info->insn_type = dis_noninsn;
                   2648:          advance += 2;
                   2649: 
                   2650:          /* If to print data as offsets, then shortcut here.  */
                   2651:          (*info->fprintf_func) (info->stream, "case %ld%s: -> ",
                   2652:                                 case_offset + no_of_case_offsets
                   2653:                                 - case_offset_counter,
                   2654:                                 case_offset_counter == 1 ? "/default" :
                   2655:                                 "");
                   2656: 
                   2657:          (*info->print_address_func) ((bfd_vma)
                   2658:                                       ((short) (insn)
                   2659:                                        + (long) (addr
                   2660:                                                  - (no_of_case_offsets
                   2661:                                                     - case_offset_counter)
                   2662:                                                  * 2)), info);
                   2663:          case_offset_counter--;
                   2664: 
                   2665:          /* The default case start (without a "sub" or "add") must be
                   2666:             zero.  */
                   2667:          if (case_offset_counter == 0)
                   2668:            case_offset = 0;
                   2669:        }
                   2670:       else if (insn == 0)
                   2671:        {
                   2672:          /* We're often called to disassemble zeroes.  While this is a
                   2673:             valid "bcc .+2" insn, it is also useless enough and enough
                   2674:             of a nuiscance that we will just output "bcc .+2" for it
                   2675:             and signal it as a noninsn.  */
                   2676:          (*info->fprintf_func) (info->stream,
                   2677:                                 disdata->distype == cris_dis_v32
                   2678:                                 ? "bcc ." : "bcc .+2");
                   2679:          info->insn_type = dis_noninsn;
                   2680:          advance += 2;
                   2681:        }
                   2682:       else
                   2683:        {
                   2684:          const struct cris_opcode *prefix_opcodep = NULL;
                   2685:          unsigned char *prefix_buffer = bufp;
                   2686:          unsigned int prefix_insn = insn;
                   2687:          int prefix_size = 0;
                   2688: 
                   2689:          matchedp = get_opcode_entry (insn, NO_CRIS_PREFIX, disdata);
                   2690: 
                   2691:          /* Check if we're supposed to write out prefixes as address
                   2692:             modes and if this was a prefix.  */
                   2693:          if (matchedp != NULL && PARSE_PREFIX && matchedp->args[0] == 'p')
                   2694:            {
                   2695:              /* If it's a prefix, put it into the prefix vars and get the
                   2696:                 main insn.  */
                   2697:              prefix_size = bytes_to_skip (prefix_insn, matchedp,
                   2698:                                           disdata->distype, NULL);
                   2699:              prefix_opcodep = matchedp;
                   2700: 
                   2701:              insn = bufp[prefix_size] + bufp[prefix_size + 1] * 256;
                   2702:              matchedp = get_opcode_entry (insn, prefix_insn, disdata);
                   2703: 
                   2704:              if (matchedp != NULL)
                   2705:                {
                   2706:                  addr += prefix_size;
                   2707:                  bufp += prefix_size;
                   2708:                  advance += prefix_size;
                   2709:                }
                   2710:              else
                   2711:                {
                   2712:                  /* The "main" insn wasn't valid, at least not when
                   2713:                     prefixed.  Put back things enough to output the
                   2714:                     prefix insn only, as a normal insn.  */
                   2715:                  matchedp = prefix_opcodep;
                   2716:                  insn = prefix_insn;
                   2717:                  prefix_opcodep = NULL;
                   2718:                }
                   2719:            }
                   2720: 
                   2721:          if (matchedp == NULL)
                   2722:            {
                   2723:              (*info->fprintf_func) (info->stream, "??0x%x", insn);
                   2724:              advance += 2;
                   2725: 
                   2726:              info->insn_type = dis_noninsn;
                   2727:            }
                   2728:          else
                   2729:            {
                   2730:              advance
                   2731:                += bytes_to_skip (insn, matchedp, disdata->distype,
                   2732:                                  prefix_opcodep);
                   2733: 
                   2734:              /* The info_type and assorted fields will be set according
                   2735:                 to the operands.   */
                   2736:              print_with_operands (matchedp, insn, bufp, addr, info,
                   2737:                                   prefix_opcodep, prefix_insn,
                   2738:                                   prefix_buffer, with_reg_prefix);
                   2739:            }
                   2740:        }
                   2741:     }
                   2742:   else
                   2743:     info->insn_type = dis_noninsn;
                   2744: 
                   2745:   /* If we read less than MAX_BYTES_PER_CRIS_INSN, i.e. we got an error
                   2746:      status when reading that much, and the insn decoding indicated a
                   2747:      length exceeding what we read, there is an error.  */
                   2748:   if (status != 0 && (nbytes == 0 || advance > nbytes))
                   2749:     {
                   2750:       (*info->memory_error_func) (status, memaddr, info);
                   2751:       return -1;
                   2752:     }
                   2753: 
                   2754:   /* Max supported insn size with one folded prefix insn.  */
                   2755:   info->bytes_per_line = MAX_BYTES_PER_CRIS_INSN;
                   2756: 
                   2757:   /* I would like to set this to a fixed value larger than the actual
                   2758:      number of bytes to print in order to avoid spaces between bytes,
                   2759:      but objdump.c (2.9.1) does not like that, so we print 16-bit
                   2760:      chunks, which is the next choice.  */
                   2761:   info->bytes_per_chunk = 2;
                   2762: 
                   2763:   /* Printing bytes in order of increasing addresses makes sense,
                   2764:      especially on a little-endian target.
                   2765:      This is completely the opposite of what you think; setting this to
                   2766:      BFD_ENDIAN_LITTLE will print bytes in order N..0 rather than the 0..N
                   2767:      we want.  */
                   2768:   info->display_endian = BFD_ENDIAN_BIG;
                   2769: 
                   2770:   return advance;
                   2771: }
                   2772: 
                   2773: /* Disassemble, prefixing register names with `$'.  CRIS v0..v10.  */
                   2774: #if 0
                   2775: static int
                   2776: print_insn_cris_with_register_prefix (bfd_vma vma,
                   2777:                                      disassemble_info *info)
                   2778: {
                   2779:   if (info->private_data == NULL
                   2780:       && !cris_parse_disassembler_options (info, cris_dis_v0_v10))
                   2781:     return -1;
                   2782:   return print_insn_cris_generic (vma, info, TRUE);
                   2783: }
                   2784: #endif
                   2785: /* Disassemble, prefixing register names with `$'.  CRIS v32.  */
                   2786: 
                   2787: static int
                   2788: print_insn_crisv32_with_register_prefix (bfd_vma vma,
                   2789:                                         disassemble_info *info)
                   2790: {
                   2791:   if (info->private_data == NULL
                   2792:       && !cris_parse_disassembler_options (info, cris_dis_v32))
                   2793:     return -1;
                   2794:   return print_insn_cris_generic (vma, info, TRUE);
                   2795: }
                   2796: 
                   2797: #if 0
                   2798: /* Disassemble, prefixing register names with `$'.
                   2799:    Common v10 and v32 subset.  */
                   2800: 
                   2801: static int
                   2802: print_insn_crisv10_v32_with_register_prefix (bfd_vma vma,
                   2803:                                             disassemble_info *info)
                   2804: {
                   2805:   if (info->private_data == NULL
                   2806:       && !cris_parse_disassembler_options (info, cris_dis_common_v10_v32))
                   2807:     return -1;
                   2808:   return print_insn_cris_generic (vma, info, TRUE);
                   2809: }
                   2810: 
                   2811: /* Disassemble, no prefixes on register names.  CRIS v0..v10.  */
                   2812: 
                   2813: static int
                   2814: print_insn_cris_without_register_prefix (bfd_vma vma,
                   2815:                                         disassemble_info *info)
                   2816: {
                   2817:   if (info->private_data == NULL
                   2818:       && !cris_parse_disassembler_options (info, cris_dis_v0_v10))
                   2819:     return -1;
                   2820:   return print_insn_cris_generic (vma, info, FALSE);
                   2821: }
                   2822: 
                   2823: /* Disassemble, no prefixes on register names.  CRIS v32.  */
                   2824: 
                   2825: static int
                   2826: print_insn_crisv32_without_register_prefix (bfd_vma vma,
                   2827:                                            disassemble_info *info)
                   2828: {
                   2829:   if (info->private_data == NULL
                   2830:       && !cris_parse_disassembler_options (info, cris_dis_v32))
                   2831:     return -1;
                   2832:   return print_insn_cris_generic (vma, info, FALSE);
                   2833: }
                   2834: 
                   2835: /* Disassemble, no prefixes on register names.
                   2836:    Common v10 and v32 subset.  */
                   2837: 
                   2838: static int
                   2839: print_insn_crisv10_v32_without_register_prefix (bfd_vma vma,
                   2840:                                                disassemble_info *info)
                   2841: {
                   2842:   if (info->private_data == NULL
                   2843:       && !cris_parse_disassembler_options (info, cris_dis_common_v10_v32))
                   2844:     return -1;
                   2845:   return print_insn_cris_generic (vma, info, FALSE);
                   2846: }
                   2847: #endif
                   2848: 
                   2849: int
                   2850: print_insn_crisv32 (bfd_vma vma,
                   2851:                    disassemble_info *info)
                   2852: {
                   2853:   return print_insn_crisv32_with_register_prefix(vma, info);
                   2854: }
                   2855: 
                   2856: /* Return a disassembler-function that prints registers with a `$' prefix,
                   2857:    or one that prints registers without a prefix.
                   2858:    FIXME: We should improve the solution to avoid the multitude of
                   2859:    functions seen above.  */
                   2860: #if 0
                   2861: disassembler_ftype
                   2862: cris_get_disassembler (bfd *abfd)
                   2863: {
                   2864:   /* If there's no bfd in sight, we return what is valid as input in all
                   2865:      contexts if fed back to the assembler: disassembly *with* register
                   2866:      prefix.  Unfortunately this will be totally wrong for v32.  */
                   2867:   if (abfd == NULL)
                   2868:     return print_insn_cris_with_register_prefix;
                   2869: 
                   2870:   if (bfd_get_symbol_leading_char (abfd) == 0)
                   2871:     {
                   2872:       if (bfd_get_mach (abfd) == bfd_mach_cris_v32)
                   2873:        return print_insn_crisv32_with_register_prefix;
                   2874:       if (bfd_get_mach (abfd) == bfd_mach_cris_v10_v32)
                   2875:        return print_insn_crisv10_v32_with_register_prefix;
                   2876: 
                   2877:       /* We default to v10.  This may be specifically specified in the
                   2878:         bfd mach, but is also the default setting.  */
                   2879:       return print_insn_cris_with_register_prefix;
                   2880:     }
                   2881: 
                   2882:   if (bfd_get_mach (abfd) == bfd_mach_cris_v32)
                   2883:     return print_insn_crisv32_without_register_prefix;
                   2884:   if (bfd_get_mach (abfd) == bfd_mach_cris_v10_v32)
                   2885:     return print_insn_crisv10_v32_without_register_prefix;
                   2886:   return print_insn_cris_without_register_prefix;
                   2887: }
                   2888: #endif
                   2889: /* Local variables:
                   2890:    eval: (c-set-style "gnu")
                   2891:    indent-tabs-mode: t
                   2892:    End:  */

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