File:  [Qemu by Fabrice Bellard] / qemu / cris-dis.c
Revision 1.1.1.2 (vendor branch): download - view: text, annotated - select for diffs
Tue Apr 24 16:50:34 2018 UTC (3 years, 1 month ago) by root
Branches: qemu, MAIN
CVS tags: qemu0105, qemu0104, qemu0103, qemu0102, qemu0101, qemu0100, HEAD
qemu 0.10.0

    1: /* Disassembler code for CRIS.
    2:    Copyright 2000, 2001, 2002, 2004, 2005, 2006 Free Software Foundation, Inc.
    3:    Contributed by Axis Communications AB, Lund, Sweden.
    4:    Written by Hans-Peter Nilsson.
    5: 
    6:    This file is part of the GNU binutils and GDB, the GNU debugger.
    7: 
    8:    This program is free software; you can redistribute it and/or modify it
    9:    under the terms of the GNU General Public License as published by the
   10:    Free Software Foundation; either version 2, or (at your option) any later
   11:    version.
   12: 
   13:    This program is distributed in the hope that it will be useful, but WITHOUT
   14:    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   15:    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   16:    more details.
   17: 
   18:    You should have received a copy of the GNU General Public License
   19:    along with this program; if not, write to the Free Software
   20:    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
   21:    MA 02110-1301, USA.  */
   22: 
   23: #include "dis-asm.h"
   24: //#include "sysdep.h"
   25: #include "target-cris/opcode-cris.h"
   26: //#include "libiberty.h"
   27: 
   28: 
   29: void *qemu_malloc(size_t len); /* can't include qemu-common.h here */
   30: 
   31: #define FALSE 0
   32: #define TRUE 1
   33: #define CONST_STRNEQ(STR1,STR2) (strncmp ((STR1), (STR2), sizeof (STR2) - 1) == 0)
   34: 
   35: /* cris-opc.c -- Table of opcodes for the CRIS processor.
   36:    Copyright 2000, 2001, 2004 Free Software Foundation, Inc.
   37:    Contributed by Axis Communications AB, Lund, Sweden.
   38:    Originally written for GAS 1.38.1 by Mikael Asker.
   39:    Reorganized by Hans-Peter Nilsson.
   40: 
   41: This file is part of GAS, GDB and the GNU binutils.
   42: 
   43: GAS, GDB, and GNU binutils is free software; you can redistribute it
   44: and/or modify it under the terms of the GNU General Public License as
   45: published by the Free Software Foundation; either version 2, or (at your
   46: option) any later version.
   47: 
   48: GAS, GDB, and GNU binutils are distributed in the hope that they will be
   49: useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
   50: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   51: GNU General Public License for more details.
   52: 
   53: You should have received a copy of the GNU General Public License
   54: along with this program; if not, write to the Free Software
   55: Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
   56: 
   57: #ifndef NULL
   58: #define NULL (0)
   59: #endif
   60: 
   61: /* This table isn't used for CRISv32 and the size of immediate operands.  */
   62: const struct cris_spec_reg
   63: cris_spec_regs[] =
   64: {
   65:   {"bz",  0,  1, cris_ver_v32p,	   NULL},
   66:   {"p0",  0,  1, 0,		   NULL},
   67:   {"vr",  1,  1, 0,		   NULL},
   68:   {"p1",  1,  1, 0,		   NULL},
   69:   {"pid", 2,  1, cris_ver_v32p,    NULL},
   70:   {"p2",  2,  1, cris_ver_v32p,	   NULL},
   71:   {"p2",  2,  1, cris_ver_warning, NULL},
   72:   {"srs", 3,  1, cris_ver_v32p,    NULL},
   73:   {"p3",  3,  1, cris_ver_v32p,	   NULL},
   74:   {"p3",  3,  1, cris_ver_warning, NULL},
   75:   {"wz",  4,  2, cris_ver_v32p,	   NULL},
   76:   {"p4",  4,  2, 0,		   NULL},
   77:   {"ccr", 5,  2, cris_ver_v0_10,   NULL},
   78:   {"exs", 5,  4, cris_ver_v32p,	   NULL},
   79:   {"p5",  5,  2, cris_ver_v0_10,   NULL},
   80:   {"p5",  5,  4, cris_ver_v32p,	   NULL},
   81:   {"dcr0",6,  2, cris_ver_v0_3,	   NULL},
   82:   {"eda", 6,  4, cris_ver_v32p,	   NULL},
   83:   {"p6",  6,  2, cris_ver_v0_3,	   NULL},
   84:   {"p6",  6,  4, cris_ver_v32p,	   NULL},
   85:   {"dcr1/mof", 7, 4, cris_ver_v10p,
   86:    "Register `dcr1/mof' with ambiguous size specified.  Guessing 4 bytes"},
   87:   {"dcr1/mof", 7, 2, cris_ver_v0_3,
   88:    "Register `dcr1/mof' with ambiguous size specified.  Guessing 2 bytes"},
   89:   {"mof", 7,  4, cris_ver_v10p,	   NULL},
   90:   {"dcr1",7,  2, cris_ver_v0_3,	   NULL},
   91:   {"p7",  7,  4, cris_ver_v10p,	   NULL},
   92:   {"p7",  7,  2, cris_ver_v0_3,	   NULL},
   93:   {"dz",  8,  4, cris_ver_v32p,	   NULL},
   94:   {"p8",  8,  4, 0,		   NULL},
   95:   {"ibr", 9,  4, cris_ver_v0_10,   NULL},
   96:   {"ebp", 9,  4, cris_ver_v32p,	   NULL},
   97:   {"p9",  9,  4, 0,		   NULL},
   98:   {"irp", 10, 4, cris_ver_v0_10,   NULL},
   99:   {"erp", 10, 4, cris_ver_v32p,	   NULL},
  100:   {"p10", 10, 4, 0,		   NULL},
  101:   {"srp", 11, 4, 0,		   NULL},
  102:   {"p11", 11, 4, 0,		   NULL},
  103:   /* For disassembly use only.  Accept at assembly with a warning.  */
  104:   {"bar/dtp0", 12, 4, cris_ver_warning,
  105:    "Ambiguous register `bar/dtp0' specified"},
  106:   {"nrp", 12, 4, cris_ver_v32p,	   NULL},
  107:   {"bar", 12, 4, cris_ver_v8_10,   NULL},
  108:   {"dtp0",12, 4, cris_ver_v0_3,	   NULL},
  109:   {"p12", 12, 4, 0,		   NULL},
  110:   /* For disassembly use only.  Accept at assembly with a warning.  */
  111:   {"dccr/dtp1",13, 4, cris_ver_warning,
  112:    "Ambiguous register `dccr/dtp1' specified"},
  113:   {"ccs", 13, 4, cris_ver_v32p,	   NULL},
  114:   {"dccr",13, 4, cris_ver_v8_10,   NULL},
  115:   {"dtp1",13, 4, cris_ver_v0_3,	   NULL},
  116:   {"p13", 13, 4, 0,		   NULL},
  117:   {"brp", 14, 4, cris_ver_v3_10,   NULL},
  118:   {"usp", 14, 4, cris_ver_v32p,	   NULL},
  119:   {"p14", 14, 4, cris_ver_v3p,	   NULL},
  120:   {"usp", 15, 4, cris_ver_v10,	   NULL},
  121:   {"spc", 15, 4, cris_ver_v32p,	   NULL},
  122:   {"p15", 15, 4, cris_ver_v10p,	   NULL},
  123:   {NULL, 0, 0, cris_ver_version_all, NULL}
  124: };
  125: 
  126: /* Add version specifiers to this table when necessary.
  127:    The (now) regular coding of register names suggests a simpler
  128:    implementation.  */
  129: const struct cris_support_reg cris_support_regs[] =
  130: {
  131:   {"s0", 0},
  132:   {"s1", 1},
  133:   {"s2", 2},
  134:   {"s3", 3},
  135:   {"s4", 4},
  136:   {"s5", 5},
  137:   {"s6", 6},
  138:   {"s7", 7},
  139:   {"s8", 8},
  140:   {"s9", 9},
  141:   {"s10", 10},
  142:   {"s11", 11},
  143:   {"s12", 12},
  144:   {"s13", 13},
  145:   {"s14", 14},
  146:   {"s15", 15},
  147:   {NULL, 0}
  148: };
  149: 
  150: /* All CRIS opcodes are 16 bits.
  151: 
  152:    - The match component is a mask saying which bits must match a
  153:      particular opcode in order for an instruction to be an instance
  154:      of that opcode.
  155: 
  156:    - The args component is a string containing characters symbolically
  157:      matching the operands of an instruction.  Used for both assembly
  158:      and disassembly.
  159: 
  160:      Operand-matching characters:
  161:      [ ] , space
  162:         Verbatim.
  163:      A	The string "ACR" (case-insensitive).
  164:      B	Not really an operand.  It causes a "BDAP -size,SP" prefix to be
  165: 	output for the PUSH alias-instructions and recognizes a push-
  166: 	prefix at disassembly.  This letter isn't recognized for v32.
  167: 	Must be followed by a R or P letter.
  168:      !	Non-match pattern, will not match if there's a prefix insn.
  169:      b	Non-matching operand, used for branches with 16-bit
  170: 	displacement. Only recognized by the disassembler.
  171:      c	5-bit unsigned immediate in bits <4:0>.
  172:      C	4-bit unsigned immediate in bits <3:0>.
  173:      d  At assembly, optionally (as in put other cases before this one)
  174: 	".d" or ".D" at the start of the operands, followed by one space
  175: 	character.  At disassembly, nothing.
  176:      D	General register in bits <15:12> and <3:0>.
  177:      f	List of flags in bits <15:12> and <3:0>.
  178:      i	6-bit signed immediate in bits <5:0>.
  179:      I	6-bit unsigned immediate in bits <5:0>.
  180:      M	Size modifier (B, W or D) for CLEAR instructions.
  181:      m	Size modifier (B, W or D) in bits <5:4>
  182:      N  A 32-bit dword, like in the difference between s and y.
  183:         This has no effect on bits in the opcode.  Can also be expressed
  184: 	as "[pc+]" in input.
  185:      n  As N, but PC-relative (to the start of the instruction).
  186:      o	[-128..127] word offset in bits <7:1> and <0>.  Used by 8-bit
  187: 	branch instructions.
  188:      O	[-128..127] offset in bits <7:0>.  Also matches a comma and a
  189: 	general register after the expression, in bits <15:12>.  Used
  190: 	only for the BDAP prefix insn (in v32 the ADDOQ insn; same opcode).
  191:      P	Special register in bits <15:12>.
  192:      p	Indicates that the insn is a prefix insn.  Must be first
  193: 	character.
  194:      Q  As O, but don't relax; force an 8-bit offset.
  195:      R	General register in bits <15:12>.
  196:      r	General register in bits <3:0>.
  197:      S	Source operand in bit <10> and a prefix; a 3-operand prefix
  198: 	without side-effect.
  199:      s	Source operand in bits <10> and <3:0>, optionally with a
  200: 	side-effect prefix, except [pc] (the name, not R15 as in ACR)
  201: 	isn't allowed for v32 and higher.
  202:      T  Support register in bits <15:12>.
  203:      u  4-bit (PC-relative) unsigned immediate word offset in bits <3:0>.
  204:      U  Relaxes to either u or n, instruction is assumed LAPCQ or LAPC.
  205: 	Not recognized at disassembly.
  206:      x	Register-dot-modifier, for example "r5.w" in bits <15:12> and <5:4>.
  207:      y	Like 's' but do not allow an integer at assembly.
  208:      Y	The difference s-y; only an integer is allowed.
  209:      z	Size modifier (B or W) in bit <4>.  */
  210: 
  211: 
  212: /* Please note the order of the opcodes in this table is significant.
  213:    The assembler requires that all instances of the same mnemonic must
  214:    be consecutive.  If they aren't, the assembler might not recognize
  215:    them, or may indicate an internal error.
  216: 
  217:    The disassembler should not normally care about the order of the
  218:    opcodes, but will prefer an earlier alternative if the "match-score"
  219:    (see cris-dis.c) is computed as equal.
  220: 
  221:    It should not be significant for proper execution that this table is
  222:    in alphabetical order, but please follow that convention for an easy
  223:    overview.  */
  224: 
  225: const struct cris_opcode
  226: cris_opcodes[] =
  227: {
  228:   {"abs",     0x06B0, 0x0940,		  "r,R",     0, SIZE_NONE,     0,
  229:    cris_abs_op},
  230: 
  231:   {"add",     0x0600, 0x09c0,		  "m r,R",   0, SIZE_NONE,     0,
  232:    cris_reg_mode_add_sub_cmp_and_or_move_op},
  233: 
  234:   {"add",     0x0A00, 0x01c0,		  "m s,R",   0, SIZE_FIELD,    0,
  235:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
  236: 
  237:   {"add",     0x0A00, 0x01c0,		  "m S,D",   0, SIZE_NONE,
  238:    cris_ver_v0_10,
  239:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
  240: 
  241:   {"add",     0x0a00, 0x05c0,		  "m S,R,r", 0, SIZE_NONE,
  242:    cris_ver_v0_10,
  243:    cris_three_operand_add_sub_cmp_and_or_op},
  244: 
  245:   {"add",     0x0A00, 0x01c0,		  "m s,R",   0, SIZE_FIELD,
  246:    cris_ver_v32p,
  247:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
  248: 
  249:   {"addc",    0x0570, 0x0A80,		  "r,R",     0, SIZE_FIX_32,
  250:    cris_ver_v32p,
  251:    cris_not_implemented_op},
  252: 
  253:   {"addc",    0x09A0, 0x0250,		  "s,R",     0, SIZE_FIX_32,
  254:    cris_ver_v32p,
  255:    cris_not_implemented_op},
  256: 
  257:   {"addi",    0x0540, 0x0A80,		  "x,r,A",   0, SIZE_NONE,
  258:    cris_ver_v32p,
  259:    cris_addi_op},
  260: 
  261:   {"addi",    0x0500, 0x0Ac0,		  "x,r",     0, SIZE_NONE,     0,
  262:    cris_addi_op},
  263: 
  264:   /* This collates after "addo", but we want to disassemble as "addoq",
  265:      not "addo".  */
  266:   {"addoq",   0x0100, 0x0E00,		  "Q,A",     0, SIZE_NONE,
  267:    cris_ver_v32p,
  268:    cris_not_implemented_op},
  269: 
  270:   {"addo",    0x0940, 0x0280,		  "m s,R,A", 0, SIZE_FIELD_SIGNED,
  271:    cris_ver_v32p,
  272:    cris_not_implemented_op},
  273: 
  274:   /* This must be located after the insn above, lest we misinterpret
  275:      "addo.b -1,r0,acr" as "addo .b-1,r0,acr".  FIXME: Sounds like a
  276:      parser bug.  */
  277:   {"addo",   0x0100, 0x0E00,		  "O,A",     0, SIZE_NONE,
  278:    cris_ver_v32p,
  279:    cris_not_implemented_op},
  280: 
  281:   {"addq",    0x0200, 0x0Dc0,		  "I,R",     0, SIZE_NONE,     0,
  282:    cris_quick_mode_add_sub_op},
  283: 
  284:   {"adds",    0x0420, 0x0Bc0,		  "z r,R",   0, SIZE_NONE,     0,
  285:    cris_reg_mode_add_sub_cmp_and_or_move_op},
  286: 
  287:   /* FIXME: SIZE_FIELD_SIGNED and all necessary changes.  */
  288:   {"adds",    0x0820, 0x03c0,		  "z s,R",   0, SIZE_FIELD,    0,
  289:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
  290: 
  291:   {"adds",    0x0820, 0x03c0,		  "z S,D",   0, SIZE_NONE,
  292:    cris_ver_v0_10,
  293:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
  294: 
  295:   {"adds",    0x0820, 0x07c0,		  "z S,R,r", 0, SIZE_NONE,
  296:    cris_ver_v0_10,
  297:    cris_three_operand_add_sub_cmp_and_or_op},
  298: 
  299:   {"addu",    0x0400, 0x0be0,		  "z r,R",   0, SIZE_NONE,     0,
  300:    cris_reg_mode_add_sub_cmp_and_or_move_op},
  301: 
  302:   /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes.  */
  303:   {"addu",    0x0800, 0x03e0,		  "z s,R",   0, SIZE_FIELD,    0,
  304:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
  305: 
  306:   {"addu",    0x0800, 0x03e0,		  "z S,D",   0, SIZE_NONE,
  307:    cris_ver_v0_10,
  308:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
  309: 
  310:   {"addu",    0x0800, 0x07e0,		  "z S,R,r", 0, SIZE_NONE,
  311:    cris_ver_v0_10,
  312:    cris_three_operand_add_sub_cmp_and_or_op},
  313: 
  314:   {"and",     0x0700, 0x08C0,		  "m r,R",   0, SIZE_NONE,     0,
  315:    cris_reg_mode_add_sub_cmp_and_or_move_op},
  316: 
  317:   {"and",     0x0B00, 0x00C0,		  "m s,R",   0, SIZE_FIELD,    0,
  318:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
  319: 
  320:   {"and",     0x0B00, 0x00C0,		  "m S,D",   0, SIZE_NONE,
  321:    cris_ver_v0_10,
  322:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
  323: 
  324:   {"and",     0x0B00, 0x04C0,		  "m S,R,r", 0, SIZE_NONE,
  325:    cris_ver_v0_10,
  326:    cris_three_operand_add_sub_cmp_and_or_op},
  327: 
  328:   {"andq",    0x0300, 0x0CC0,		  "i,R",     0, SIZE_NONE,     0,
  329:    cris_quick_mode_and_cmp_move_or_op},
  330: 
  331:   {"asr",     0x0780, 0x0840,		  "m r,R",   0, SIZE_NONE,     0,
  332:    cris_asr_op},
  333: 
  334:   {"asrq",    0x03a0, 0x0c40,		  "c,R",     0, SIZE_NONE,     0,
  335:    cris_asrq_op},
  336: 
  337:   {"ax",      0x15B0, 0xEA4F,		  "",	     0, SIZE_NONE,     0,
  338:    cris_ax_ei_setf_op},
  339: 
  340:   /* FIXME: Should use branch #defines.  */
  341:   {"b",	      0x0dff, 0x0200,		  "b",	     1, SIZE_NONE,     0,
  342:    cris_sixteen_bit_offset_branch_op},
  343: 
  344:   {"ba",
  345:    BA_QUICK_OPCODE,
  346:    0x0F00+(0xF-CC_A)*0x1000,		  "o",	     1, SIZE_NONE,     0,
  347:    cris_eight_bit_offset_branch_op},
  348: 
  349:   /* Needs to come after the usual "ba o", which might be relaxed to
  350:      this one.  */
  351:   {"ba",     BA_DWORD_OPCODE,
  352:    0xffff & (~BA_DWORD_OPCODE),		  "n",	     0, SIZE_FIX_32,
  353:    cris_ver_v32p,
  354:    cris_none_reg_mode_jump_op},
  355: 
  356:   {"bas",     0x0EBF, 0x0140,		  "n,P",     0, SIZE_FIX_32,
  357:    cris_ver_v32p,
  358:    cris_none_reg_mode_jump_op},
  359: 
  360:   {"basc",     0x0EFF, 0x0100,		  "n,P",     0, SIZE_FIX_32,
  361:    cris_ver_v32p,
  362:    cris_none_reg_mode_jump_op},
  363: 
  364:   {"bcc",
  365:    BRANCH_QUICK_OPCODE+CC_CC*0x1000,
  366:    0x0f00+(0xF-CC_CC)*0x1000,		  "o",	     1, SIZE_NONE,     0,
  367:    cris_eight_bit_offset_branch_op},
  368: 
  369:   {"bcs",
  370:    BRANCH_QUICK_OPCODE+CC_CS*0x1000,
  371:    0x0f00+(0xF-CC_CS)*0x1000,		  "o",	     1, SIZE_NONE,     0,
  372:    cris_eight_bit_offset_branch_op},
  373: 
  374:   {"bdap",
  375:    BDAP_INDIR_OPCODE, BDAP_INDIR_Z_BITS,  "pm s,R",  0, SIZE_FIELD_SIGNED,
  376:    cris_ver_v0_10,
  377:    cris_bdap_prefix},
  378: 
  379:   {"bdap",
  380:    BDAP_QUICK_OPCODE, BDAP_QUICK_Z_BITS,  "pO",	     0, SIZE_NONE,
  381:    cris_ver_v0_10,
  382:    cris_quick_mode_bdap_prefix},
  383: 
  384:   {"beq",
  385:    BRANCH_QUICK_OPCODE+CC_EQ*0x1000,
  386:    0x0f00+(0xF-CC_EQ)*0x1000,		  "o",	     1, SIZE_NONE,     0,
  387:    cris_eight_bit_offset_branch_op},
  388: 
  389:   /* This is deliberately put before "bext" to trump it, even though not
  390:      in alphabetical order, since we don't do excluding version checks
  391:      for v0..v10.  */
  392:   {"bwf",
  393:    BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
  394:    0x0f00+(0xF-CC_EXT)*0x1000,		  "o",	     1, SIZE_NONE,
  395:    cris_ver_v10,
  396:    cris_eight_bit_offset_branch_op},
  397: 
  398:   {"bext",
  399:    BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
  400:    0x0f00+(0xF-CC_EXT)*0x1000,		  "o",	     1, SIZE_NONE,
  401:    cris_ver_v0_3,
  402:    cris_eight_bit_offset_branch_op},
  403: 
  404:   {"bge",
  405:    BRANCH_QUICK_OPCODE+CC_GE*0x1000,
  406:    0x0f00+(0xF-CC_GE)*0x1000,		  "o",	     1, SIZE_NONE,     0,
  407:    cris_eight_bit_offset_branch_op},
  408: 
  409:   {"bgt",
  410:    BRANCH_QUICK_OPCODE+CC_GT*0x1000,
  411:    0x0f00+(0xF-CC_GT)*0x1000,		  "o",	     1, SIZE_NONE,     0,
  412:    cris_eight_bit_offset_branch_op},
  413: 
  414:   {"bhi",
  415:    BRANCH_QUICK_OPCODE+CC_HI*0x1000,
  416:    0x0f00+(0xF-CC_HI)*0x1000,		  "o",	     1, SIZE_NONE,     0,
  417:    cris_eight_bit_offset_branch_op},
  418: 
  419:   {"bhs",
  420:    BRANCH_QUICK_OPCODE+CC_HS*0x1000,
  421:    0x0f00+(0xF-CC_HS)*0x1000,		  "o",	     1, SIZE_NONE,     0,
  422:    cris_eight_bit_offset_branch_op},
  423: 
  424:   {"biap", BIAP_OPCODE, BIAP_Z_BITS,	  "pm r,R",  0, SIZE_NONE,
  425:    cris_ver_v0_10,
  426:    cris_biap_prefix},
  427: 
  428:   {"ble",
  429:    BRANCH_QUICK_OPCODE+CC_LE*0x1000,
  430:    0x0f00+(0xF-CC_LE)*0x1000,		  "o",	     1, SIZE_NONE,     0,
  431:    cris_eight_bit_offset_branch_op},
  432: 
  433:   {"blo",
  434:    BRANCH_QUICK_OPCODE+CC_LO*0x1000,
  435:    0x0f00+(0xF-CC_LO)*0x1000,		  "o",	     1, SIZE_NONE,     0,
  436:    cris_eight_bit_offset_branch_op},
  437: 
  438:   {"bls",
  439:    BRANCH_QUICK_OPCODE+CC_LS*0x1000,
  440:    0x0f00+(0xF-CC_LS)*0x1000,		  "o",	     1, SIZE_NONE,     0,
  441:    cris_eight_bit_offset_branch_op},
  442: 
  443:   {"blt",
  444:    BRANCH_QUICK_OPCODE+CC_LT*0x1000,
  445:    0x0f00+(0xF-CC_LT)*0x1000,		  "o",	     1, SIZE_NONE,     0,
  446:    cris_eight_bit_offset_branch_op},
  447: 
  448:   {"bmi",
  449:    BRANCH_QUICK_OPCODE+CC_MI*0x1000,
  450:    0x0f00+(0xF-CC_MI)*0x1000,		  "o",	     1, SIZE_NONE,     0,
  451:    cris_eight_bit_offset_branch_op},
  452: 
  453:   {"bmod",    0x0ab0, 0x0140,		  "s,R",     0, SIZE_FIX_32,
  454:    cris_ver_sim_v0_10,
  455:    cris_not_implemented_op},
  456: 
  457:   {"bmod",    0x0ab0, 0x0140,		  "S,D",     0, SIZE_NONE,
  458:    cris_ver_sim_v0_10,
  459:    cris_not_implemented_op},
  460: 
  461:   {"bmod",    0x0ab0, 0x0540,		  "S,R,r",   0, SIZE_NONE,
  462:    cris_ver_sim_v0_10,
  463:    cris_not_implemented_op},
  464: 
  465:   {"bne",
  466:    BRANCH_QUICK_OPCODE+CC_NE*0x1000,
  467:    0x0f00+(0xF-CC_NE)*0x1000,		  "o",	     1, SIZE_NONE,     0,
  468:    cris_eight_bit_offset_branch_op},
  469: 
  470:   {"bound",   0x05c0, 0x0A00,		  "m r,R",   0, SIZE_NONE,     0,
  471:    cris_two_operand_bound_op},
  472:   /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes.  */
  473:   {"bound",   0x09c0, 0x0200,		  "m s,R",   0, SIZE_FIELD,
  474:    cris_ver_v0_10,
  475:    cris_two_operand_bound_op},
  476:   /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes.  */
  477:   {"bound",   0x0dcf, 0x0200,		  "m Y,R",   0, SIZE_FIELD,    0,
  478:    cris_two_operand_bound_op},
  479:   {"bound",   0x09c0, 0x0200,		  "m S,D",   0, SIZE_NONE,
  480:    cris_ver_v0_10,
  481:    cris_two_operand_bound_op},
  482:   {"bound",   0x09c0, 0x0600,		  "m S,R,r", 0, SIZE_NONE,
  483:    cris_ver_v0_10,
  484:    cris_three_operand_bound_op},
  485: 
  486:   {"bpl",
  487:    BRANCH_QUICK_OPCODE+CC_PL*0x1000,
  488:    0x0f00+(0xF-CC_PL)*0x1000,		  "o",	     1, SIZE_NONE,     0,
  489:    cris_eight_bit_offset_branch_op},
  490: 
  491:   {"break",   0xe930, 0x16c0,		  "C",	     0, SIZE_NONE,
  492:    cris_ver_v3p,
  493:    cris_break_op},
  494: 
  495:   {"bsb",
  496:    BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
  497:    0x0f00+(0xF-CC_EXT)*0x1000,		  "o",	     1, SIZE_NONE,
  498:    cris_ver_v32p,
  499:    cris_eight_bit_offset_branch_op},
  500: 
  501:   {"bsr",     0xBEBF, 0x4140,		  "n",	     0, SIZE_FIX_32,
  502:    cris_ver_v32p,
  503:    cris_none_reg_mode_jump_op},
  504: 
  505:   {"bsrc",     0xBEFF, 0x4100,		  "n",	     0, SIZE_FIX_32,
  506:    cris_ver_v32p,
  507:    cris_none_reg_mode_jump_op},
  508: 
  509:   {"bstore",  0x0af0, 0x0100,		  "s,R",     0, SIZE_FIX_32,
  510:    cris_ver_warning,
  511:    cris_not_implemented_op},
  512: 
  513:   {"bstore",  0x0af0, 0x0100,		  "S,D",     0, SIZE_NONE,
  514:    cris_ver_warning,
  515:    cris_not_implemented_op},
  516: 
  517:   {"bstore",  0x0af0, 0x0500,		  "S,R,r",   0, SIZE_NONE,
  518:    cris_ver_warning,
  519:    cris_not_implemented_op},
  520: 
  521:   {"btst",    0x04F0, 0x0B00,		  "r,R",     0, SIZE_NONE,     0,
  522:    cris_btst_nop_op},
  523:   {"btstq",   0x0380, 0x0C60,		  "c,R",     0, SIZE_NONE,     0,
  524:    cris_btst_nop_op},
  525: 
  526:   {"bvc",
  527:    BRANCH_QUICK_OPCODE+CC_VC*0x1000,
  528:    0x0f00+(0xF-CC_VC)*0x1000,		  "o",	     1, SIZE_NONE,     0,
  529:    cris_eight_bit_offset_branch_op},
  530: 
  531:   {"bvs",
  532:    BRANCH_QUICK_OPCODE+CC_VS*0x1000,
  533:    0x0f00+(0xF-CC_VS)*0x1000,		  "o",	     1, SIZE_NONE,     0,
  534:    cris_eight_bit_offset_branch_op},
  535: 
  536:   {"clear",   0x0670, 0x3980,		  "M r",     0, SIZE_NONE,     0,
  537:    cris_reg_mode_clear_op},
  538: 
  539:   {"clear",   0x0A70, 0x3180,		  "M y",     0, SIZE_NONE,     0,
  540:    cris_none_reg_mode_clear_test_op},
  541: 
  542:   {"clear",   0x0A70, 0x3180,		  "M S",     0, SIZE_NONE,
  543:    cris_ver_v0_10,
  544:    cris_none_reg_mode_clear_test_op},
  545: 
  546:   {"clearf",  0x05F0, 0x0A00,		  "f",	     0, SIZE_NONE,     0,
  547:    cris_clearf_di_op},
  548: 
  549:   {"cmp",     0x06C0, 0x0900,		  "m r,R",   0, SIZE_NONE,     0,
  550:    cris_reg_mode_add_sub_cmp_and_or_move_op},
  551: 
  552:   {"cmp",     0x0Ac0, 0x0100,		  "m s,R",   0, SIZE_FIELD,    0,
  553:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
  554: 
  555:   {"cmp",     0x0Ac0, 0x0100,		  "m S,D",   0, SIZE_NONE,
  556:    cris_ver_v0_10,
  557:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
  558: 
  559:   {"cmpq",    0x02C0, 0x0D00,		  "i,R",     0, SIZE_NONE,     0,
  560:    cris_quick_mode_and_cmp_move_or_op},
  561: 
  562:   /* FIXME: SIZE_FIELD_SIGNED and all necessary changes.  */
  563:   {"cmps",    0x08e0, 0x0300,		  "z s,R",   0, SIZE_FIELD,    0,
  564:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
  565: 
  566:   {"cmps",    0x08e0, 0x0300,		  "z S,D",   0, SIZE_NONE,
  567:    cris_ver_v0_10,
  568:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
  569: 
  570:   /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes.  */
  571:   {"cmpu",    0x08c0, 0x0320,		  "z s,R" ,  0, SIZE_FIELD,    0,
  572:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
  573: 
  574:   {"cmpu",    0x08c0, 0x0320,		  "z S,D",   0, SIZE_NONE,
  575:    cris_ver_v0_10,
  576:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
  577: 
  578:   {"di",      0x25F0, 0xDA0F,		  "",	     0, SIZE_NONE,     0,
  579:    cris_clearf_di_op},
  580: 
  581:   {"dip",     DIP_OPCODE, DIP_Z_BITS,	  "ps",	     0, SIZE_FIX_32,
  582:    cris_ver_v0_10,
  583:    cris_dip_prefix},
  584: 
  585:   {"div",     0x0980, 0x0640,		  "m R,r",   0, SIZE_FIELD,    0,
  586:    cris_not_implemented_op},
  587: 
  588:   {"dstep",   0x06f0, 0x0900,		  "r,R",     0, SIZE_NONE,     0,
  589:    cris_dstep_logshift_mstep_neg_not_op},
  590: 
  591:   {"ei",      0x25B0, 0xDA4F,		  "",	     0, SIZE_NONE,     0,
  592:    cris_ax_ei_setf_op},
  593: 
  594:   {"fidxd",    0x0ab0, 0xf540,		  "[r]",     0, SIZE_NONE,
  595:    cris_ver_v32p,
  596:    cris_not_implemented_op},
  597: 
  598:   {"fidxi",    0x0d30, 0xF2C0,		  "[r]",     0, SIZE_NONE,
  599:    cris_ver_v32p,
  600:    cris_not_implemented_op},
  601: 
  602:   {"ftagd",    0x1AB0, 0xE540,		  "[r]",     0, SIZE_NONE,
  603:    cris_ver_v32p,
  604:    cris_not_implemented_op},
  605: 
  606:   {"ftagi",    0x1D30, 0xE2C0,		  "[r]",     0, SIZE_NONE,
  607:    cris_ver_v32p,
  608:    cris_not_implemented_op},
  609: 
  610:   {"halt",    0xF930, 0x06CF,		  "",	     0, SIZE_NONE,
  611:    cris_ver_v32p,
  612:    cris_not_implemented_op},
  613: 
  614:   {"jas",    0x09B0, 0x0640,		  "r,P",     0, SIZE_NONE,
  615:    cris_ver_v32p,
  616:    cris_reg_mode_jump_op},
  617: 
  618:   {"jas",    0x0DBF, 0x0240,		  "N,P",     0, SIZE_FIX_32,
  619:    cris_ver_v32p,
  620:    cris_reg_mode_jump_op},
  621: 
  622:   {"jasc",    0x0B30, 0x04C0,		  "r,P",     0, SIZE_NONE,
  623:    cris_ver_v32p,
  624:    cris_reg_mode_jump_op},
  625: 
  626:   {"jasc",    0x0F3F, 0x00C0,		  "N,P",     0, SIZE_FIX_32,
  627:    cris_ver_v32p,
  628:    cris_reg_mode_jump_op},
  629: 
  630:   {"jbrc",    0x69b0, 0x9640,		  "r",	     0, SIZE_NONE,
  631:    cris_ver_v8_10,
  632:    cris_reg_mode_jump_op},
  633: 
  634:   {"jbrc",    0x6930, 0x92c0,		  "s",	     0, SIZE_FIX_32,
  635:    cris_ver_v8_10,
  636:    cris_none_reg_mode_jump_op},
  637: 
  638:   {"jbrc",    0x6930, 0x92c0,		  "S",	     0, SIZE_NONE,
  639:    cris_ver_v8_10,
  640:    cris_none_reg_mode_jump_op},
  641: 
  642:   {"jir",     0xA9b0, 0x5640,		  "r",	     0, SIZE_NONE,
  643:    cris_ver_v8_10,
  644:    cris_reg_mode_jump_op},
  645: 
  646:   {"jir",     0xA930, 0x52c0,		  "s",	     0, SIZE_FIX_32,
  647:    cris_ver_v8_10,
  648:    cris_none_reg_mode_jump_op},
  649: 
  650:   {"jir",     0xA930, 0x52c0,		  "S",	     0, SIZE_NONE,
  651:    cris_ver_v8_10,
  652:    cris_none_reg_mode_jump_op},
  653: 
  654:   {"jirc",    0x29b0, 0xd640,		  "r",	     0, SIZE_NONE,
  655:    cris_ver_v8_10,
  656:    cris_reg_mode_jump_op},
  657: 
  658:   {"jirc",    0x2930, 0xd2c0,		  "s",	     0, SIZE_FIX_32,
  659:    cris_ver_v8_10,
  660:    cris_none_reg_mode_jump_op},
  661: 
  662:   {"jirc",    0x2930, 0xd2c0,		  "S",	     0, SIZE_NONE,
  663:    cris_ver_v8_10,
  664:    cris_none_reg_mode_jump_op},
  665: 
  666:   {"jsr",     0xB9b0, 0x4640,		  "r",	     0, SIZE_NONE,     0,
  667:    cris_reg_mode_jump_op},
  668: 
  669:   {"jsr",     0xB930, 0x42c0,		  "s",	     0, SIZE_FIX_32,
  670:    cris_ver_v0_10,
  671:    cris_none_reg_mode_jump_op},
  672: 
  673:   {"jsr",     0xBDBF, 0x4240,		  "N",	     0, SIZE_FIX_32,
  674:    cris_ver_v32p,
  675:    cris_none_reg_mode_jump_op},
  676: 
  677:   {"jsr",     0xB930, 0x42c0,		  "S",	     0, SIZE_NONE,
  678:    cris_ver_v0_10,
  679:    cris_none_reg_mode_jump_op},
  680: 
  681:   {"jsrc",    0x39b0, 0xc640,		  "r",	     0, SIZE_NONE,
  682:    cris_ver_v8_10,
  683:    cris_reg_mode_jump_op},
  684: 
  685:   {"jsrc",    0x3930, 0xc2c0,		  "s",	     0, SIZE_FIX_32,
  686:    cris_ver_v8_10,
  687:    cris_none_reg_mode_jump_op},
  688: 
  689:   {"jsrc",    0x3930, 0xc2c0,		  "S",	     0, SIZE_NONE,
  690:    cris_ver_v8_10,
  691:    cris_none_reg_mode_jump_op},
  692: 
  693:   {"jsrc",    0xBB30, 0x44C0,		  "r",       0, SIZE_NONE,
  694:    cris_ver_v32p,
  695:    cris_reg_mode_jump_op},
  696: 
  697:   {"jsrc",    0xBF3F, 0x40C0,		  "N",	     0, SIZE_FIX_32,
  698:    cris_ver_v32p,
  699:    cris_reg_mode_jump_op},
  700: 
  701:   {"jump",    0x09b0, 0xF640,		  "r",	     0, SIZE_NONE,     0,
  702:    cris_reg_mode_jump_op},
  703: 
  704:   {"jump",
  705:    JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS,  "s",	     0, SIZE_FIX_32,
  706:    cris_ver_v0_10,
  707:    cris_none_reg_mode_jump_op},
  708: 
  709:   {"jump",
  710:    JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS,  "S",	     0, SIZE_NONE,
  711:    cris_ver_v0_10,
  712:    cris_none_reg_mode_jump_op},
  713: 
  714:   {"jump",    0x09F0, 0x060F,		  "P",	     0, SIZE_NONE,
  715:    cris_ver_v32p,
  716:    cris_none_reg_mode_jump_op},
  717: 
  718:   {"jump",
  719:    JUMP_PC_INCR_OPCODE_V32,
  720:    (0xffff & ~JUMP_PC_INCR_OPCODE_V32),	  "N",	     0, SIZE_FIX_32,
  721:    cris_ver_v32p,
  722:    cris_none_reg_mode_jump_op},
  723: 
  724:   {"jmpu",    0x8930, 0x72c0,		  "s",	     0, SIZE_FIX_32,
  725:    cris_ver_v10,
  726:    cris_none_reg_mode_jump_op},
  727: 
  728:   {"jmpu",    0x8930, 0x72c0,		   "S",	     0, SIZE_NONE,
  729:    cris_ver_v10,
  730:    cris_none_reg_mode_jump_op},
  731: 
  732:   {"lapc",    0x0970, 0x0680,		  "U,R",    0, SIZE_NONE,
  733:    cris_ver_v32p,
  734:    cris_not_implemented_op},
  735: 
  736:   {"lapc",    0x0D7F, 0x0280,		  "dn,R",    0, SIZE_FIX_32,
  737:    cris_ver_v32p,
  738:    cris_not_implemented_op},
  739: 
  740:   {"lapcq",   0x0970, 0x0680,		  "u,R",     0, SIZE_NONE,
  741:    cris_ver_v32p,
  742:    cris_addi_op},
  743: 
  744:   {"lsl",     0x04C0, 0x0B00,		  "m r,R",   0, SIZE_NONE,     0,
  745:    cris_dstep_logshift_mstep_neg_not_op},
  746: 
  747:   {"lslq",    0x03c0, 0x0C20,		  "c,R",     0, SIZE_NONE,     0,
  748:    cris_dstep_logshift_mstep_neg_not_op},
  749: 
  750:   {"lsr",     0x07C0, 0x0800,		  "m r,R",   0, SIZE_NONE,     0,
  751:    cris_dstep_logshift_mstep_neg_not_op},
  752: 
  753:   {"lsrq",    0x03e0, 0x0C00,		  "c,R",     0, SIZE_NONE,     0,
  754:    cris_dstep_logshift_mstep_neg_not_op},
  755: 
  756:   {"lz",      0x0730, 0x08C0,		  "r,R",     0, SIZE_NONE,
  757:    cris_ver_v3p,
  758:    cris_not_implemented_op},
  759: 
  760:   {"mcp",      0x07f0, 0x0800,		  "P,r",     0, SIZE_NONE,
  761:    cris_ver_v32p,
  762:    cris_not_implemented_op},
  763: 
  764:   {"move",    0x0640, 0x0980,		  "m r,R",   0, SIZE_NONE,     0,
  765:    cris_reg_mode_add_sub_cmp_and_or_move_op},
  766: 
  767:   {"move",    0x0A40, 0x0180,		  "m s,R",   0, SIZE_FIELD,    0,
  768:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
  769: 
  770:   {"move",    0x0A40, 0x0180,		  "m S,D",   0, SIZE_NONE,
  771:    cris_ver_v0_10,
  772:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
  773: 
  774:   {"move",    0x0630, 0x09c0,		  "r,P",     0, SIZE_NONE,     0,
  775:    cris_move_to_preg_op},
  776: 
  777:   {"move",    0x0670, 0x0980,		  "P,r",     0, SIZE_NONE,     0,
  778:    cris_reg_mode_move_from_preg_op},
  779: 
  780:   {"move",    0x0BC0, 0x0000,		  "m R,y",   0, SIZE_FIELD,    0,
  781:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
  782: 
  783:   {"move",    0x0BC0, 0x0000,		  "m D,S",   0, SIZE_NONE,
  784:    cris_ver_v0_10,
  785:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
  786: 
  787:   {"move",
  788:    MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS,
  789:    "s,P",   0, SIZE_SPEC_REG, 0,
  790:    cris_move_to_preg_op},
  791: 
  792:   {"move",    0x0A30, 0x01c0,		  "S,P",     0, SIZE_NONE,
  793:    cris_ver_v0_10,
  794:    cris_move_to_preg_op},
  795: 
  796:   {"move",    0x0A70, 0x0180,		  "P,y",     0, SIZE_SPEC_REG, 0,
  797:    cris_none_reg_mode_move_from_preg_op},
  798: 
  799:   {"move",    0x0A70, 0x0180,		  "P,S",     0, SIZE_NONE,
  800:    cris_ver_v0_10,
  801:    cris_none_reg_mode_move_from_preg_op},
  802: 
  803:   {"move",    0x0B70, 0x0480,		  "r,T",     0, SIZE_NONE,
  804:    cris_ver_v32p,
  805:    cris_not_implemented_op},
  806: 
  807:   {"move",    0x0F70, 0x0080,		  "T,r",     0, SIZE_NONE,
  808:    cris_ver_v32p,
  809:    cris_not_implemented_op},
  810: 
  811:   {"movem",   0x0BF0, 0x0000,		  "R,y",     0, SIZE_FIX_32,   0,
  812:    cris_move_reg_to_mem_movem_op},
  813: 
  814:   {"movem",   0x0BF0, 0x0000,		  "D,S",     0, SIZE_NONE,
  815:    cris_ver_v0_10,
  816:    cris_move_reg_to_mem_movem_op},
  817: 
  818:   {"movem",   0x0BB0, 0x0040,		  "s,R",     0, SIZE_FIX_32,   0,
  819:    cris_move_mem_to_reg_movem_op},
  820: 
  821:   {"movem",   0x0BB0, 0x0040,		  "S,D",     0, SIZE_NONE,
  822:    cris_ver_v0_10,
  823:    cris_move_mem_to_reg_movem_op},
  824: 
  825:   {"moveq",   0x0240, 0x0D80,		  "i,R",     0, SIZE_NONE,     0,
  826:    cris_quick_mode_and_cmp_move_or_op},
  827: 
  828:   {"movs",    0x0460, 0x0B80,		  "z r,R",   0, SIZE_NONE,     0,
  829:    cris_reg_mode_add_sub_cmp_and_or_move_op},
  830: 
  831:   /* FIXME: SIZE_FIELD_SIGNED and all necessary changes.  */
  832:   {"movs",    0x0860, 0x0380,		  "z s,R",   0, SIZE_FIELD,    0,
  833:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
  834: 
  835:   {"movs",    0x0860, 0x0380,		  "z S,D",   0, SIZE_NONE,
  836:    cris_ver_v0_10,
  837:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
  838: 
  839:   {"movu",    0x0440, 0x0Ba0,		  "z r,R",   0, SIZE_NONE,     0,
  840:    cris_reg_mode_add_sub_cmp_and_or_move_op},
  841: 
  842:   /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes.  */
  843:   {"movu",    0x0840, 0x03a0,		  "z s,R",   0, SIZE_FIELD,    0,
  844:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
  845: 
  846:   {"movu",    0x0840, 0x03a0,		  "z S,D",   0, SIZE_NONE,
  847:    cris_ver_v0_10,
  848:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
  849: 
  850:   {"mstep",   0x07f0, 0x0800,		  "r,R",     0, SIZE_NONE,
  851:    cris_ver_v0_10,
  852:    cris_dstep_logshift_mstep_neg_not_op},
  853: 
  854:   {"muls",    0x0d00, 0x02c0,		  "m r,R",   0, SIZE_NONE,
  855:    cris_ver_v10p,
  856:    cris_muls_op},
  857: 
  858:   {"mulu",    0x0900, 0x06c0,		  "m r,R",   0, SIZE_NONE,
  859:    cris_ver_v10p,
  860:    cris_mulu_op},
  861: 
  862:   {"neg",     0x0580, 0x0A40,		  "m r,R",   0, SIZE_NONE,     0,
  863:    cris_dstep_logshift_mstep_neg_not_op},
  864: 
  865:   {"nop",     NOP_OPCODE, NOP_Z_BITS,	  "",	     0, SIZE_NONE,
  866:    cris_ver_v0_10,
  867:    cris_btst_nop_op},
  868: 
  869:   {"nop",     NOP_OPCODE_V32, NOP_Z_BITS_V32, "",    0, SIZE_NONE,
  870:    cris_ver_v32p,
  871:    cris_btst_nop_op},
  872: 
  873:   {"not",     0x8770, 0x7880,		  "r",	     0, SIZE_NONE,     0,
  874:    cris_dstep_logshift_mstep_neg_not_op},
  875: 
  876:   {"or",      0x0740, 0x0880,		  "m r,R",   0, SIZE_NONE,     0,
  877:    cris_reg_mode_add_sub_cmp_and_or_move_op},
  878: 
  879:   {"or",      0x0B40, 0x0080,		  "m s,R",   0, SIZE_FIELD,    0,
  880:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
  881: 
  882:   {"or",      0x0B40, 0x0080,		  "m S,D",   0, SIZE_NONE,
  883:    cris_ver_v0_10,
  884:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
  885: 
  886:   {"or",      0x0B40, 0x0480,		  "m S,R,r", 0, SIZE_NONE,
  887:    cris_ver_v0_10,
  888:    cris_three_operand_add_sub_cmp_and_or_op},
  889: 
  890:   {"orq",     0x0340, 0x0C80,		  "i,R",     0, SIZE_NONE,     0,
  891:    cris_quick_mode_and_cmp_move_or_op},
  892: 
  893:   {"pop",     0x0E6E, 0x0191,		  "!R",	     0, SIZE_NONE,
  894:    cris_ver_v0_10,
  895:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
  896: 
  897:   {"pop",     0x0e3e, 0x01c1,		  "!P",	     0, SIZE_NONE,
  898:    cris_ver_v0_10,
  899:    cris_none_reg_mode_move_from_preg_op},
  900: 
  901:   {"push",    0x0FEE, 0x0011,		  "BR",	     0, SIZE_NONE,
  902:    cris_ver_v0_10,
  903:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
  904: 
  905:   {"push",    0x0E7E, 0x0181,		  "BP",	     0, SIZE_NONE,
  906:    cris_ver_v0_10,
  907:    cris_move_to_preg_op},
  908: 
  909:   {"rbf",     0x3b30, 0xc0c0,		  "y",	     0, SIZE_NONE,
  910:    cris_ver_v10,
  911:    cris_not_implemented_op},
  912: 
  913:   {"rbf",     0x3b30, 0xc0c0,		  "S",	     0, SIZE_NONE,
  914:    cris_ver_v10,
  915:    cris_not_implemented_op},
  916: 
  917:   {"rfe",     0x2930, 0xD6CF,		  "",	     0, SIZE_NONE,
  918:    cris_ver_v32p,
  919:    cris_not_implemented_op},
  920: 
  921:   {"rfg",     0x4930, 0xB6CF,		  "",	     0, SIZE_NONE,
  922:    cris_ver_v32p,
  923:    cris_not_implemented_op},
  924: 
  925:   {"rfn",     0x5930, 0xA6CF,		  "",	     0, SIZE_NONE,
  926:    cris_ver_v32p,
  927:    cris_not_implemented_op},
  928: 
  929:   {"ret",     0xB67F, 0x4980,		  "",	     1, SIZE_NONE,
  930:    cris_ver_v0_10,
  931:    cris_reg_mode_move_from_preg_op},
  932: 
  933:   {"ret",     0xB9F0, 0x460F,		  "",	     1, SIZE_NONE,
  934:    cris_ver_v32p,
  935:    cris_reg_mode_move_from_preg_op},
  936: 
  937:   {"retb",    0xe67f, 0x1980,		  "",	     1, SIZE_NONE,
  938:    cris_ver_v0_10,
  939:    cris_reg_mode_move_from_preg_op},
  940: 
  941:   {"rete",     0xA9F0, 0x560F,		  "",	     1, SIZE_NONE,
  942:    cris_ver_v32p,
  943:    cris_reg_mode_move_from_preg_op},
  944: 
  945:   {"reti",    0xA67F, 0x5980,		  "",	     1, SIZE_NONE,
  946:    cris_ver_v0_10,
  947:    cris_reg_mode_move_from_preg_op},
  948: 
  949:   {"retn",     0xC9F0, 0x360F,		  "",	     1, SIZE_NONE,
  950:    cris_ver_v32p,
  951:    cris_reg_mode_move_from_preg_op},
  952: 
  953:   {"sbfs",    0x3b70, 0xc080,		  "y",	     0, SIZE_NONE,
  954:    cris_ver_v10,
  955:    cris_not_implemented_op},
  956: 
  957:   {"sbfs",    0x3b70, 0xc080,		  "S",	     0, SIZE_NONE,
  958:    cris_ver_v10,
  959:    cris_not_implemented_op},
  960: 
  961:   {"sa",
  962:    0x0530+CC_A*0x1000,
  963:    0x0AC0+(0xf-CC_A)*0x1000,		  "r",	     0, SIZE_NONE,     0,
  964:    cris_scc_op},
  965: 
  966:   {"ssb",
  967:    0x0530+CC_EXT*0x1000,
  968:    0x0AC0+(0xf-CC_EXT)*0x1000,		  "r",	     0, SIZE_NONE,
  969:    cris_ver_v32p,
  970:    cris_scc_op},
  971: 
  972:   {"scc",
  973:    0x0530+CC_CC*0x1000,
  974:    0x0AC0+(0xf-CC_CC)*0x1000,		  "r",	     0, SIZE_NONE,     0,
  975:    cris_scc_op},
  976: 
  977:   {"scs",
  978:    0x0530+CC_CS*0x1000,
  979:    0x0AC0+(0xf-CC_CS)*0x1000,		  "r",	     0, SIZE_NONE,     0,
  980:    cris_scc_op},
  981: 
  982:   {"seq",
  983:    0x0530+CC_EQ*0x1000,
  984:    0x0AC0+(0xf-CC_EQ)*0x1000,		  "r",	     0, SIZE_NONE,     0,
  985:    cris_scc_op},
  986: 
  987:   {"setf",    0x05b0, 0x0A40,		  "f",	     0, SIZE_NONE,     0,
  988:    cris_ax_ei_setf_op},
  989: 
  990:   {"sfe",    0x3930, 0xC6CF,		  "",	     0, SIZE_NONE,
  991:    cris_ver_v32p,
  992:    cris_not_implemented_op},
  993: 
  994:   /* Need to have "swf" in front of "sext" so it is the one displayed in
  995:      disassembly.  */
  996:   {"swf",
  997:    0x0530+CC_EXT*0x1000,
  998:    0x0AC0+(0xf-CC_EXT)*0x1000,		  "r",	     0, SIZE_NONE,
  999:    cris_ver_v10,
 1000:    cris_scc_op},
 1001: 
 1002:   {"sext",
 1003:    0x0530+CC_EXT*0x1000,
 1004:    0x0AC0+(0xf-CC_EXT)*0x1000,		  "r",	     0, SIZE_NONE,
 1005:    cris_ver_v0_3,
 1006:    cris_scc_op},
 1007: 
 1008:   {"sge",
 1009:    0x0530+CC_GE*0x1000,
 1010:    0x0AC0+(0xf-CC_GE)*0x1000,		  "r",	     0, SIZE_NONE,     0,
 1011:    cris_scc_op},
 1012: 
 1013:   {"sgt",
 1014:    0x0530+CC_GT*0x1000,
 1015:    0x0AC0+(0xf-CC_GT)*0x1000,		  "r",	     0, SIZE_NONE,     0,
 1016:    cris_scc_op},
 1017: 
 1018:   {"shi",
 1019:    0x0530+CC_HI*0x1000,
 1020:    0x0AC0+(0xf-CC_HI)*0x1000,		  "r",	     0, SIZE_NONE,     0,
 1021:    cris_scc_op},
 1022: 
 1023:   {"shs",
 1024:    0x0530+CC_HS*0x1000,
 1025:    0x0AC0+(0xf-CC_HS)*0x1000,		  "r",	     0, SIZE_NONE,     0,
 1026:    cris_scc_op},
 1027: 
 1028:   {"sle",
 1029:    0x0530+CC_LE*0x1000,
 1030:    0x0AC0+(0xf-CC_LE)*0x1000,		  "r",	     0, SIZE_NONE,     0,
 1031:    cris_scc_op},
 1032: 
 1033:   {"slo",
 1034:    0x0530+CC_LO*0x1000,
 1035:    0x0AC0+(0xf-CC_LO)*0x1000,		  "r",	     0, SIZE_NONE,     0,
 1036:    cris_scc_op},
 1037: 
 1038:   {"sls",
 1039:    0x0530+CC_LS*0x1000,
 1040:    0x0AC0+(0xf-CC_LS)*0x1000,		  "r",	     0, SIZE_NONE,     0,
 1041:    cris_scc_op},
 1042: 
 1043:   {"slt",
 1044:    0x0530+CC_LT*0x1000,
 1045:    0x0AC0+(0xf-CC_LT)*0x1000,		  "r",	     0, SIZE_NONE,     0,
 1046:    cris_scc_op},
 1047: 
 1048:   {"smi",
 1049:    0x0530+CC_MI*0x1000,
 1050:    0x0AC0+(0xf-CC_MI)*0x1000,		  "r",	     0, SIZE_NONE,     0,
 1051:    cris_scc_op},
 1052: 
 1053:   {"sne",
 1054:    0x0530+CC_NE*0x1000,
 1055:    0x0AC0+(0xf-CC_NE)*0x1000,		  "r",	     0, SIZE_NONE,     0,
 1056:    cris_scc_op},
 1057: 
 1058:   {"spl",
 1059:    0x0530+CC_PL*0x1000,
 1060:    0x0AC0+(0xf-CC_PL)*0x1000,		  "r",	     0, SIZE_NONE,     0,
 1061:    cris_scc_op},
 1062: 
 1063:   {"sub",     0x0680, 0x0940,		  "m r,R",   0, SIZE_NONE,     0,
 1064:    cris_reg_mode_add_sub_cmp_and_or_move_op},
 1065: 
 1066:   {"sub",     0x0a80, 0x0140,		  "m s,R",   0, SIZE_FIELD,    0,
 1067:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
 1068: 
 1069:   {"sub",     0x0a80, 0x0140,		  "m S,D",   0, SIZE_NONE,
 1070:    cris_ver_v0_10,
 1071:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
 1072: 
 1073:   {"sub",     0x0a80, 0x0540,		  "m S,R,r", 0, SIZE_NONE,
 1074:    cris_ver_v0_10,
 1075:    cris_three_operand_add_sub_cmp_and_or_op},
 1076: 
 1077:   {"subq",    0x0280, 0x0d40,		  "I,R",     0, SIZE_NONE,     0,
 1078:    cris_quick_mode_add_sub_op},
 1079: 
 1080:   {"subs",    0x04a0, 0x0b40,		  "z r,R",   0, SIZE_NONE,     0,
 1081:    cris_reg_mode_add_sub_cmp_and_or_move_op},
 1082: 
 1083:   /* FIXME: SIZE_FIELD_SIGNED and all necessary changes.  */
 1084:   {"subs",    0x08a0, 0x0340,		  "z s,R",   0, SIZE_FIELD,    0,
 1085:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
 1086: 
 1087:   {"subs",    0x08a0, 0x0340,		  "z S,D",   0, SIZE_NONE,
 1088:    cris_ver_v0_10,
 1089:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
 1090: 
 1091:   {"subs",    0x08a0, 0x0740,		  "z S,R,r", 0, SIZE_NONE,
 1092:    cris_ver_v0_10,
 1093:    cris_three_operand_add_sub_cmp_and_or_op},
 1094: 
 1095:   {"subu",    0x0480, 0x0b60,		  "z r,R",   0, SIZE_NONE,     0,
 1096:    cris_reg_mode_add_sub_cmp_and_or_move_op},
 1097: 
 1098:   /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes.  */
 1099:   {"subu",    0x0880, 0x0360,		  "z s,R",   0, SIZE_FIELD,    0,
 1100:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
 1101: 
 1102:   {"subu",    0x0880, 0x0360,		  "z S,D",   0, SIZE_NONE,
 1103:    cris_ver_v0_10,
 1104:    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
 1105: 
 1106:   {"subu",    0x0880, 0x0760,		  "z S,R,r", 0, SIZE_NONE,
 1107:    cris_ver_v0_10,
 1108:    cris_three_operand_add_sub_cmp_and_or_op},
 1109: 
 1110:   {"svc",
 1111:    0x0530+CC_VC*0x1000,
 1112:    0x0AC0+(0xf-CC_VC)*0x1000,		  "r",	     0, SIZE_NONE,     0,
 1113:    cris_scc_op},
 1114: 
 1115:   {"svs",
 1116:    0x0530+CC_VS*0x1000,
 1117:    0x0AC0+(0xf-CC_VS)*0x1000,		  "r",	     0, SIZE_NONE,     0,
 1118:    cris_scc_op},
 1119: 
 1120:   /* The insn "swapn" is the same as "not" and will be disassembled as
 1121:      such, but the swap* family of mnmonics are generally v8-and-higher
 1122:      only, so count it in.  */
 1123:   {"swapn",   0x8770, 0x7880,		  "r",	     0, SIZE_NONE,
 1124:    cris_ver_v8p,
 1125:    cris_not_implemented_op},
 1126: 
 1127:   {"swapw",   0x4770, 0xb880,		  "r",	     0, SIZE_NONE,
 1128:    cris_ver_v8p,
 1129:    cris_not_implemented_op},
 1130: 
 1131:   {"swapnw",  0xc770, 0x3880,		  "r",	     0, SIZE_NONE,
 1132:    cris_ver_v8p,
 1133:    cris_not_implemented_op},
 1134: 
 1135:   {"swapb",   0x2770, 0xd880,		  "r",	     0, SIZE_NONE,
 1136:    cris_ver_v8p,
 1137:    cris_not_implemented_op},
 1138: 
 1139:   {"swapnb",  0xA770, 0x5880,		  "r",	     0, SIZE_NONE,
 1140:    cris_ver_v8p,
 1141:    cris_not_implemented_op},
 1142: 
 1143:   {"swapwb",  0x6770, 0x9880,		  "r",	     0, SIZE_NONE,
 1144:    cris_ver_v8p,
 1145:    cris_not_implemented_op},
 1146: 
 1147:   {"swapnwb", 0xE770, 0x1880,		  "r",	     0, SIZE_NONE,
 1148:    cris_ver_v8p,
 1149:    cris_not_implemented_op},
 1150: 
 1151:   {"swapr",   0x1770, 0xe880,		  "r",	     0, SIZE_NONE,
 1152:    cris_ver_v8p,
 1153:    cris_not_implemented_op},
 1154: 
 1155:   {"swapnr",  0x9770, 0x6880,		  "r",	     0, SIZE_NONE,
 1156:    cris_ver_v8p,
 1157:    cris_not_implemented_op},
 1158: 
 1159:   {"swapwr",  0x5770, 0xa880,		  "r",	     0, SIZE_NONE,
 1160:    cris_ver_v8p,
 1161:    cris_not_implemented_op},
 1162: 
 1163:   {"swapnwr", 0xd770, 0x2880,		  "r",	     0, SIZE_NONE,
 1164:    cris_ver_v8p,
 1165:    cris_not_implemented_op},
 1166: 
 1167:   {"swapbr",  0x3770, 0xc880,		  "r",	     0, SIZE_NONE,
 1168:    cris_ver_v8p,
 1169:    cris_not_implemented_op},
 1170: 
 1171:   {"swapnbr", 0xb770, 0x4880,		  "r",	     0, SIZE_NONE,
 1172:    cris_ver_v8p,
 1173:    cris_not_implemented_op},
 1174: 
 1175:   {"swapwbr", 0x7770, 0x8880,		  "r",	     0, SIZE_NONE,
 1176:    cris_ver_v8p,
 1177:    cris_not_implemented_op},
 1178: 
 1179:   {"swapnwbr", 0xf770, 0x0880,		  "r",	     0, SIZE_NONE,
 1180:    cris_ver_v8p,
 1181:    cris_not_implemented_op},
 1182: 
 1183:   {"test",    0x0640, 0x0980,		  "m D",     0, SIZE_NONE,
 1184:    cris_ver_v0_10,
 1185:    cris_reg_mode_test_op},
 1186: 
 1187:   {"test",    0x0b80, 0xf040,		  "m y",     0, SIZE_FIELD,    0,
 1188:    cris_none_reg_mode_clear_test_op},
 1189: 
 1190:   {"test",    0x0b80, 0xf040,		  "m S",     0, SIZE_NONE,
 1191:    cris_ver_v0_10,
 1192:    cris_none_reg_mode_clear_test_op},
 1193: 
 1194:   {"xor",     0x07B0, 0x0840,		  "r,R",     0, SIZE_NONE,     0,
 1195:    cris_xor_op},
 1196: 
 1197:   {NULL, 0, 0, NULL, 0, 0, 0, cris_not_implemented_op}
 1198: };
 1199: 
 1200: /* Condition-names, indexed by the CC_* numbers as found in cris.h. */
 1201: const char * const
 1202: cris_cc_strings[] =
 1203: {
 1204:   "hs",
 1205:   "lo",
 1206:   "ne",
 1207:   "eq",
 1208:   "vc",
 1209:   "vs",
 1210:   "pl",
 1211:   "mi",
 1212:   "ls",
 1213:   "hi",
 1214:   "ge",
 1215:   "lt",
 1216:   "gt",
 1217:   "le",
 1218:   "a",
 1219:   /* This is a placeholder.  In v0, this would be "ext".  In v32, this
 1220:      is "sb".  See cris_conds15.  */
 1221:   "wf"
 1222: };
 1223: 
 1224: /* Different names and semantics for condition 1111 (0xf).  */
 1225: const struct cris_cond15 cris_cond15s[] =
 1226: {
 1227:   /* FIXME: In what version did condition "ext" disappear?  */
 1228:   {"ext", cris_ver_v0_3},
 1229:   {"wf", cris_ver_v10},
 1230:   {"sb", cris_ver_v32p},
 1231:   {NULL, 0}
 1232: };
 1233: 
 1234: 
 1235: /*
 1236:  * Local variables:
 1237:  * eval: (c-set-style "gnu")
 1238:  * indent-tabs-mode: t
 1239:  * End:
 1240:  */
 1241: 
 1242: 
 1243: /* No instruction will be disassembled longer than this.  In theory, and
 1244:    in silicon, address prefixes can be cascaded.  In practice, cascading
 1245:    is not used by GCC, and not supported by the assembler.  */
 1246: #ifndef MAX_BYTES_PER_CRIS_INSN
 1247: #define MAX_BYTES_PER_CRIS_INSN 8
 1248: #endif
 1249: 
 1250: /* Whether or not to decode prefixes, folding it into the following
 1251:    instruction.  FIXME: Make this optional later.  */
 1252: #ifndef PARSE_PREFIX
 1253: #define PARSE_PREFIX 1
 1254: #endif
 1255: 
 1256: /* Sometimes we prefix all registers with this character.  */
 1257: #define REGISTER_PREFIX_CHAR '$'
 1258: 
 1259: /* Whether or not to trace the following sequence:
 1260:    sub* X,r%d
 1261:    bound* Y,r%d
 1262:    adds.w [pc+r%d.w],pc
 1263: 
 1264:    This is the assembly form of a switch-statement in C.
 1265:    The "sub is optional.  If there is none, then X will be zero.
 1266:    X is the value of the first case,
 1267:    Y is the number of cases (including default).
 1268: 
 1269:    This results in case offsets printed on the form:
 1270:     case N: -> case_address
 1271:    where N is an estimation on the corresponding 'case' operand in C,
 1272:    and case_address is where execution of that case continues after the
 1273:    sequence presented above.
 1274: 
 1275:    The old style of output was to print the offsets as instructions,
 1276:    which made it hard to follow "case"-constructs in the disassembly,
 1277:    and caused a lot of annoying warnings about undefined instructions.
 1278: 
 1279:    FIXME: Make this optional later.  */
 1280: #ifndef TRACE_CASE
 1281: #define TRACE_CASE (disdata->trace_case)
 1282: #endif
 1283: 
 1284: enum cris_disass_family
 1285:  { cris_dis_v0_v10, cris_dis_common_v10_v32, cris_dis_v32 };
 1286: 
 1287: /* Stored in the disasm_info->private_data member.  */
 1288: struct cris_disasm_data
 1289: {
 1290:   /* Whether to print something less confusing if we find something
 1291:      matching a switch-construct.  */
 1292:   bfd_boolean trace_case;
 1293: 
 1294:   /* Whether this code is flagged as crisv32.  FIXME: Should be an enum
 1295:      that includes "compatible".  */
 1296:   enum cris_disass_family distype;
 1297: };
 1298: 
 1299: /* Value of first element in switch.  */
 1300: static long case_offset = 0;
 1301: 
 1302: /* How many more case-offsets to print.  */
 1303: static long case_offset_counter = 0;
 1304: 
 1305: /* Number of case offsets.  */
 1306: static long no_of_case_offsets = 0;
 1307: 
 1308: /* Candidate for next case_offset.  */
 1309: static long last_immediate = 0;
 1310: 
 1311: static int cris_constraint
 1312:   (const char *, unsigned, unsigned, struct cris_disasm_data *);
 1313: 
 1314: /* Parse disassembler options and store state in info.  FIXME: For the
 1315:    time being, we abuse static variables.  */
 1316: 
 1317: static bfd_boolean
 1318: cris_parse_disassembler_options (disassemble_info *info,
 1319: 				 enum cris_disass_family distype)
 1320: {
 1321:   struct cris_disasm_data *disdata;
 1322: 
 1323:   info->private_data = calloc (1, sizeof (struct cris_disasm_data));
 1324:   disdata = (struct cris_disasm_data *) info->private_data;
 1325:   if (disdata == NULL)
 1326:     return FALSE;
 1327: 
 1328:   /* Default true.  */
 1329:   disdata->trace_case
 1330:     = (info->disassembler_options == NULL
 1331:        || (strcmp (info->disassembler_options, "nocase") != 0));
 1332: 
 1333:   disdata->distype = distype;
 1334:   return TRUE;
 1335: }
 1336: 
 1337: static const struct cris_spec_reg *
 1338: spec_reg_info (unsigned int sreg, enum cris_disass_family distype)
 1339: {
 1340:   int i;
 1341: 
 1342:   for (i = 0; cris_spec_regs[i].name != NULL; i++)
 1343:     {
 1344:       if (cris_spec_regs[i].number == sreg)
 1345: 	{
 1346: 	  if (distype == cris_dis_v32)
 1347: 	    switch (cris_spec_regs[i].applicable_version)
 1348: 	      {
 1349: 	      case cris_ver_warning:
 1350: 	      case cris_ver_version_all:
 1351: 	      case cris_ver_v3p:
 1352: 	      case cris_ver_v8p:
 1353: 	      case cris_ver_v10p:
 1354: 	      case cris_ver_v32p:
 1355: 		/* No ambiguous sizes or register names with CRISv32.  */
 1356: 		if (cris_spec_regs[i].warning == NULL)
 1357: 		  return &cris_spec_regs[i];
 1358: 	      default:
 1359: 		;
 1360: 	      }
 1361: 	  else if (cris_spec_regs[i].applicable_version != cris_ver_v32p)
 1362: 	    return &cris_spec_regs[i];
 1363: 	}
 1364:     }
 1365: 
 1366:   return NULL;
 1367: }
 1368: 
 1369: /* Return the number of bits in the argument.  */
 1370: 
 1371: static int
 1372: number_of_bits (unsigned int val)
 1373: {
 1374:   int bits;
 1375: 
 1376:   for (bits = 0; val != 0; val &= val - 1)
 1377:     bits++;
 1378: 
 1379:   return bits;
 1380: }
 1381: 
 1382: /* Get an entry in the opcode-table.  */
 1383: 
 1384: static const struct cris_opcode *
 1385: get_opcode_entry (unsigned int insn,
 1386: 		  unsigned int prefix_insn,
 1387: 		  struct cris_disasm_data *disdata)
 1388: {
 1389:   /* For non-prefixed insns, we keep a table of pointers, indexed by the
 1390:      insn code.  Each entry is initialized when found to be NULL.  */
 1391:   static const struct cris_opcode **opc_table = NULL;
 1392: 
 1393:   const struct cris_opcode *max_matchedp = NULL;
 1394:   const struct cris_opcode **prefix_opc_table = NULL;
 1395: 
 1396:   /* We hold a table for each prefix that need to be handled differently.  */
 1397:   static const struct cris_opcode **dip_prefixes = NULL;
 1398:   static const struct cris_opcode **bdapq_m1_prefixes = NULL;
 1399:   static const struct cris_opcode **bdapq_m2_prefixes = NULL;
 1400:   static const struct cris_opcode **bdapq_m4_prefixes = NULL;
 1401:   static const struct cris_opcode **rest_prefixes = NULL;
 1402: 
 1403:   /* Allocate and clear the opcode-table.  */
 1404:   if (opc_table == NULL)
 1405:     {
 1406:       opc_table = qemu_malloc (65536 * sizeof (opc_table[0]));
 1407: 
 1408:       memset (opc_table, 0, 65536 * sizeof (const struct cris_opcode *));
 1409: 
 1410:       dip_prefixes
 1411: 	= qemu_malloc (65536 * sizeof (const struct cris_opcode **));
 1412: 
 1413:       memset (dip_prefixes, 0, 65536 * sizeof (dip_prefixes[0]));
 1414: 
 1415:       bdapq_m1_prefixes
 1416: 	= qemu_malloc (65536 * sizeof (const struct cris_opcode **));
 1417: 
 1418:       memset (bdapq_m1_prefixes, 0, 65536 * sizeof (bdapq_m1_prefixes[0]));
 1419: 
 1420:       bdapq_m2_prefixes
 1421: 	= qemu_malloc (65536 * sizeof (const struct cris_opcode **));
 1422: 
 1423:       memset (bdapq_m2_prefixes, 0, 65536 * sizeof (bdapq_m2_prefixes[0]));
 1424: 
 1425:       bdapq_m4_prefixes
 1426: 	= qemu_malloc (65536 * sizeof (const struct cris_opcode **));
 1427: 
 1428:       memset (bdapq_m4_prefixes, 0, 65536 * sizeof (bdapq_m4_prefixes[0]));
 1429: 
 1430:       rest_prefixes
 1431: 	= qemu_malloc (65536 * sizeof (const struct cris_opcode **));
 1432: 
 1433:       memset (rest_prefixes, 0, 65536 * sizeof (rest_prefixes[0]));
 1434:     }
 1435: 
 1436:   /* Get the right table if this is a prefix.
 1437:      This code is connected to cris_constraints in that it knows what
 1438:      prefixes play a role in recognition of patterns; the necessary
 1439:      state is reflected by which table is used.  If constraints
 1440:      involving match or non-match of prefix insns are changed, then this
 1441:      probably needs changing too.  */
 1442:   if (prefix_insn != NO_CRIS_PREFIX)
 1443:     {
 1444:       const struct cris_opcode *popcodep
 1445: 	= (opc_table[prefix_insn] != NULL
 1446: 	   ? opc_table[prefix_insn]
 1447: 	   : get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata));
 1448: 
 1449:       if (popcodep == NULL)
 1450: 	return NULL;
 1451: 
 1452:       if (popcodep->match == BDAP_QUICK_OPCODE)
 1453: 	{
 1454: 	  /* Since some offsets are recognized with "push" macros, we
 1455: 	     have to have different tables for them.  */
 1456: 	  int offset = (prefix_insn & 255);
 1457: 
 1458: 	  if (offset > 127)
 1459: 	    offset -= 256;
 1460: 
 1461: 	  switch (offset)
 1462: 	    {
 1463: 	    case -4:
 1464: 	      prefix_opc_table = bdapq_m4_prefixes;
 1465: 	      break;
 1466: 
 1467: 	    case -2:
 1468: 	      prefix_opc_table = bdapq_m2_prefixes;
 1469: 	      break;
 1470: 
 1471: 	    case -1:
 1472: 	      prefix_opc_table = bdapq_m1_prefixes;
 1473: 	      break;
 1474: 
 1475: 	    default:
 1476: 	      prefix_opc_table = rest_prefixes;
 1477: 	      break;
 1478: 	    }
 1479: 	}
 1480:       else if (popcodep->match == DIP_OPCODE)
 1481: 	/* We don't allow postincrement when the prefix is DIP, so use a
 1482: 	   different table for DIP.  */
 1483: 	prefix_opc_table = dip_prefixes;
 1484:       else
 1485: 	prefix_opc_table = rest_prefixes;
 1486:     }
 1487: 
 1488:   if (prefix_insn != NO_CRIS_PREFIX
 1489:       && prefix_opc_table[insn] != NULL)
 1490:     max_matchedp = prefix_opc_table[insn];
 1491:   else if (prefix_insn == NO_CRIS_PREFIX && opc_table[insn] != NULL)
 1492:     max_matchedp = opc_table[insn];
 1493:   else
 1494:     {
 1495:       const struct cris_opcode *opcodep;
 1496:       int max_level_of_match = -1;
 1497: 
 1498:       for (opcodep = cris_opcodes;
 1499: 	   opcodep->name != NULL;
 1500: 	   opcodep++)
 1501: 	{
 1502: 	  int level_of_match;
 1503: 
 1504: 	  if (disdata->distype == cris_dis_v32)
 1505: 	    {
 1506: 	      switch (opcodep->applicable_version)
 1507: 		{
 1508: 		case cris_ver_version_all:
 1509: 		  break;
 1510: 
 1511: 		case cris_ver_v0_3:
 1512: 		case cris_ver_v0_10:
 1513: 		case cris_ver_v3_10:
 1514: 		case cris_ver_sim_v0_10:
 1515: 		case cris_ver_v8_10:
 1516: 		case cris_ver_v10:
 1517: 		case cris_ver_warning:
 1518: 		  continue;
 1519: 
 1520: 		case cris_ver_v3p:
 1521: 		case cris_ver_v8p:
 1522: 		case cris_ver_v10p:
 1523: 		case cris_ver_v32p:
 1524: 		  break;
 1525: 
 1526: 		case cris_ver_v8:
 1527: 		  abort ();
 1528: 		default:
 1529: 		  abort ();
 1530: 		}
 1531: 	    }
 1532: 	  else
 1533: 	    {
 1534: 	      switch (opcodep->applicable_version)
 1535: 		{
 1536: 		case cris_ver_version_all:
 1537: 		case cris_ver_v0_3:
 1538: 		case cris_ver_v3p:
 1539: 		case cris_ver_v0_10:
 1540: 		case cris_ver_v8p:
 1541: 		case cris_ver_v8_10:
 1542: 		case cris_ver_v10:
 1543: 		case cris_ver_sim_v0_10:
 1544: 		case cris_ver_v10p:
 1545: 		case cris_ver_warning:
 1546: 		  break;
 1547: 
 1548: 		case cris_ver_v32p:
 1549: 		  continue;
 1550: 
 1551: 		case cris_ver_v8:
 1552: 		  abort ();
 1553: 		default:
 1554: 		  abort ();
 1555: 		}
 1556: 	    }
 1557: 
 1558: 	  /* We give a double lead for bits matching the template in
 1559: 	     cris_opcodes.  Not even, because then "move p8,r10" would
 1560: 	     be given 2 bits lead over "clear.d r10".  When there's a
 1561: 	     tie, the first entry in the table wins.  This is
 1562: 	     deliberate, to avoid a more complicated recognition
 1563: 	     formula.  */
 1564: 	  if ((opcodep->match & insn) == opcodep->match
 1565: 	      && (opcodep->lose & insn) == 0
 1566: 	      && ((level_of_match
 1567: 		   = cris_constraint (opcodep->args,
 1568: 				      insn,
 1569: 				      prefix_insn,
 1570: 				      disdata))
 1571: 		  >= 0)
 1572: 	      && ((level_of_match
 1573: 		   += 2 * number_of_bits (opcodep->match
 1574: 					  | opcodep->lose))
 1575: 			  > max_level_of_match))
 1576: 		    {
 1577: 		      max_matchedp = opcodep;
 1578: 		      max_level_of_match = level_of_match;
 1579: 
 1580: 		      /* If there was a full match, never mind looking
 1581: 			 further.  */
 1582: 		      if (level_of_match >= 2 * 16)
 1583: 			break;
 1584: 		    }
 1585: 		}
 1586:       /* Fill in the new entry.
 1587: 
 1588: 	 If there are changes to the opcode-table involving prefixes, and
 1589: 	 disassembly then does not work correctly, try removing the
 1590: 	 else-clause below that fills in the prefix-table.  If that
 1591: 	 helps, you need to change the prefix_opc_table setting above, or
 1592: 	 something related.  */
 1593:       if (prefix_insn == NO_CRIS_PREFIX)
 1594: 	opc_table[insn] = max_matchedp;
 1595:       else
 1596: 	prefix_opc_table[insn] = max_matchedp;
 1597:     }
 1598: 
 1599:   return max_matchedp;
 1600: }
 1601: 
 1602: /* Return -1 if the constraints of a bitwise-matched instruction say
 1603:    that there is no match.  Otherwise return a nonnegative number
 1604:    indicating the confidence in the match (higher is better).  */
 1605: 
 1606: static int
 1607: cris_constraint (const char *cs,
 1608: 		 unsigned int insn,
 1609: 		 unsigned int prefix_insn,
 1610: 		 struct cris_disasm_data *disdata)
 1611: {
 1612:   int retval = 0;
 1613:   int tmp;
 1614:   int prefix_ok = 0;
 1615:   const char *s;
 1616: 
 1617:   for (s = cs; *s; s++)
 1618:     switch (*s)
 1619:       {
 1620:       case '!':
 1621: 	/* Do not recognize "pop" if there's a prefix and then only for
 1622:            v0..v10.  */
 1623: 	if (prefix_insn != NO_CRIS_PREFIX
 1624: 	    || disdata->distype != cris_dis_v0_v10)
 1625: 	  return -1;
 1626: 	break;
 1627: 
 1628:       case 'U':
 1629: 	/* Not recognized at disassembly.  */
 1630: 	return -1;
 1631: 
 1632:       case 'M':
 1633: 	/* Size modifier for "clear", i.e. special register 0, 4 or 8.
 1634: 	   Check that it is one of them.  Only special register 12 could
 1635: 	   be mismatched, but checking for matches is more logical than
 1636: 	   checking for mismatches when there are only a few cases.  */
 1637: 	tmp = ((insn >> 12) & 0xf);
 1638: 	if (tmp != 0 && tmp != 4 && tmp != 8)
 1639: 	  return -1;
 1640: 	break;
 1641: 
 1642:       case 'm':
 1643: 	if ((insn & 0x30) == 0x30)
 1644: 	  return -1;
 1645: 	break;
 1646: 
 1647:       case 'S':
 1648: 	/* A prefix operand without side-effect.  */
 1649: 	if (prefix_insn != NO_CRIS_PREFIX && (insn & 0x400) == 0)
 1650: 	  {
 1651: 	    prefix_ok = 1;
 1652: 	    break;
 1653: 	  }
 1654: 	else
 1655: 	  return -1;
 1656: 
 1657:       case 's':
 1658:       case 'y':
 1659:       case 'Y':
 1660: 	/* If this is a prefixed insn with postincrement (side-effect),
 1661: 	   the prefix must not be DIP.  */
 1662: 	if (prefix_insn != NO_CRIS_PREFIX)
 1663: 	  {
 1664: 	    if (insn & 0x400)
 1665: 	      {
 1666: 		const struct cris_opcode *prefix_opcodep
 1667: 		  = get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata);
 1668: 
 1669: 		if (prefix_opcodep->match == DIP_OPCODE)
 1670: 		  return -1;
 1671: 	      }
 1672: 
 1673: 	    prefix_ok = 1;
 1674: 	  }
 1675: 	break;
 1676: 
 1677:       case 'B':
 1678: 	/* If we don't fall through, then the prefix is ok.  */
 1679: 	prefix_ok = 1;
 1680: 
 1681: 	/* A "push" prefix.  Check for valid "push" size.
 1682: 	   In case of special register, it may be != 4.  */
 1683: 	if (prefix_insn != NO_CRIS_PREFIX)
 1684: 	  {
 1685: 	    /* Match the prefix insn to BDAPQ.  */
 1686: 	    const struct cris_opcode *prefix_opcodep
 1687: 	      = get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata);
 1688: 
 1689: 	    if (prefix_opcodep->match == BDAP_QUICK_OPCODE)
 1690: 	      {
 1691: 		int pushsize = (prefix_insn & 255);
 1692: 
 1693: 		if (pushsize > 127)
 1694: 		  pushsize -= 256;
 1695: 
 1696: 		if (s[1] == 'P')
 1697: 		  {
 1698: 		    unsigned int spec_reg = (insn >> 12) & 15;
 1699: 		    const struct cris_spec_reg *sregp
 1700: 		      = spec_reg_info (spec_reg, disdata->distype);
 1701: 
 1702: 		    /* For a special-register, the "prefix size" must
 1703: 		       match the size of the register.  */
 1704: 		    if (sregp && sregp->reg_size == (unsigned int) -pushsize)
 1705: 		      break;
 1706: 		  }
 1707: 		else if (s[1] == 'R')
 1708: 		  {
 1709: 		    if ((insn & 0x30) == 0x20 && pushsize == -4)
 1710: 		      break;
 1711: 		  }
 1712: 		/* FIXME:  Should abort here; next constraint letter
 1713: 		   *must* be 'P' or 'R'.  */
 1714: 	      }
 1715: 	  }
 1716: 	return -1;
 1717: 
 1718:       case 'D':
 1719: 	retval = (((insn >> 12) & 15) == (insn & 15));
 1720: 	if (!retval)
 1721: 	  return -1;
 1722: 	else
 1723: 	  retval += 4;
 1724: 	break;
 1725: 
 1726:       case 'P':
 1727: 	{
 1728: 	  const struct cris_spec_reg *sregp
 1729: 	    = spec_reg_info ((insn >> 12) & 15, disdata->distype);
 1730: 
 1731: 	  /* Since we match four bits, we will give a value of 4-1 = 3
 1732: 	     in a match.  If there is a corresponding exact match of a
 1733: 	     special register in another pattern, it will get a value of
 1734: 	     4, which will be higher.  This should be correct in that an
 1735: 	     exact pattern would match better than a general pattern.
 1736: 
 1737: 	     Note that there is a reason for not returning zero; the
 1738: 	     pattern for "clear" is partly  matched in the bit-pattern
 1739: 	     (the two lower bits must be zero), while the bit-pattern
 1740: 	     for a move from a special register is matched in the
 1741: 	     register constraint.  */
 1742: 
 1743: 	  if (sregp != NULL)
 1744: 	    {
 1745: 	      retval += 3;
 1746: 	      break;
 1747: 	    }
 1748: 	  else
 1749: 	    return -1;
 1750: 	}
 1751:       }
 1752: 
 1753:   if (prefix_insn != NO_CRIS_PREFIX && ! prefix_ok)
 1754:     return -1;
 1755: 
 1756:   return retval;
 1757: }
 1758: 
 1759: /* Format number as hex with a leading "0x" into outbuffer.  */
 1760: 
 1761: static char *
 1762: format_hex (unsigned long number,
 1763: 	    char *outbuffer,
 1764: 	    struct cris_disasm_data *disdata)
 1765: {
 1766:   /* Truncate negative numbers on >32-bit hosts.  */
 1767:   number &= 0xffffffff;
 1768: 
 1769:   sprintf (outbuffer, "0x%lx", number);
 1770: 
 1771:   /* Save this value for the "case" support.  */
 1772:   if (TRACE_CASE)
 1773:     last_immediate = number;
 1774: 
 1775:   return outbuffer + strlen (outbuffer);
 1776: }
 1777: 
 1778: /* Format number as decimal into outbuffer.  Parameter signedp says
 1779:    whether the number should be formatted as signed (!= 0) or
 1780:    unsigned (== 0).  */
 1781: 
 1782: static char *
 1783: format_dec (long number, char *outbuffer, int signedp)
 1784: {
 1785:   last_immediate = number;
 1786:   sprintf (outbuffer, signedp ? "%ld" : "%lu", number);
 1787: 
 1788:   return outbuffer + strlen (outbuffer);
 1789: }
 1790: 
 1791: /* Format the name of the general register regno into outbuffer.  */
 1792: 
 1793: static char *
 1794: format_reg (struct cris_disasm_data *disdata,
 1795: 	    int regno,
 1796: 	    char *outbuffer_start,
 1797: 	    bfd_boolean with_reg_prefix)
 1798: {
 1799:   char *outbuffer = outbuffer_start;
 1800: 
 1801:   if (with_reg_prefix)
 1802:     *outbuffer++ = REGISTER_PREFIX_CHAR;
 1803: 
 1804:   switch (regno)
 1805:     {
 1806:     case 15:
 1807:       /* For v32, there is no context in which we output PC.  */
 1808:       if (disdata->distype == cris_dis_v32)
 1809: 	strcpy (outbuffer, "acr");
 1810:       else
 1811: 	strcpy (outbuffer, "pc");
 1812:       break;
 1813: 
 1814:     case 14:
 1815:       strcpy (outbuffer, "sp");
 1816:       break;
 1817: 
 1818:     default:
 1819:       sprintf (outbuffer, "r%d", regno);
 1820:       break;
 1821:     }
 1822: 
 1823:   return outbuffer_start + strlen (outbuffer_start);
 1824: }
 1825: 
 1826: /* Format the name of a support register into outbuffer.  */
 1827: 
 1828: static char *
 1829: format_sup_reg (unsigned int regno,
 1830: 		char *outbuffer_start,
 1831: 		bfd_boolean with_reg_prefix)
 1832: {
 1833:   char *outbuffer = outbuffer_start;
 1834:   int i;
 1835: 
 1836:   if (with_reg_prefix)
 1837:     *outbuffer++ = REGISTER_PREFIX_CHAR;
 1838: 
 1839:   for (i = 0; cris_support_regs[i].name != NULL; i++)
 1840:     if (cris_support_regs[i].number == regno)
 1841:       {
 1842: 	sprintf (outbuffer, "%s", cris_support_regs[i].name);
 1843: 	return outbuffer_start + strlen (outbuffer_start);
 1844:       }
 1845: 
 1846:   /* There's supposed to be register names covering all numbers, though
 1847:      some may be generic names.  */
 1848:   sprintf (outbuffer, "format_sup_reg-BUG");
 1849:   return outbuffer_start + strlen (outbuffer_start);
 1850: }
 1851: 
 1852: /* Return the length of an instruction.  */
 1853: 
 1854: static unsigned
 1855: bytes_to_skip (unsigned int insn,
 1856: 	       const struct cris_opcode *matchedp,
 1857: 	       enum cris_disass_family distype,
 1858: 	       const struct cris_opcode *prefix_matchedp)
 1859: {
 1860:   /* Each insn is a word plus "immediate" operands.  */
 1861:   unsigned to_skip = 2;
 1862:   const char *template = matchedp->args;
 1863:   const char *s;
 1864: 
 1865:   for (s = template; *s; s++)
 1866:     if ((*s == 's' || *s == 'N' || *s == 'Y')
 1867: 	&& (insn & 0x400) && (insn & 15) == 15
 1868: 	&& prefix_matchedp == NULL)
 1869:       {
 1870: 	/* Immediate via [pc+], so we have to check the size of the
 1871: 	   operand.  */
 1872: 	int mode_size = 1 << ((insn >> 4) & (*template == 'z' ? 1 : 3));
 1873: 
 1874: 	if (matchedp->imm_oprnd_size == SIZE_FIX_32)
 1875: 	  to_skip += 4;
 1876: 	else if (matchedp->imm_oprnd_size == SIZE_SPEC_REG)
 1877: 	  {
 1878: 	    const struct cris_spec_reg *sregp
 1879: 	      = spec_reg_info ((insn >> 12) & 15, distype);
 1880: 
 1881: 	    /* FIXME: Improve error handling; should have been caught
 1882: 	       earlier.  */
 1883: 	    if (sregp == NULL)
 1884: 	      return 2;
 1885: 
 1886: 	    /* PC is incremented by two, not one, for a byte.  Except on
 1887: 	       CRISv32, where constants are always DWORD-size for
 1888: 	       special registers.  */
 1889: 	    to_skip +=
 1890: 	      distype == cris_dis_v32 ? 4 : (sregp->reg_size + 1) & ~1;
 1891: 	  }
 1892: 	else
 1893: 	  to_skip += (mode_size + 1) & ~1;
 1894:       }
 1895:     else if (*s == 'n')
 1896:       to_skip += 4;
 1897:     else if (*s == 'b')
 1898:       to_skip += 2;
 1899: 
 1900:   return to_skip;
 1901: }
 1902: 
 1903: /* Print condition code flags.  */
 1904: 
 1905: static char *
 1906: print_flags (struct cris_disasm_data *disdata, unsigned int insn, char *cp)
 1907: {
 1908:   /* Use the v8 (Etrax 100) flag definitions for disassembly.
 1909:      The differences with v0 (Etrax 1..4) vs. Svinto are:
 1910:       v0 'd' <=> v8 'm'
 1911:       v0 'e' <=> v8 'b'.
 1912:      FIXME: Emit v0..v3 flag names somehow.  */
 1913:   static const char v8_fnames[] = "cvznxibm";
 1914:   static const char v32_fnames[] = "cvznxiup";
 1915:   const char *fnames
 1916:     = disdata->distype == cris_dis_v32 ? v32_fnames : v8_fnames;
 1917: 
 1918:   unsigned char flagbits = (((insn >> 8) & 0xf0) | (insn & 15));
 1919:   int i;
 1920: 
 1921:   for (i = 0; i < 8; i++)
 1922:     if (flagbits & (1 << i))
 1923:       *cp++ = fnames[i];
 1924: 
 1925:   return cp;
 1926: }
 1927: 
 1928: /* Print out an insn with its operands, and update the info->insn_type
 1929:    fields.  The prefix_opcodep and the rest hold a prefix insn that is
 1930:    supposed to be output as an address mode.  */
 1931: 
 1932: static void
 1933: print_with_operands (const struct cris_opcode *opcodep,
 1934: 		     unsigned int insn,
 1935: 		     unsigned char *buffer,
 1936: 		     bfd_vma addr,
 1937: 		     disassemble_info *info,
 1938: 		     /* If a prefix insn was before this insn (and is supposed
 1939: 			to be output as an address), here is a description of
 1940: 			it.  */
 1941: 		     const struct cris_opcode *prefix_opcodep,
 1942: 		     unsigned int prefix_insn,
 1943: 		     unsigned char *prefix_buffer,
 1944: 		     bfd_boolean with_reg_prefix)
 1945: {
 1946:   /* Get a buffer of somewhat reasonable size where we store
 1947:      intermediate parts of the insn.  */
 1948:   char temp[sizeof (".d [$r13=$r12-2147483648],$r10") * 2];
 1949:   char *tp = temp;
 1950:   static const char mode_char[] = "bwd?";
 1951:   const char *s;
 1952:   const char *cs;
 1953:   struct cris_disasm_data *disdata
 1954:     = (struct cris_disasm_data *) info->private_data;
 1955: 
 1956:   /* Print out the name first thing we do.  */
 1957:   (*info->fprintf_func) (info->stream, "%s", opcodep->name);
 1958: 
 1959:   cs = opcodep->args;
 1960:   s = cs;
 1961: 
 1962:   /* Ignore any prefix indicator.  */
 1963:   if (*s == 'p')
 1964:     s++;
 1965: 
 1966:   if (*s == 'm' || *s == 'M' || *s == 'z')
 1967:     {
 1968:       *tp++ = '.';
 1969: 
 1970:       /* Get the size-letter.  */
 1971:       *tp++ = *s == 'M'
 1972: 	? (insn & 0x8000 ? 'd'
 1973: 	   : insn & 0x4000 ? 'w' : 'b')
 1974: 	: mode_char[(insn >> 4) & (*s == 'z' ? 1 : 3)];
 1975: 
 1976:       /* Ignore the size and the space character that follows.  */
 1977:       s += 2;
 1978:     }
 1979: 
 1980:   /* Add a space if this isn't a long-branch, because for those will add
 1981:      the condition part of the name later.  */
 1982:   if (opcodep->match != (BRANCH_PC_LOW + BRANCH_INCR_HIGH * 256))
 1983:     *tp++ = ' ';
 1984: 
 1985:   /* Fill in the insn-type if deducible from the name (and there's no
 1986:      better way).  */
 1987:   if (opcodep->name[0] == 'j')
 1988:     {
 1989:       if (CONST_STRNEQ (opcodep->name, "jsr"))
 1990: 	/* It's "jsr" or "jsrc".  */
 1991: 	info->insn_type = dis_jsr;
 1992:       else
 1993: 	/* Any other jump-type insn is considered a branch.  */
 1994: 	info->insn_type = dis_branch;
 1995:     }
 1996: 
 1997:   /* We might know some more fields right now.  */
 1998:   info->branch_delay_insns = opcodep->delayed;
 1999: 
 2000:   /* Handle operands.  */
 2001:   for (; *s; s++)
 2002:     {
 2003:     switch (*s)
 2004:       {
 2005:       case 'T':
 2006: 	tp = format_sup_reg ((insn >> 12) & 15, tp, with_reg_prefix);
 2007: 	break;
 2008: 
 2009:       case 'A':
 2010: 	if (with_reg_prefix)
 2011: 	  *tp++ = REGISTER_PREFIX_CHAR;
 2012: 	*tp++ = 'a';
 2013: 	*tp++ = 'c';
 2014: 	*tp++ = 'r';
 2015: 	break;
 2016: 
 2017:       case '[':
 2018:       case ']':
 2019:       case ',':
 2020: 	*tp++ = *s;
 2021: 	break;
 2022: 
 2023:       case '!':
 2024: 	/* Ignore at this point; used at earlier stages to avoid
 2025: 	   recognition if there's a prefix at something that in other
 2026: 	   ways looks like a "pop".  */
 2027: 	break;
 2028: 
 2029:       case 'd':
 2030: 	/* Ignore.  This is an optional ".d " on the large one of
 2031: 	   relaxable insns.  */
 2032: 	break;
 2033: 
 2034:       case 'B':
 2035: 	/* This was the prefix that made this a "push".  We've already
 2036: 	   handled it by recognizing it, so signal that the prefix is
 2037: 	   handled by setting it to NULL.  */
 2038: 	prefix_opcodep = NULL;
 2039: 	break;
 2040: 
 2041:       case 'D':
 2042:       case 'r':
 2043: 	tp = format_reg (disdata, insn & 15, tp, with_reg_prefix);
 2044: 	break;
 2045: 
 2046:       case 'R':
 2047: 	tp = format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix);
 2048: 	break;
 2049: 
 2050:       case 'n':
 2051: 	{
 2052: 	  /* Like N but pc-relative to the start of the insn.  */
 2053: 	  unsigned long number
 2054: 	    = (buffer[2] + buffer[3] * 256 + buffer[4] * 65536
 2055: 	       + buffer[5] * 0x1000000 + addr);
 2056: 
 2057: 	  /* Finish off and output previous formatted bytes.  */
 2058: 	  *tp = 0;
 2059: 	  if (temp[0])
 2060: 	    (*info->fprintf_func) (info->stream, "%s", temp);
 2061: 	  tp = temp;
 2062: 
 2063: 	  (*info->print_address_func) ((bfd_vma) number, info);
 2064: 	}
 2065: 	break;
 2066: 
 2067:       case 'u':
 2068: 	{
 2069: 	  /* Like n but the offset is bits <3:0> in the instruction.  */
 2070: 	  unsigned long number = (buffer[0] & 0xf) * 2 + addr;
 2071: 
 2072: 	  /* Finish off and output previous formatted bytes.  */
 2073: 	  *tp = 0;
 2074: 	  if (temp[0])
 2075: 	    (*info->fprintf_func) (info->stream, "%s", temp);
 2076: 	  tp = temp;
 2077: 
 2078: 	  (*info->print_address_func) ((bfd_vma) number, info);
 2079: 	}
 2080: 	break;
 2081: 
 2082:       case 'N':
 2083:       case 'y':
 2084:       case 'Y':
 2085:       case 'S':
 2086:       case 's':
 2087: 	/* Any "normal" memory operand.  */
 2088: 	if ((insn & 0x400) && (insn & 15) == 15 && prefix_opcodep == NULL)
 2089: 	  {
 2090: 	    /* We're looking at [pc+], i.e. we need to output an immediate
 2091: 	       number, where the size can depend on different things.  */
 2092: 	    long number;
 2093: 	    int signedp
 2094: 	      = ((*cs == 'z' && (insn & 0x20))
 2095: 		 || opcodep->match == BDAP_QUICK_OPCODE);
 2096: 	    int nbytes;
 2097: 
 2098: 	    if (opcodep->imm_oprnd_size == SIZE_FIX_32)
 2099: 	      nbytes = 4;
 2100: 	    else if (opcodep->imm_oprnd_size == SIZE_SPEC_REG)
 2101: 	      {
 2102: 		const struct cris_spec_reg *sregp
 2103: 		  = spec_reg_info ((insn >> 12) & 15, disdata->distype);
 2104: 
 2105: 		/* A NULL return should have been as a non-match earlier,
 2106: 		   so catch it as an internal error in the error-case
 2107: 		   below.  */
 2108: 		if (sregp == NULL)
 2109: 		  /* Whatever non-valid size.  */
 2110: 		  nbytes = 42;
 2111: 		else
 2112: 		  /* PC is always incremented by a multiple of two.
 2113: 		     For CRISv32, immediates are always 4 bytes for
 2114: 		     special registers.  */
 2115: 		  nbytes = disdata->distype == cris_dis_v32
 2116: 		    ? 4 : (sregp->reg_size + 1) & ~1;
 2117: 	      }
 2118: 	    else
 2119: 	      {
 2120: 		int mode_size = 1 << ((insn >> 4) & (*cs == 'z' ? 1 : 3));
 2121: 
 2122: 		if (mode_size == 1)
 2123: 		  nbytes = 2;
 2124: 		else
 2125: 		  nbytes = mode_size;
 2126: 	      }
 2127: 
 2128: 	    switch (nbytes)
 2129: 	      {
 2130: 	      case 1:
 2131: 		number = buffer[2];
 2132: 		if (signedp && number > 127)
 2133: 		  number -= 256;
 2134: 		break;
 2135: 
 2136: 	      case 2:
 2137: 		number = buffer[2] + buffer[3] * 256;
 2138: 		if (signedp && number > 32767)
 2139: 		  number -= 65536;
 2140: 		break;
 2141: 
 2142: 	      case 4:
 2143: 		number
 2144: 		  = buffer[2] + buffer[3] * 256 + buffer[4] * 65536
 2145: 		  + buffer[5] * 0x1000000;
 2146: 		break;
 2147: 
 2148: 	      default:
 2149: 		strcpy (tp, "bug");
 2150: 		tp += 3;
 2151: 		number = 42;
 2152: 	      }
 2153: 
 2154: 	    if ((*cs == 'z' && (insn & 0x20))
 2155: 		|| (opcodep->match == BDAP_QUICK_OPCODE
 2156: 		    && (nbytes <= 2 || buffer[1 + nbytes] == 0)))
 2157: 	      tp = format_dec (number, tp, signedp);
 2158: 	    else
 2159: 	      {
 2160: 		unsigned int highbyte = (number >> 24) & 0xff;
 2161: 
 2162: 		/* Either output this as an address or as a number.  If it's
 2163: 		   a dword with the same high-byte as the address of the
 2164: 		   insn, assume it's an address, and also if it's a non-zero
 2165: 		   non-0xff high-byte.  If this is a jsr or a jump, then
 2166: 		   it's definitely an address.  */
 2167: 		if (nbytes == 4
 2168: 		    && (highbyte == ((addr >> 24) & 0xff)
 2169: 			|| (highbyte != 0 && highbyte != 0xff)
 2170: 			|| info->insn_type == dis_branch
 2171: 			|| info->insn_type == dis_jsr))
 2172: 		  {
 2173: 		    /* Finish off and output previous formatted bytes.  */
 2174: 		    *tp = 0;
 2175: 		    tp = temp;
 2176: 		    if (temp[0])
 2177: 		      (*info->fprintf_func) (info->stream, "%s", temp);
 2178: 
 2179: 		    (*info->print_address_func) ((bfd_vma) number, info);
 2180: 
 2181: 		    info->target = number;
 2182: 		  }
 2183: 		else
 2184: 		  tp = format_hex (number, tp, disdata);
 2185: 	      }
 2186: 	  }
 2187: 	else
 2188: 	  {
 2189: 	    /* Not an immediate number.  Then this is a (possibly
 2190: 	       prefixed) memory operand.  */
 2191: 	    if (info->insn_type != dis_nonbranch)
 2192: 	      {
 2193: 		int mode_size
 2194: 		  = 1 << ((insn >> 4)
 2195: 			  & (opcodep->args[0] == 'z' ? 1 : 3));
 2196: 		int size;
 2197: 		info->insn_type = dis_dref;
 2198: 		info->flags |= CRIS_DIS_FLAG_MEMREF;
 2199: 
 2200: 		if (opcodep->imm_oprnd_size == SIZE_FIX_32)
 2201: 		  size = 4;
 2202: 		else if (opcodep->imm_oprnd_size == SIZE_SPEC_REG)
 2203: 		  {
 2204: 		    const struct cris_spec_reg *sregp
 2205: 		      = spec_reg_info ((insn >> 12) & 15, disdata->distype);
 2206: 
 2207: 		    /* FIXME: Improve error handling; should have been caught
 2208: 		       earlier.  */
 2209: 		    if (sregp == NULL)
 2210: 		      size = 4;
 2211: 		    else
 2212: 		      size = sregp->reg_size;
 2213: 		  }
 2214: 		else
 2215: 		  size = mode_size;
 2216: 
 2217: 		info->data_size = size;
 2218: 	      }
 2219: 
 2220: 	    *tp++ = '[';
 2221: 
 2222: 	    if (prefix_opcodep
 2223: 		/* We don't match dip with a postincremented field
 2224: 		   as a side-effect address mode.  */
 2225: 		&& ((insn & 0x400) == 0
 2226: 		    || prefix_opcodep->match != DIP_OPCODE))
 2227: 	      {
 2228: 		if (insn & 0x400)
 2229: 		  {
 2230: 		    tp = format_reg (disdata, insn & 15, tp, with_reg_prefix);
 2231: 		    *tp++ = '=';
 2232: 		  }
 2233: 
 2234: 
 2235: 		/* We mainly ignore the prefix format string when the
 2236: 		   address-mode syntax is output.  */
 2237: 		switch (prefix_opcodep->match)
 2238: 		  {
 2239: 		  case DIP_OPCODE:
 2240: 		    /* It's [r], [r+] or [pc+].  */
 2241: 		    if ((prefix_insn & 0x400) && (prefix_insn & 15) == 15)
 2242: 		      {
 2243: 			/* It's [pc+].  This cannot possibly be anything
 2244: 			   but an address.  */
 2245: 			unsigned long number
 2246: 			  = prefix_buffer[2] + prefix_buffer[3] * 256
 2247: 			  + prefix_buffer[4] * 65536
 2248: 			  + prefix_buffer[5] * 0x1000000;
 2249: 
 2250: 			info->target = (bfd_vma) number;
 2251: 
 2252: 			/* Finish off and output previous formatted
 2253: 			   data.  */
 2254: 			*tp = 0;
 2255: 			tp = temp;
 2256: 			if (temp[0])
 2257: 			  (*info->fprintf_func) (info->stream, "%s", temp);
 2258: 
 2259: 			(*info->print_address_func) ((bfd_vma) number, info);
 2260: 		      }
 2261: 		    else
 2262: 		      {
 2263: 			/* For a memref in an address, we use target2.
 2264: 			   In this case, target is zero.  */
 2265: 			info->flags
 2266: 			  |= (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG
 2267: 			      | CRIS_DIS_FLAG_MEM_TARGET2_MEM);
 2268: 
 2269: 			info->target2 = prefix_insn & 15;
 2270: 
 2271: 			*tp++ = '[';
 2272: 			tp = format_reg (disdata, prefix_insn & 15, tp,
 2273: 					 with_reg_prefix);
 2274: 			if (prefix_insn & 0x400)
 2275: 			  *tp++ = '+';
 2276: 			*tp++ = ']';
 2277: 		      }
 2278: 		    break;
 2279: 
 2280: 		  case BDAP_QUICK_OPCODE:
 2281: 		    {
 2282: 		      int number;
 2283: 
 2284: 		      number = prefix_buffer[0];
 2285: 		      if (number > 127)
 2286: 			number -= 256;
 2287: 
 2288: 		      /* Output "reg+num" or, if num < 0, "reg-num".  */
 2289: 		      tp = format_reg (disdata, (prefix_insn >> 12) & 15, tp,
 2290: 				       with_reg_prefix);
 2291: 		      if (number >= 0)
 2292: 			*tp++ = '+';
 2293: 		      tp = format_dec (number, tp, 1);
 2294: 
 2295: 		      info->flags |= CRIS_DIS_FLAG_MEM_TARGET_IS_REG;
 2296: 		      info->target = (prefix_insn >> 12) & 15;
 2297: 		      info->target2 = (bfd_vma) number;
 2298: 		      break;
 2299: 		    }
 2300: 
 2301: 		  case BIAP_OPCODE:
 2302: 		    /* Output "r+R.m".  */
 2303: 		    tp = format_reg (disdata, prefix_insn & 15, tp,
 2304: 				     with_reg_prefix);
 2305: 		    *tp++ = '+';
 2306: 		    tp = format_reg (disdata, (prefix_insn >> 12) & 15, tp,
 2307: 				     with_reg_prefix);
 2308: 		    *tp++ = '.';
 2309: 		    *tp++ = mode_char[(prefix_insn >> 4) & 3];
 2310: 
 2311: 		    info->flags
 2312: 		      |= (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG
 2313: 			  | CRIS_DIS_FLAG_MEM_TARGET_IS_REG
 2314: 
 2315: 			  | ((prefix_insn & 0x8000)
 2316: 			     ? CRIS_DIS_FLAG_MEM_TARGET2_MULT4
 2317: 			     : ((prefix_insn & 0x8000)
 2318: 				? CRIS_DIS_FLAG_MEM_TARGET2_MULT2 : 0)));
 2319: 
 2320: 		    /* Is it the casejump?  It's a "adds.w [pc+r%d.w],pc".  */
 2321: 		    if (insn == 0xf83f && (prefix_insn & ~0xf000) == 0x55f)
 2322: 		      /* Then start interpreting data as offsets.  */
 2323: 		      case_offset_counter = no_of_case_offsets;
 2324: 		    break;
 2325: 
 2326: 		  case BDAP_INDIR_OPCODE:
 2327: 		    /* Output "r+s.m", or, if "s" is [pc+], "r+s" or
 2328: 		       "r-s".  */
 2329: 		    tp = format_reg (disdata, (prefix_insn >> 12) & 15, tp,
 2330: 				     with_reg_prefix);
 2331: 
 2332: 		    if ((prefix_insn & 0x400) && (prefix_insn & 15) == 15)
 2333: 		      {
 2334: 			long number;
 2335: 			unsigned int nbytes;
 2336: 
 2337: 			/* It's a value.  Get its size.  */
 2338: 			int mode_size = 1 << ((prefix_insn >> 4) & 3);
 2339: 
 2340: 			if (mode_size == 1)
 2341: 			  nbytes = 2;
 2342: 			else
 2343: 			  nbytes = mode_size;
 2344: 
 2345: 			switch (nbytes)
 2346: 			  {
 2347: 			  case 1:
 2348: 			    number = prefix_buffer[2];
 2349: 			    if (number > 127)
 2350: 			      number -= 256;
 2351: 			    break;
 2352: 
 2353: 			  case 2:
 2354: 			    number = prefix_buffer[2] + prefix_buffer[3] * 256;
 2355: 			    if (number > 32767)
 2356: 			      number -= 65536;
 2357: 			    break;
 2358: 
 2359: 			  case 4:
 2360: 			    number
 2361: 			      = prefix_buffer[2] + prefix_buffer[3] * 256
 2362: 			      + prefix_buffer[4] * 65536
 2363: 			      + prefix_buffer[5] * 0x1000000;
 2364: 			    break;
 2365: 
 2366: 			  default:
 2367: 			    strcpy (tp, "bug");
 2368: 			    tp += 3;
 2369: 			    number = 42;
 2370: 			  }
 2371: 
 2372: 			info->flags |= CRIS_DIS_FLAG_MEM_TARGET_IS_REG;
 2373: 			info->target2 = (bfd_vma) number;
 2374: 
 2375: 			/* If the size is dword, then assume it's an
 2376: 			   address.  */
 2377: 			if (nbytes == 4)
 2378: 			  {
 2379: 			    /* Finish off and output previous formatted
 2380: 			       bytes.  */
 2381: 			    *tp++ = '+';
 2382: 			    *tp = 0;
 2383: 			    tp = temp;
 2384: 			    (*info->fprintf_func) (info->stream, "%s", temp);
 2385: 
 2386: 			    (*info->print_address_func) ((bfd_vma) number, info);
 2387: 			  }
 2388: 			else
 2389: 			  {
 2390: 			    if (number >= 0)
 2391: 			      *tp++ = '+';
 2392: 			    tp = format_dec (number, tp, 1);
 2393: 			  }
 2394: 		      }
 2395: 		    else
 2396: 		      {
 2397: 			/* Output "r+[R].m" or "r+[R+].m".  */
 2398: 			*tp++ = '+';
 2399: 			*tp++ = '[';
 2400: 			tp = format_reg (disdata, prefix_insn & 15, tp,
 2401: 					 with_reg_prefix);
 2402: 			if (prefix_insn & 0x400)
 2403: 			  *tp++ = '+';
 2404: 			*tp++ = ']';
 2405: 			*tp++ = '.';
 2406: 			*tp++ = mode_char[(prefix_insn >> 4) & 3];
 2407: 
 2408: 			info->flags
 2409: 			  |= (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG
 2410: 			      | CRIS_DIS_FLAG_MEM_TARGET2_MEM
 2411: 			      | CRIS_DIS_FLAG_MEM_TARGET_IS_REG
 2412: 
 2413: 			      | (((prefix_insn >> 4) == 2)
 2414: 				 ? 0
 2415: 				 : (((prefix_insn >> 4) & 3) == 1
 2416: 				    ? CRIS_DIS_FLAG_MEM_TARGET2_MEM_WORD
 2417: 				    : CRIS_DIS_FLAG_MEM_TARGET2_MEM_BYTE)));
 2418: 		      }
 2419: 		    break;
 2420: 
 2421: 		  default:
 2422: 		    (*info->fprintf_func) (info->stream, "?prefix-bug");
 2423: 		  }
 2424: 
 2425: 		/* To mark that the prefix is used, reset it.  */
 2426: 		prefix_opcodep = NULL;
 2427: 	      }
 2428: 	    else
 2429: 	      {
 2430: 		tp = format_reg (disdata, insn & 15, tp, with_reg_prefix);
 2431: 
 2432: 		info->flags |= CRIS_DIS_FLAG_MEM_TARGET_IS_REG;
 2433: 		info->target = insn & 15;
 2434: 
 2435: 		if (insn & 0x400)
 2436: 		  *tp++ = '+';
 2437: 	      }
 2438: 	    *tp++ = ']';
 2439: 	  }
 2440: 	break;
 2441: 
 2442:       case 'x':
 2443: 	tp = format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix);
 2444: 	*tp++ = '.';
 2445: 	*tp++ = mode_char[(insn >> 4) & 3];
 2446: 	break;
 2447: 
 2448:       case 'I':
 2449: 	tp = format_dec (insn & 63, tp, 0);
 2450: 	break;
 2451: 
 2452:       case 'b':
 2453: 	{
 2454: 	  int where = buffer[2] + buffer[3] * 256;
 2455: 
 2456: 	  if (where > 32767)
 2457: 	    where -= 65536;
 2458: 
 2459: 	  where += addr + ((disdata->distype == cris_dis_v32) ? 0 : 4);
 2460: 
 2461: 	  if (insn == BA_PC_INCR_OPCODE)
 2462: 	    info->insn_type = dis_branch;
 2463: 	  else
 2464: 	    info->insn_type = dis_condbranch;
 2465: 
 2466: 	  info->target = (bfd_vma) where;
 2467: 
 2468: 	  *tp = 0;
 2469: 	  tp = temp;
 2470: 	  (*info->fprintf_func) (info->stream, "%s%s ",
 2471: 				 temp, cris_cc_strings[insn >> 12]);
 2472: 
 2473: 	  (*info->print_address_func) ((bfd_vma) where, info);
 2474: 	}
 2475:       break;
 2476: 
 2477:     case 'c':
 2478:       tp = format_dec (insn & 31, tp, 0);
 2479:       break;
 2480: 
 2481:     case 'C':
 2482:       tp = format_dec (insn & 15, tp, 0);
 2483:       break;
 2484: 
 2485:     case 'o':
 2486:       {
 2487: 	long offset = insn & 0xfe;
 2488: 	bfd_vma target;
 2489: 
 2490: 	if (insn & 1)
 2491: 	  offset |= ~0xff;
 2492: 
 2493: 	if (opcodep->match == BA_QUICK_OPCODE)
 2494: 	  info->insn_type = dis_branch;
 2495: 	else
 2496: 	  info->insn_type = dis_condbranch;
 2497: 
 2498: 	target = addr + ((disdata->distype == cris_dis_v32) ? 0 : 2) + offset;
 2499: 	info->target = target;
 2500: 	*tp = 0;
 2501: 	tp = temp;
 2502: 	(*info->fprintf_func) (info->stream, "%s", temp);
 2503: 	(*info->print_address_func) (target, info);
 2504:       }
 2505:       break;
 2506: 
 2507:     case 'Q':
 2508:     case 'O':
 2509:       {
 2510: 	long number = buffer[0];
 2511: 
 2512: 	if (number > 127)
 2513: 	  number = number - 256;
 2514: 
 2515: 	tp = format_dec (number, tp, 1);
 2516: 	*tp++ = ',';
 2517: 	tp = format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix);
 2518:       }
 2519:       break;
 2520: 
 2521:     case 'f':
 2522:       tp = print_flags (disdata, insn, tp);
 2523:       break;
 2524: 
 2525:     case 'i':
 2526:       tp = format_dec ((insn & 32) ? (insn & 31) | ~31L : insn & 31, tp, 1);
 2527:       break;
 2528: 
 2529:     case 'P':
 2530:       {
 2531: 	const struct cris_spec_reg *sregp
 2532: 	  = spec_reg_info ((insn >> 12) & 15, disdata->distype);
 2533: 
 2534: 	if (sregp->name == NULL)
 2535: 	  /* Should have been caught as a non-match eariler.  */
 2536: 	  *tp++ = '?';
 2537: 	else
 2538: 	  {
 2539: 	    if (with_reg_prefix)
 2540: 	      *tp++ = REGISTER_PREFIX_CHAR;
 2541: 	    strcpy (tp, sregp->name);
 2542: 	    tp += strlen (tp);
 2543: 	  }
 2544:       }
 2545:       break;
 2546: 
 2547:     default:
 2548:       strcpy (tp, "???");
 2549:       tp += 3;
 2550:     }
 2551:   }
 2552: 
 2553:   *tp = 0;
 2554: 
 2555:   if (prefix_opcodep)
 2556:     (*info->fprintf_func) (info->stream, " (OOPS unused prefix \"%s: %s\")",
 2557: 			   prefix_opcodep->name, prefix_opcodep->args);
 2558: 
 2559:   (*info->fprintf_func) (info->stream, "%s", temp);
 2560: 
 2561:   /* Get info for matching case-tables, if we don't have any active.
 2562:      We assume that the last constant seen is used; either in the insn
 2563:      itself or in a "move.d const,rN, sub.d rN,rM"-like sequence.  */
 2564:   if (TRACE_CASE && case_offset_counter == 0)
 2565:     {
 2566:       if (CONST_STRNEQ (opcodep->name, "sub"))
 2567: 	case_offset = last_immediate;
 2568: 
 2569:       /* It could also be an "add", if there are negative case-values.  */
 2570:       else if (CONST_STRNEQ (opcodep->name, "add"))
 2571: 	/* The first case is the negated operand to the add.  */
 2572: 	case_offset = -last_immediate;
 2573: 
 2574:       /* A bound insn will tell us the number of cases.  */
 2575:       else if (CONST_STRNEQ (opcodep->name, "bound"))
 2576: 	no_of_case_offsets = last_immediate + 1;
 2577: 
 2578:       /* A jump or jsr or branch breaks the chain of insns for a
 2579: 	 case-table, so assume default first-case again.  */
 2580:       else if (info->insn_type == dis_jsr
 2581: 	       || info->insn_type == dis_branch
 2582: 	       || info->insn_type == dis_condbranch)
 2583: 	case_offset = 0;
 2584:     }
 2585: }
 2586: 
 2587: 
 2588: /* Print the CRIS instruction at address memaddr on stream.  Returns
 2589:    length of the instruction, in bytes.  Prefix register names with `$' if
 2590:    WITH_REG_PREFIX.  */
 2591: 
 2592: static int
 2593: print_insn_cris_generic (bfd_vma memaddr,
 2594: 			 disassemble_info *info,
 2595: 			 bfd_boolean with_reg_prefix)
 2596: {
 2597:   int nbytes;
 2598:   unsigned int insn;
 2599:   const struct cris_opcode *matchedp;
 2600:   int advance = 0;
 2601:   struct cris_disasm_data *disdata
 2602:     = (struct cris_disasm_data *) info->private_data;
 2603: 
 2604:   /* No instruction will be disassembled as longer than this number of
 2605:      bytes; stacked prefixes will not be expanded.  */
 2606:   unsigned char buffer[MAX_BYTES_PER_CRIS_INSN];
 2607:   unsigned char *bufp;
 2608:   int status = 0;
 2609:   bfd_vma addr;
 2610: 
 2611:   /* There will be an "out of range" error after the last instruction.
 2612:      Reading pairs of bytes in decreasing number, we hope that we will get
 2613:      at least the amount that we will consume.
 2614: 
 2615:      If we can't get any data, or we do not get enough data, we print
 2616:      the error message.  */
 2617: 
 2618:   nbytes = info->buffer_length;
 2619:   if (nbytes > MAX_BYTES_PER_CRIS_INSN)
 2620: 	  nbytes = MAX_BYTES_PER_CRIS_INSN;
 2621:   status = (*info->read_memory_func) (memaddr, buffer, nbytes, info);  
 2622: 
 2623:   /* If we did not get all we asked for, then clear the rest.
 2624:      Hopefully this makes a reproducible result in case of errors.  */
 2625:   if (nbytes != MAX_BYTES_PER_CRIS_INSN)
 2626:     memset (buffer + nbytes, 0, MAX_BYTES_PER_CRIS_INSN - nbytes);
 2627: 
 2628:   addr = memaddr;
 2629:   bufp = buffer;
 2630: 
 2631:   /* Set some defaults for the insn info.  */
 2632:   info->insn_info_valid = 1;
 2633:   info->branch_delay_insns = 0;
 2634:   info->data_size = 0;
 2635:   info->insn_type = dis_nonbranch;
 2636:   info->flags = 0;
 2637:   info->target = 0;
 2638:   info->target2 = 0;
 2639: 
 2640:   /* If we got any data, disassemble it.  */
 2641:   if (nbytes != 0)
 2642:     {
 2643:       matchedp = NULL;
 2644: 
 2645:       insn = bufp[0] + bufp[1] * 256;
 2646: 
 2647:       /* If we're in a case-table, don't disassemble the offsets.  */
 2648:       if (TRACE_CASE && case_offset_counter != 0)
 2649: 	{
 2650: 	  info->insn_type = dis_noninsn;
 2651: 	  advance += 2;
 2652: 
 2653: 	  /* If to print data as offsets, then shortcut here.  */
 2654: 	  (*info->fprintf_func) (info->stream, "case %ld%s: -> ",
 2655: 				 case_offset + no_of_case_offsets
 2656: 				 - case_offset_counter,
 2657: 				 case_offset_counter == 1 ? "/default" :
 2658: 				 "");
 2659: 
 2660: 	  (*info->print_address_func) ((bfd_vma)
 2661: 				       ((short) (insn)
 2662: 					+ (long) (addr
 2663: 						  - (no_of_case_offsets
 2664: 						     - case_offset_counter)
 2665: 						  * 2)), info);
 2666: 	  case_offset_counter--;
 2667: 
 2668: 	  /* The default case start (without a "sub" or "add") must be
 2669: 	     zero.  */
 2670: 	  if (case_offset_counter == 0)
 2671: 	    case_offset = 0;
 2672: 	}
 2673:       else if (insn == 0)
 2674: 	{
 2675: 	  /* We're often called to disassemble zeroes.  While this is a
 2676: 	     valid "bcc .+2" insn, it is also useless enough and enough
 2677: 	     of a nuiscance that we will just output "bcc .+2" for it
 2678: 	     and signal it as a noninsn.  */
 2679: 	  (*info->fprintf_func) (info->stream,
 2680: 				 disdata->distype == cris_dis_v32
 2681: 				 ? "bcc ." : "bcc .+2");
 2682: 	  info->insn_type = dis_noninsn;
 2683: 	  advance += 2;
 2684: 	}
 2685:       else
 2686: 	{
 2687: 	  const struct cris_opcode *prefix_opcodep = NULL;
 2688: 	  unsigned char *prefix_buffer = bufp;
 2689: 	  unsigned int prefix_insn = insn;
 2690: 	  int prefix_size = 0;
 2691: 
 2692: 	  matchedp = get_opcode_entry (insn, NO_CRIS_PREFIX, disdata);
 2693: 
 2694: 	  /* Check if we're supposed to write out prefixes as address
 2695: 	     modes and if this was a prefix.  */
 2696: 	  if (matchedp != NULL && PARSE_PREFIX && matchedp->args[0] == 'p')
 2697: 	    {
 2698: 	      /* If it's a prefix, put it into the prefix vars and get the
 2699: 		 main insn.  */
 2700: 	      prefix_size = bytes_to_skip (prefix_insn, matchedp,
 2701: 					   disdata->distype, NULL);
 2702: 	      prefix_opcodep = matchedp;
 2703: 
 2704: 	      insn = bufp[prefix_size] + bufp[prefix_size + 1] * 256;
 2705: 	      matchedp = get_opcode_entry (insn, prefix_insn, disdata);
 2706: 
 2707: 	      if (matchedp != NULL)
 2708: 		{
 2709: 		  addr += prefix_size;
 2710: 		  bufp += prefix_size;
 2711: 		  advance += prefix_size;
 2712: 		}
 2713: 	      else
 2714: 		{
 2715: 		  /* The "main" insn wasn't valid, at least not when
 2716: 		     prefixed.  Put back things enough to output the
 2717: 		     prefix insn only, as a normal insn.  */
 2718: 		  matchedp = prefix_opcodep;
 2719: 		  insn = prefix_insn;
 2720: 		  prefix_opcodep = NULL;
 2721: 		}
 2722: 	    }
 2723: 
 2724: 	  if (matchedp == NULL)
 2725: 	    {
 2726: 	      (*info->fprintf_func) (info->stream, "??0x%x", insn);
 2727: 	      advance += 2;
 2728: 
 2729: 	      info->insn_type = dis_noninsn;
 2730: 	    }
 2731: 	  else
 2732: 	    {
 2733: 	      advance
 2734: 		+= bytes_to_skip (insn, matchedp, disdata->distype,
 2735: 				  prefix_opcodep);
 2736: 
 2737: 	      /* The info_type and assorted fields will be set according
 2738: 		 to the operands.   */
 2739: 	      print_with_operands (matchedp, insn, bufp, addr, info,
 2740: 				   prefix_opcodep, prefix_insn,
 2741: 				   prefix_buffer, with_reg_prefix);
 2742: 	    }
 2743: 	}
 2744:     }
 2745:   else
 2746:     info->insn_type = dis_noninsn;
 2747: 
 2748:   /* If we read less than MAX_BYTES_PER_CRIS_INSN, i.e. we got an error
 2749:      status when reading that much, and the insn decoding indicated a
 2750:      length exceeding what we read, there is an error.  */
 2751:   if (status != 0 && (nbytes == 0 || advance > nbytes))
 2752:     {
 2753:       (*info->memory_error_func) (status, memaddr, info);
 2754:       return -1;
 2755:     }
 2756: 
 2757:   /* Max supported insn size with one folded prefix insn.  */
 2758:   info->bytes_per_line = MAX_BYTES_PER_CRIS_INSN;
 2759: 
 2760:   /* I would like to set this to a fixed value larger than the actual
 2761:      number of bytes to print in order to avoid spaces between bytes,
 2762:      but objdump.c (2.9.1) does not like that, so we print 16-bit
 2763:      chunks, which is the next choice.  */
 2764:   info->bytes_per_chunk = 2;
 2765: 
 2766:   /* Printing bytes in order of increasing addresses makes sense,
 2767:      especially on a little-endian target.
 2768:      This is completely the opposite of what you think; setting this to
 2769:      BFD_ENDIAN_LITTLE will print bytes in order N..0 rather than the 0..N
 2770:      we want.  */
 2771:   info->display_endian = BFD_ENDIAN_BIG;
 2772: 
 2773:   return advance;
 2774: }
 2775: 
 2776: /* Disassemble, prefixing register names with `$'.  CRIS v0..v10.  */
 2777: #if 0
 2778: static int
 2779: print_insn_cris_with_register_prefix (bfd_vma vma,
 2780: 				      disassemble_info *info)
 2781: {
 2782:   if (info->private_data == NULL
 2783:       && !cris_parse_disassembler_options (info, cris_dis_v0_v10))
 2784:     return -1;
 2785:   return print_insn_cris_generic (vma, info, TRUE);
 2786: }
 2787: #endif
 2788: /* Disassemble, prefixing register names with `$'.  CRIS v32.  */
 2789: 
 2790: static int
 2791: print_insn_crisv32_with_register_prefix (bfd_vma vma,
 2792: 					 disassemble_info *info)
 2793: {
 2794:   if (info->private_data == NULL
 2795:       && !cris_parse_disassembler_options (info, cris_dis_v32))
 2796:     return -1;
 2797:   return print_insn_cris_generic (vma, info, TRUE);
 2798: }
 2799: 
 2800: #if 0
 2801: /* Disassemble, prefixing register names with `$'.
 2802:    Common v10 and v32 subset.  */
 2803: 
 2804: static int
 2805: print_insn_crisv10_v32_with_register_prefix (bfd_vma vma,
 2806: 					     disassemble_info *info)
 2807: {
 2808:   if (info->private_data == NULL
 2809:       && !cris_parse_disassembler_options (info, cris_dis_common_v10_v32))
 2810:     return -1;
 2811:   return print_insn_cris_generic (vma, info, TRUE);
 2812: }
 2813: 
 2814: /* Disassemble, no prefixes on register names.  CRIS v0..v10.  */
 2815: 
 2816: static int
 2817: print_insn_cris_without_register_prefix (bfd_vma vma,
 2818: 					 disassemble_info *info)
 2819: {
 2820:   if (info->private_data == NULL
 2821:       && !cris_parse_disassembler_options (info, cris_dis_v0_v10))
 2822:     return -1;
 2823:   return print_insn_cris_generic (vma, info, FALSE);
 2824: }
 2825: 
 2826: /* Disassemble, no prefixes on register names.  CRIS v32.  */
 2827: 
 2828: static int
 2829: print_insn_crisv32_without_register_prefix (bfd_vma vma,
 2830: 					    disassemble_info *info)
 2831: {
 2832:   if (info->private_data == NULL
 2833:       && !cris_parse_disassembler_options (info, cris_dis_v32))
 2834:     return -1;
 2835:   return print_insn_cris_generic (vma, info, FALSE);
 2836: }
 2837: 
 2838: /* Disassemble, no prefixes on register names.
 2839:    Common v10 and v32 subset.  */
 2840: 
 2841: static int
 2842: print_insn_crisv10_v32_without_register_prefix (bfd_vma vma,
 2843: 						disassemble_info *info)
 2844: {
 2845:   if (info->private_data == NULL
 2846:       && !cris_parse_disassembler_options (info, cris_dis_common_v10_v32))
 2847:     return -1;
 2848:   return print_insn_cris_generic (vma, info, FALSE);
 2849: }
 2850: #endif
 2851: 
 2852: int
 2853: print_insn_crisv32 (bfd_vma vma,
 2854: 		    disassemble_info *info)
 2855: {
 2856:   return print_insn_crisv32_with_register_prefix(vma, info);
 2857: }
 2858: 
 2859: /* Return a disassembler-function that prints registers with a `$' prefix,
 2860:    or one that prints registers without a prefix.
 2861:    FIXME: We should improve the solution to avoid the multitude of
 2862:    functions seen above.  */
 2863: #if 0
 2864: disassembler_ftype
 2865: cris_get_disassembler (bfd *abfd)
 2866: {
 2867:   /* If there's no bfd in sight, we return what is valid as input in all
 2868:      contexts if fed back to the assembler: disassembly *with* register
 2869:      prefix.  Unfortunately this will be totally wrong for v32.  */
 2870:   if (abfd == NULL)
 2871:     return print_insn_cris_with_register_prefix;
 2872: 
 2873:   if (bfd_get_symbol_leading_char (abfd) == 0)
 2874:     {
 2875:       if (bfd_get_mach (abfd) == bfd_mach_cris_v32)
 2876: 	return print_insn_crisv32_with_register_prefix;
 2877:       if (bfd_get_mach (abfd) == bfd_mach_cris_v10_v32)
 2878: 	return print_insn_crisv10_v32_with_register_prefix;
 2879: 
 2880:       /* We default to v10.  This may be specifically specified in the
 2881: 	 bfd mach, but is also the default setting.  */
 2882:       return print_insn_cris_with_register_prefix;
 2883:     }
 2884: 
 2885:   if (bfd_get_mach (abfd) == bfd_mach_cris_v32)
 2886:     return print_insn_crisv32_without_register_prefix;
 2887:   if (bfd_get_mach (abfd) == bfd_mach_cris_v10_v32)
 2888:     return print_insn_crisv10_v32_without_register_prefix;
 2889:   return print_insn_cris_without_register_prefix;
 2890: }
 2891: #endif
 2892: /* Local variables:
 2893:    eval: (c-set-style "gnu")
 2894:    indent-tabs-mode: t
 2895:    End:  */

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