Diff for /qemu/dis-asm.h between versions 1.1.1.3 and 1.1.1.4

version 1.1.1.3, 2018/04/24 16:40:38 version 1.1.1.4, 2018/04/24 16:47:17
Line 44  enum bfd_flavour { Line 44  enum bfd_flavour {
   
 enum bfd_endian { BFD_ENDIAN_BIG, BFD_ENDIAN_LITTLE, BFD_ENDIAN_UNKNOWN };  enum bfd_endian { BFD_ENDIAN_BIG, BFD_ENDIAN_LITTLE, BFD_ENDIAN_UNKNOWN };
   
 enum bfd_architecture   enum bfd_architecture
 {  {
   bfd_arch_unknown,    /* File arch not known */    bfd_arch_unknown,    /* File arch not known */
   bfd_arch_obscure,    /* Arch known, not one of these */    bfd_arch_obscure,    /* Arch known, not one of these */
Line 67  enum bfd_architecture  Line 67  enum bfd_architecture 
 #define bfd_mach_mcf5249   16  #define bfd_mach_mcf5249   16
 #define bfd_mach_mcf547x   17  #define bfd_mach_mcf547x   17
 #define bfd_mach_mcf548x   18  #define bfd_mach_mcf548x   18
   bfd_arch_vax,        /* DEC Vax */       bfd_arch_vax,        /* DEC Vax */
   bfd_arch_i960,       /* Intel 960 */    bfd_arch_i960,       /* Intel 960 */
      /* The order of the following is important.       /* The order of the following is important.
        lower number indicates a machine type that          lower number indicates a machine type that
        only accepts a subset of the instructions         only accepts a subset of the instructions
        available to machines with higher numbers.         available to machines with higher numbers.
        The exception is the "ca", which is         The exception is the "ca", which is
        incompatible with all other machines except          incompatible with all other machines except
        "core". */         "core". */
   
 #define bfd_mach_i960_core      1  #define bfd_mach_i960_core      1
Line 181  enum bfd_architecture  Line 181  enum bfd_architecture 
 #define bfd_mach_sh4al_dsp  0x4d  #define bfd_mach_sh4al_dsp  0x4d
 #define bfd_mach_sh5        0x50  #define bfd_mach_sh5        0x50
   bfd_arch_alpha,      /* Dec Alpha */    bfd_arch_alpha,      /* Dec Alpha */
   #define bfd_mach_alpha 1
   bfd_arch_arm,        /* Advanced Risc Machines ARM */    bfd_arch_arm,        /* Advanced Risc Machines ARM */
 #define bfd_mach_arm_2         1  #define bfd_mach_arm_unknown    0
 #define bfd_mach_arm_2a                2  #define bfd_mach_arm_2          1
 #define bfd_mach_arm_3         3  #define bfd_mach_arm_2a         2
 #define bfd_mach_arm_3M        4  #define bfd_mach_arm_3          3
 #define bfd_mach_arm_4                 5  #define bfd_mach_arm_3M         4
 #define bfd_mach_arm_4T        6  #define bfd_mach_arm_4          5
   #define bfd_mach_arm_4T         6
   #define bfd_mach_arm_5          7
   #define bfd_mach_arm_5T         8
   #define bfd_mach_arm_5TE        9
   #define bfd_mach_arm_XScale     10
   #define bfd_mach_arm_ep9312     11
   #define bfd_mach_arm_iWMMXt     12
   #define bfd_mach_arm_iWMMXt2    13
   bfd_arch_ns32k,      /* National Semiconductors ns32000 */    bfd_arch_ns32k,      /* National Semiconductors ns32000 */
   bfd_arch_w65,        /* WDC 65816 */    bfd_arch_w65,        /* WDC 65816 */
   bfd_arch_tic30,      /* Texas Instruments TMS320C30 */    bfd_arch_tic30,      /* Texas Instruments TMS320C30 */
Line 199  enum bfd_architecture  Line 208  enum bfd_architecture 
 #define bfd_mach_m32r          0  /* backwards compatibility */  #define bfd_mach_m32r          0  /* backwards compatibility */
   bfd_arch_mn10200,    /* Matsushita MN10200 */    bfd_arch_mn10200,    /* Matsushita MN10200 */
   bfd_arch_mn10300,    /* Matsushita MN10300 */    bfd_arch_mn10300,    /* Matsushita MN10300 */
     bfd_arch_cris,       /* Axis CRIS */
   #define bfd_mach_cris_v0_v10   255
   #define bfd_mach_cris_v32      32
   #define bfd_mach_cris_v10_v32  1032
   bfd_arch_last    bfd_arch_last
   };    };
   #define bfd_mach_s390_31 31
   #define bfd_mach_s390_64 64
   
 typedef struct symbol_cache_entry  typedef struct symbol_cache_entry
 {  {
Line 225  enum dis_insn_type { Line 240  enum dis_insn_type {
   dis_dref2                     /* Two data references in instruction */    dis_dref2                     /* Two data references in instruction */
 };  };
   
 /* This struct is passed into the instruction decoding routine,   /* This struct is passed into the instruction decoding routine,
    and is passed back out into each callback.  The various fields are used     and is passed back out into each callback.  The various fields are used
    for conveying information from your main routine into your callbacks,     for conveying information from your main routine into your callbacks,
    for passing information into the instruction decoders (such as the     for passing information into the instruction decoders (such as the
Line 377  extern int print_insn_d10v  PARAMS ((bfd Line 392  extern int print_insn_d10v  PARAMS ((bfd
 extern int print_insn_v850              PARAMS ((bfd_vma, disassemble_info*));  extern int print_insn_v850              PARAMS ((bfd_vma, disassemble_info*));
 extern int print_insn_tic30             PARAMS ((bfd_vma, disassemble_info*));  extern int print_insn_tic30             PARAMS ((bfd_vma, disassemble_info*));
 extern int print_insn_ppc               PARAMS ((bfd_vma, disassemble_info*));  extern int print_insn_ppc               PARAMS ((bfd_vma, disassemble_info*));
   extern int print_insn_alpha             PARAMS ((bfd_vma, disassemble_info*));
   extern int print_insn_s390              PARAMS ((bfd_vma, disassemble_info*));
   extern int print_insn_crisv32           PARAMS ((bfd_vma, disassemble_info*));
   
 #if 0  #if 0
 /* Fetch the disassembler for a given BFD, if that support is available.  */  /* Fetch the disassembler for a given BFD, if that support is available.  */
Line 419  extern int generic_symbol_at_address Line 437  extern int generic_symbol_at_address
 /* Call this macro to initialize only the internal variables for the  /* Call this macro to initialize only the internal variables for the
    disassembler.  Architecture dependent things such as byte order, or machine     disassembler.  Architecture dependent things such as byte order, or machine
    variant are not touched by this macro.  This makes things much easier for     variant are not touched by this macro.  This makes things much easier for
    GDB which must initialize these things seperatly.  */     GDB which must initialize these things separately.  */
   
 #define INIT_DISASSEMBLE_INFO_NO_ARCH(INFO, STREAM, FPRINTF_FUNC) \  #define INIT_DISASSEMBLE_INFO_NO_ARCH(INFO, STREAM, FPRINTF_FUNC) \
   (INFO).fprintf_func = (FPRINTF_FUNC), \    (INFO).fprintf_func = (FPRINTF_FUNC), \

Removed from v.1.1.1.3  
changed lines
  Added in v.1.1.1.4


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