Diff for /qemu/dyngen.h between versions 1.1.1.4 and 1.1.1.5

version 1.1.1.4, 2018/04/24 16:44:42 version 1.1.1.5, 2018/04/24 16:47:03
Line 1 Line 1
 /*  /*
  * dyngen helpers   * dyngen helpers
  *    *
  *  Copyright (c) 2003 Fabrice Bellard   *  Copyright (c) 2003 Fabrice Bellard
  *   *
  * This library is free software; you can redistribute it and/or   * This library is free software; you can redistribute it and/or
Line 28  int __op_param1, __op_param2, __op_param Line 28  int __op_param1, __op_param2, __op_param
 #endif  #endif
 int __op_jmp0, __op_jmp1, __op_jmp2, __op_jmp3;  int __op_jmp0, __op_jmp1, __op_jmp2, __op_jmp3;
   
 #ifdef __i386__  #if defined(__i386__) || defined(__x86_64__) || defined(__s390__)
 static inline void flush_icache_range(unsigned long start, unsigned long stop)  
 {  
 }  
 #endif  
   
 #ifdef __x86_64__  
 static inline void flush_icache_range(unsigned long start, unsigned long stop)  static inline void flush_icache_range(unsigned long start, unsigned long stop)
 {  {
 }  }
 #endif  #elif defined(__ia64__)
   
 #ifdef __s390__  
 static inline void flush_icache_range(unsigned long start, unsigned long stop)  
 {  
 }  
 #endif  
   
 #ifdef __ia64__  
 static inline void flush_icache_range(unsigned long start, unsigned long stop)  static inline void flush_icache_range(unsigned long start, unsigned long stop)
 {  {
     while (start < stop) {      while (start < stop) {
Line 55  static inline void flush_icache_range(un Line 41  static inline void flush_icache_range(un
     }      }
     asm volatile (";;sync.i;;srlz.i;;");      asm volatile (";;sync.i;;srlz.i;;");
 }  }
 #endif  #elif defined(__powerpc__)
   
 #ifdef __powerpc__  
   
 #define MIN_CACHE_LINE_SIZE 8 /* conservative value */  #define MIN_CACHE_LINE_SIZE 8 /* conservative value */
   
 static void inline flush_icache_range(unsigned long start, unsigned long stop)  static inline void flush_icache_range(unsigned long start, unsigned long stop)
 {  {
     unsigned long p;      unsigned long p;
   
     start &= ~(MIN_CACHE_LINE_SIZE - 1);      start &= ~(MIN_CACHE_LINE_SIZE - 1);
     stop = (stop + MIN_CACHE_LINE_SIZE - 1) & ~(MIN_CACHE_LINE_SIZE - 1);      stop = (stop + MIN_CACHE_LINE_SIZE - 1) & ~(MIN_CACHE_LINE_SIZE - 1);
       
     for (p = start; p < stop; p += MIN_CACHE_LINE_SIZE) {      for (p = start; p < stop; p += MIN_CACHE_LINE_SIZE) {
         asm volatile ("dcbst 0,%0" : : "r"(p) : "memory");          asm volatile ("dcbst 0,%0" : : "r"(p) : "memory");
     }      }
Line 78  static void inline flush_icache_range(un Line 62  static void inline flush_icache_range(un
     asm volatile ("sync" : : : "memory");      asm volatile ("sync" : : : "memory");
     asm volatile ("isync" : : : "memory");      asm volatile ("isync" : : : "memory");
 }  }
 #endif  #elif defined(__alpha__)
   
 #ifdef __alpha__  
 static inline void flush_icache_range(unsigned long start, unsigned long stop)  static inline void flush_icache_range(unsigned long start, unsigned long stop)
 {  {
     asm ("imb");      asm ("imb");
 }  }
 #endif  #elif defined(__sparc__)
   static inline void flush_icache_range(unsigned long start, unsigned long stop)
 #ifdef __sparc__  
   
 static void inline flush_icache_range(unsigned long start, unsigned long stop)  
 {  {
         unsigned long p;          unsigned long p;
   
Line 99  static void inline flush_icache_range(un Line 78  static void inline flush_icache_range(un
         for (; p < stop; p += 8)          for (; p < stop; p += 8)
                 __asm__ __volatile__("flush\t%0" : : "r" (p));                  __asm__ __volatile__("flush\t%0" : : "r" (p));
 }  }
   #elif defined(__arm__)
 #endif  
   
 #ifdef __arm__  
 static inline void flush_icache_range(unsigned long start, unsigned long stop)  static inline void flush_icache_range(unsigned long start, unsigned long stop)
 {  {
     register unsigned long _beg __asm ("a1") = start;      register unsigned long _beg __asm ("a1") = start;
Line 110  static inline void flush_icache_range(un Line 86  static inline void flush_icache_range(un
     register unsigned long _flg __asm ("a3") = 0;      register unsigned long _flg __asm ("a3") = 0;
     __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));      __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
 }  }
 #endif  #elif defined(__mc68000)
   
 #ifdef __mc68000  # include <asm/cachectl.h>
 #include <asm/cachectl.h>  
 static inline void flush_icache_range(unsigned long start, unsigned long stop)  static inline void flush_icache_range(unsigned long start, unsigned long stop)
 {  {
     cacheflush(start,FLUSH_SCOPE_LINE,FLUSH_CACHE_BOTH,stop-start+16);      cacheflush(start,FLUSH_SCOPE_LINE,FLUSH_CACHE_BOTH,stop-start+16);
 }  }
   #elif defined(__mips__)
   
   #include <sys/cachectl.h>
   static inline void flush_icache_range(unsigned long start, unsigned long stop)
   {
       _flush_cache ((void *)start, stop - start, BCACHE);
   }
   #else
   #error unsupported CPU
 #endif  #endif
   
 #ifdef __alpha__  #ifdef __alpha__
Line 164  static inline void arm_reloc_pc24(uint32 Line 148  static inline void arm_reloc_pc24(uint32
 }  }
   
 static uint8_t *arm_flush_ldr(uint8_t *gen_code_ptr,  static uint8_t *arm_flush_ldr(uint8_t *gen_code_ptr,
                               LDREntry *ldr_start, LDREntry *ldr_end,                                 LDREntry *ldr_start, LDREntry *ldr_end,
                               uint32_t *data_start, uint32_t *data_end,                                 uint32_t *data_start, uint32_t *data_end,
                               int gen_jmp)                                int gen_jmp)
 {  {
     LDREntry *le;      LDREntry *le;
Line 174  static uint8_t *arm_flush_ldr(uint8_t *g Line 158  static uint8_t *arm_flush_ldr(uint8_t *g
     uint8_t *data_ptr;      uint8_t *data_ptr;
     uint32_t insn;      uint32_t insn;
     uint32_t mask;      uint32_t mask;
    
     data_size = (data_end - data_start) << 2;      data_size = (data_end - data_start) << 2;
   
     if (gen_jmp) {      if (gen_jmp) {
Line 185  static uint8_t *arm_flush_ldr(uint8_t *g Line 169  static uint8_t *arm_flush_ldr(uint8_t *g
         arm_reloc_pc24((uint32_t *)gen_code_ptr, 0xeafffffe, target);          arm_reloc_pc24((uint32_t *)gen_code_ptr, 0xeafffffe, target);
         gen_code_ptr += 4;          gen_code_ptr += 4;
     }      }
      
     /* copy the data */      /* copy the data */
     data_ptr = gen_code_ptr;      data_ptr = gen_code_ptr;
     memcpy(gen_code_ptr, data_start, data_size);      memcpy(gen_code_ptr, data_start, data_size);
     gen_code_ptr += data_size;      gen_code_ptr += data_size;
       
     /* patch the ldr to point to the data */      /* patch the ldr to point to the data */
     for(le = ldr_start; le < ldr_end; le++) {      for(le = ldr_start; le < ldr_end; le++) {
         ptr = (uint32_t *)le->ptr;          ptr = (uint32_t *)le->ptr;
         offset = ((unsigned long)(le->data_ptr) - (unsigned long)data_start) +           offset = ((unsigned long)(le->data_ptr) - (unsigned long)data_start) +
             (unsigned long)data_ptr -               (unsigned long)data_ptr -
             (unsigned long)ptr - 8;              (unsigned long)ptr - 8;
         if (offset < 0) {          if (offset < 0) {
             fprintf(stderr, "Negative constant pool offset\n");              fprintf(stderr, "Negative constant pool offset\n");
Line 248  static uint8_t *arm_flush_ldr(uint8_t *g Line 232  static uint8_t *arm_flush_ldr(uint8_t *g
   
 #ifdef __ia64  #ifdef __ia64
   
   
 /* Patch instruction with "val" where "mask" has 1 bits. */  /* Patch instruction with "val" where "mask" has 1 bits. */
 static inline void ia64_patch (uint64_t insn_addr, uint64_t mask, uint64_t val)  static inline void ia64_patch (uint64_t insn_addr, uint64_t mask, uint64_t val)
 {  {
Line 409  static inline void ia64_apply_fixes (uin Line 392  static inline void ia64_apply_fixes (uin
         0x05, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, /* nop 0; brl IP */          0x05, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, /* nop 0; brl IP */
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0          0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0
     };      };
     uint8_t *gen_code_ptr = *gen_code_pp, *plt_start, *got_start, *vp;      uint8_t *gen_code_ptr = *gen_code_pp, *plt_start, *got_start;
       uint64_t *vp;
     struct ia64_fixup *fixup;      struct ia64_fixup *fixup;
     unsigned int offset = 0;      unsigned int offset = 0;
     struct fdesc {      struct fdesc {
Line 446  static inline void ia64_apply_fixes (uin Line 430  static inline void ia64_apply_fixes (uin
     /* First, create the GOT: */      /* First, create the GOT: */
     for (fixup = ltoff_fixes; fixup; fixup = fixup->next) {      for (fixup = ltoff_fixes; fixup; fixup = fixup->next) {
         /* first check if we already have this value in the GOT: */          /* first check if we already have this value in the GOT: */
         for (vp = got_start; vp < gen_code_ptr; ++vp)          for (vp = (uint64_t *) got_start; vp < (uint64_t *) gen_code_ptr; ++vp)
             if (*(uint64_t *) vp == fixup->value)              if (*vp == fixup->value)
                 break;                  break;
         if (vp == gen_code_ptr) {          if (vp == (uint64_t *) gen_code_ptr) {
             /* Nope, we need to put the value in the GOT: */              /* Nope, we need to put the value in the GOT: */
             *(uint64_t *) vp = fixup->value;              *vp = fixup->value;
             gen_code_ptr += 8;              gen_code_ptr += 8;
         }          }
         ia64_imm22(fixup->addr, (long) vp - gp);          ia64_imm22(fixup->addr, (long) vp - gp);

Removed from v.1.1.1.4  
changed lines
  Added in v.1.1.1.5


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