Diff for /qemu/exec-all.h between versions and

version, 2018/04/24 16:37:52 version, 2018/04/24 16:40:28
Line 62  extern target_ulong gen_opc_npc[OPC_BUF_ Line 62  extern target_ulong gen_opc_npc[OPC_BUF_
 extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];  extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
 extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];  extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
 extern target_ulong gen_opc_jump_pc[2];  extern target_ulong gen_opc_jump_pc[2];
   extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];
 typedef void (GenOpFunc)(void);  typedef void (GenOpFunc)(void);
 typedef void (GenOpFunc1)(long);  typedef void (GenOpFunc1)(long);
Line 91  int cpu_restore_state_copy(struct Transl Line 92  int cpu_restore_state_copy(struct Transl
                            CPUState *env, unsigned long searched_pc,                             CPUState *env, unsigned long searched_pc,
                            void *puc);                             void *puc);
 void cpu_resume_from_signal(CPUState *env1, void *puc);  void cpu_resume_from_signal(CPUState *env1, void *puc);
 void cpu_exec_init(void);  void cpu_exec_init(CPUState *env);
 int page_unprotect(unsigned long address, unsigned long pc, void *puc);  int page_unprotect(target_ulong address, unsigned long pc, void *puc);
 void tb_invalidate_phys_page_range(target_ulong start, target_ulong end,   void tb_invalidate_phys_page_range(target_ulong start, target_ulong end, 
                                    int is_cpu_write_access);                                     int is_cpu_write_access);
 void tb_invalidate_page_range(target_ulong start, target_ulong end);  void tb_invalidate_page_range(target_ulong start, target_ulong end);
 void tlb_flush_page(CPUState *env, target_ulong addr);  void tlb_flush_page(CPUState *env, target_ulong addr);
 void tlb_flush(CPUState *env, int flush_global);  void tlb_flush(CPUState *env, int flush_global);
 int tlb_set_page(CPUState *env, target_ulong vaddr,   int tlb_set_page_exec(CPUState *env, target_ulong vaddr, 
                  target_phys_addr_t paddr, int prot,                         target_phys_addr_t paddr, int prot, 
                  int is_user, int is_softmmu);                        int is_user, int is_softmmu);
   static inline int tlb_set_page(CPUState *env, target_ulong vaddr, 
                                  target_phys_addr_t paddr, int prot, 
                                  int is_user, int is_softmmu)
       if (prot & PAGE_READ)
           prot |= PAGE_EXEC;
       return tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
 #define CODE_GEN_MAX_SIZE        65536  #define CODE_GEN_MAX_SIZE        65536
 #define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */  #define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */
 #define CODE_GEN_HASH_BITS     15  
 #define CODE_GEN_PHYS_HASH_BITS     15  #define CODE_GEN_PHYS_HASH_BITS     15
Line 167  typedef struct TranslationBlock { Line 173  typedef struct TranslationBlock {
 #define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */  #define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */
     uint8_t *tc_ptr;    /* pointer to the translated code */      uint8_t *tc_ptr;    /* pointer to the translated code */
     struct TranslationBlock *hash_next; /* next matching tb for virtual address */  
     /* next matching tb for physical address. */      /* next matching tb for physical address. */
     struct TranslationBlock *phys_hash_next;       struct TranslationBlock *phys_hash_next; 
     /* first and second physical page containing code. The lower bit      /* first and second physical page containing code. The lower bit
Line 191  typedef struct TranslationBlock { Line 196  typedef struct TranslationBlock {
     struct TranslationBlock *jmp_first;      struct TranslationBlock *jmp_first;
 } TranslationBlock;  } TranslationBlock;
 static inline unsigned int tb_hash_func(target_ulong pc)  static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
 {  {
     return pc & (CODE_GEN_HASH_SIZE - 1);      return (pc ^ (pc >> TB_JMP_CACHE_BITS)) & (TB_JMP_CACHE_SIZE - 1);
 }  }
 static inline unsigned int tb_phys_hash_func(unsigned long pc)  static inline unsigned int tb_phys_hash_func(unsigned long pc)
Line 203  static inline unsigned int tb_phys_hash_ Line 208  static inline unsigned int tb_phys_hash_
 TranslationBlock *tb_alloc(target_ulong pc);  TranslationBlock *tb_alloc(target_ulong pc);
 void tb_flush(CPUState *env);  void tb_flush(CPUState *env);
 void tb_link(TranslationBlock *tb);  
 void tb_link_phys(TranslationBlock *tb,   void tb_link_phys(TranslationBlock *tb, 
                   target_ulong phys_pc, target_ulong phys_page2);                    target_ulong phys_pc, target_ulong phys_page2);
 extern TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE];  
 extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];  extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
 extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];  extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
 extern uint8_t *code_gen_ptr;  extern uint8_t *code_gen_ptr;
 /* find a translation block in the translation cache. If not found,  
    return NULL and the pointer to the last element of the list in pptb */  
 static inline TranslationBlock *tb_find(TranslationBlock ***pptb,  
                                         target_ulong pc,   
                                         target_ulong cs_base,  
                                         unsigned int flags)  
     TranslationBlock **ptb, *tb;  
     unsigned int h;  
     h = tb_hash_func(pc);  
     ptb = &tb_hash[h];  
     for(;;) {  
         tb = *ptb;  
         if (!tb)  
         if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags)  
             return tb;  
         ptb = &tb->hash_next;  
     *pptb = ptb;  
     return NULL;  
 #if defined(USE_DIRECT_JUMP)  #if defined(USE_DIRECT_JUMP)
 #if defined(__powerpc__)  #if defined(__powerpc__)
Line 365  dummy_label ## n: ;\ Line 343  dummy_label ## n: ;\
 #endif  #endif
 /* XXX: will be suppressed */  
 #define JUMP_TB(opname, tbparam, n, eip)\  
 do {\  
     GOTO_TB(opname, tbparam, n);\  
     T0 = (long)(tbparam) + (n);\  
     EIP = (int32_t)eip;\  
 } while (0)  
 extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];  extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
 extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];  extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
 extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];  extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
Line 589  static inline target_ulong get_phys_addr Line 558  static inline target_ulong get_phys_addr
     is_user = ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM);      is_user = ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM);
 #elif defined (TARGET_SPARC)  #elif defined (TARGET_SPARC)
     is_user = (env->psrs == 0);      is_user = (env->psrs == 0);
   #elif defined (TARGET_ARM)
       is_user = ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR);
   #elif defined (TARGET_SH4)
       is_user = ((env->sr & SR_MD) == 0);
 #else  #else
 #error "Unimplemented !"  #error unimplemented CPU
 #endif  #endif
     if (__builtin_expect(env->tlb_read[is_user][index].address !=       if (__builtin_expect(env->tlb_table[is_user][index].addr_code != 
                          (addr & TARGET_PAGE_MASK), 0)) {                           (addr & TARGET_PAGE_MASK), 0)) {
         ldub_code(addr);          ldub_code(addr);
     }      }
     pd = env->tlb_read[is_user][index].address & ~TARGET_PAGE_MASK;      pd = env->tlb_table[is_user][index].addr_code & ~TARGET_PAGE_MASK;
     if (pd > IO_MEM_ROM) {      if (pd > IO_MEM_ROM) {
         cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x%08lx\n", addr);          cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x%08lx\n", addr);
     }      }
     return addr + env->tlb_read[is_user][index].addend - (unsigned long)phys_ram_base;      return addr + env->tlb_table[is_user][index].addend - (unsigned long)phys_ram_base;
 }  }
 #endif  #endif
 #ifdef USE_KQEMU  #ifdef USE_KQEMU
 int kqemu_init(CPUState *env);  int kqemu_init(CPUState *env);
 int kqemu_cpu_exec(CPUState *env);  int kqemu_cpu_exec(CPUState *env);
 void kqemu_flush_page(CPUState *env, target_ulong addr);  void kqemu_flush_page(CPUState *env, target_ulong addr);
 void kqemu_flush(CPUState *env, int global);  void kqemu_flush(CPUState *env, int global);
 void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);  void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
   void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr);
 void kqemu_cpu_interrupt(CPUState *env);  void kqemu_cpu_interrupt(CPUState *env);
   void kqemu_record_dump(void);
 static inline int kqemu_is_ok(CPUState *env)  static inline int kqemu_is_ok(CPUState *env)
 {  {
     return(env->kqemu_enabled &&      return(env->kqemu_enabled &&
            (env->hflags & HF_CPL_MASK) == 3 &&  
            (env->eflags & IOPL_MASK) != IOPL_MASK &&  
            (env->cr[0] & CR0_PE_MASK) &&              (env->cr[0] & CR0_PE_MASK) && 
              !(env->hflags & HF_INHIBIT_IRQ_MASK) &&
            (env->eflags & IF_MASK) &&             (env->eflags & IF_MASK) &&
            !(env->eflags & VM_MASK));             !(env->eflags & VM_MASK) &&
              (env->kqemu_enabled == 2 || 
               ((env->hflags & HF_CPL_MASK) == 3 &&
                (env->eflags & IOPL_MASK) != IOPL_MASK)));
 }  }
 #endif  #endif

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