Annotation of qemu/exec-all.h, revision 1.1.1.15

1.1       root        1: /*
                      2:  * internal execution defines for qemu
1.1.1.6   root        3:  *
1.1       root        4:  *  Copyright (c) 2003 Fabrice Bellard
                      5:  *
                      6:  * This library is free software; you can redistribute it and/or
                      7:  * modify it under the terms of the GNU Lesser General Public
                      8:  * License as published by the Free Software Foundation; either
                      9:  * version 2 of the License, or (at your option) any later version.
                     10:  *
                     11:  * This library is distributed in the hope that it will be useful,
                     12:  * but WITHOUT ANY WARRANTY; without even the implied warranty of
                     13:  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
                     14:  * Lesser General Public License for more details.
                     15:  *
                     16:  * You should have received a copy of the GNU Lesser General Public
1.1.1.8   root       17:  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
1.1       root       18:  */
                     19: 
1.1.1.7   root       20: #ifndef _EXEC_ALL_H_
                     21: #define _EXEC_ALL_H_
                     22: 
                     23: #include "qemu-common.h"
                     24: 
1.1       root       25: /* allow to see translation results - the slowdown should be negligible, so we leave it */
                     26: #define DEBUG_DISAS
                     27: 
1.1.1.11  root       28: /* Page tracking code uses ram addresses in system mode, and virtual
                     29:    addresses in userspace mode.  Define tb_page_addr_t to be an appropriate
                     30:    type.  */
                     31: #if defined(CONFIG_USER_ONLY)
                     32: typedef abi_ulong tb_page_addr_t;
                     33: #else
                     34: typedef ram_addr_t tb_page_addr_t;
                     35: #endif
                     36: 
1.1       root       37: /* is_jmp field values */
                     38: #define DISAS_NEXT    0 /* next instruction can be analyzed */
                     39: #define DISAS_JUMP    1 /* only pc was modified dynamically */
                     40: #define DISAS_UPDATE  2 /* cpu state was modified dynamically */
                     41: #define DISAS_TB_JUMP 3 /* only pc was modified statically */
                     42: 
1.1.1.13  root       43: struct TranslationBlock;
1.1.1.7   root       44: typedef struct TranslationBlock TranslationBlock;
1.1       root       45: 
                     46: /* XXX: make safe guess about sizes */
1.1.1.13  root       47: #define MAX_OP_PER_INSTR 208
1.1.1.11  root       48: 
                     49: #if HOST_LONG_BITS == 32
                     50: #define MAX_OPC_PARAM_PER_ARG 2
                     51: #else
                     52: #define MAX_OPC_PARAM_PER_ARG 1
                     53: #endif
                     54: #define MAX_OPC_PARAM_IARGS 4
                     55: #define MAX_OPC_PARAM_OARGS 1
                     56: #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
                     57: 
                     58: /* A Call op needs up to 4 + 2N parameters on 32-bit archs,
                     59:  * and up to 4 + N parameters on 64-bit archs
                     60:  * (N = number of input arguments + output arguments).  */
                     61: #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
1.1.1.10  root       62: #define OPC_BUF_SIZE 640
1.1       root       63: #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
                     64: 
1.1.1.7   root       65: /* Maximum size a TCG op can expand to.  This is complicated because a
1.1.1.10  root       66:    single op may require several host instructions and register reloads.
                     67:    For now take a wild guess at 192 bytes, which should allow at least
1.1.1.7   root       68:    a couple of fixup instructions per argument.  */
1.1.1.10  root       69: #define TCG_MAX_OP_SIZE 192
1.1.1.7   root       70: 
                     71: #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
1.1       root       72: 
                     73: extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
                     74: extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
1.1.1.7   root       75: extern uint16_t gen_opc_icount[OPC_BUF_SIZE];
1.1       root       76: 
1.1.1.7   root       77: #include "qemu-log.h"
1.1       root       78: 
1.1.1.15! root       79: void gen_intermediate_code(CPUArchState *env, struct TranslationBlock *tb);
        !            80: void gen_intermediate_code_pc(CPUArchState *env, struct TranslationBlock *tb);
        !            81: void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb,
1.1.1.13  root       82:                           int pc_pos);
1.1       root       83: 
1.1.1.7   root       84: void cpu_gen_init(void);
1.1.1.15! root       85: int cpu_gen_code(CPUArchState *env, struct TranslationBlock *tb,
1.1.1.6   root       86:                  int *gen_code_size_ptr);
                     87: int cpu_restore_state(struct TranslationBlock *tb,
1.1.1.15! root       88:                       CPUArchState *env, uintptr_t searched_pc);
        !            89: void QEMU_NORETURN cpu_resume_from_signal(CPUArchState *env1, void *puc);
        !            90: void QEMU_NORETURN cpu_io_recompile(CPUArchState *env, uintptr_t retaddr);
        !            91: TranslationBlock *tb_gen_code(CPUArchState *env, 
1.1.1.7   root       92:                               target_ulong pc, target_ulong cs_base, int flags,
                     93:                               int cflags);
1.1.1.15! root       94: void cpu_exec_init(CPUArchState *env);
        !            95: void QEMU_NORETURN cpu_loop_exit(CPUArchState *env1);
        !            96: int page_unprotect(target_ulong address, uintptr_t pc, void *puc);
1.1.1.11  root       97: void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
1.1       root       98:                                    int is_cpu_write_access);
1.1.1.15! root       99: void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end,
        !           100:                               int is_cpu_write_access);
1.1.1.11  root      101: #if !defined(CONFIG_USER_ONLY)
1.1.1.15! root      102: /* cputlb.c */
        !           103: void tlb_flush_page(CPUArchState *env, target_ulong addr);
        !           104: void tlb_flush(CPUArchState *env, int flush_global);
        !           105: void tlb_set_page(CPUArchState *env, target_ulong vaddr,
1.1.1.11  root      106:                   target_phys_addr_t paddr, int prot,
                    107:                   int mmu_idx, target_ulong size);
1.1.1.15! root      108: void tb_invalidate_phys_addr(target_phys_addr_t addr);
        !           109: #else
        !           110: static inline void tlb_flush_page(CPUArchState *env, target_ulong addr)
        !           111: {
        !           112: }
        !           113: 
        !           114: static inline void tlb_flush(CPUArchState *env, int flush_global)
        !           115: {
        !           116: }
1.1.1.11  root      117: #endif
1.1       root      118: 
                    119: #define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */
                    120: 
                    121: #define CODE_GEN_PHYS_HASH_BITS     15
                    122: #define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)
                    123: 
1.1.1.7   root      124: #define MIN_CODE_GEN_BUFFER_SIZE     (1024 * 1024)
1.1       root      125: 
                    126: /* estimated block size for TB allocation */
                    127: /* XXX: use a per code average code fragment size and modulate it
                    128:    according to the host CPU */
                    129: #if defined(CONFIG_SOFTMMU)
                    130: #define CODE_GEN_AVG_BLOCK_SIZE 128
                    131: #else
                    132: #define CODE_GEN_AVG_BLOCK_SIZE 64
                    133: #endif
                    134: 
1.1.1.10  root      135: #if defined(_ARCH_PPC) || defined(__x86_64__) || defined(__arm__) || defined(__i386__)
1.1       root      136: #define USE_DIRECT_JUMP
1.1.1.14  root      137: #elif defined(CONFIG_TCG_INTERPRETER)
                    138: #define USE_DIRECT_JUMP
1.1       root      139: #endif
                    140: 
1.1.1.7   root      141: struct TranslationBlock {
1.1       root      142:     target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */
                    143:     target_ulong cs_base; /* CS base for this block */
1.1.1.6   root      144:     uint64_t flags; /* flags defining in which context the code was generated */
1.1       root      145:     uint16_t size;      /* size of target code for this block (1 <=
                    146:                            size <= TARGET_PAGE_SIZE) */
                    147:     uint16_t cflags;    /* compile flags */
1.1.1.7   root      148: #define CF_COUNT_MASK  0x7fff
                    149: #define CF_LAST_IO     0x8000 /* Last insn may be an IO access.  */
1.1       root      150: 
                    151:     uint8_t *tc_ptr;    /* pointer to the translated code */
                    152:     /* next matching tb for physical address. */
1.1.1.6   root      153:     struct TranslationBlock *phys_hash_next;
1.1       root      154:     /* first and second physical page containing code. The lower bit
                    155:        of the pointer tells the index in page_next[] */
1.1.1.6   root      156:     struct TranslationBlock *page_next[2];
1.1.1.11  root      157:     tb_page_addr_t page_addr[2];
1.1       root      158: 
                    159:     /* the following data are used to directly call another TB from
                    160:        the code of this one. */
                    161:     uint16_t tb_next_offset[2]; /* offset of original jump target */
                    162: #ifdef USE_DIRECT_JUMP
1.1.1.11  root      163:     uint16_t tb_jmp_offset[2]; /* offset of jump instruction */
1.1       root      164: #else
1.1.1.15! root      165:     uintptr_t tb_next[2]; /* address of jump generated code */
1.1       root      166: #endif
                    167:     /* list of TBs jumping to this one. This is a circular list using
                    168:        the two least significant bits of the pointers to tell what is
                    169:        the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
                    170:        jmp_first */
1.1.1.6   root      171:     struct TranslationBlock *jmp_next[2];
1.1       root      172:     struct TranslationBlock *jmp_first;
1.1.1.7   root      173:     uint32_t icount;
                    174: };
1.1       root      175: 
1.1.1.5   root      176: static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
                    177: {
                    178:     target_ulong tmp;
                    179:     tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
1.1.1.7   root      180:     return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
1.1.1.5   root      181: }
                    182: 
1.1.1.2   root      183: static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
1.1       root      184: {
1.1.1.5   root      185:     target_ulong tmp;
                    186:     tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
1.1.1.7   root      187:     return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
                    188:            | (tmp & TB_JMP_ADDR_MASK));
1.1       root      189: }
                    190: 
1.1.1.11  root      191: static inline unsigned int tb_phys_hash_func(tb_page_addr_t pc)
1.1       root      192: {
1.1.1.12  root      193:     return (pc >> 2) & (CODE_GEN_PHYS_HASH_SIZE - 1);
1.1       root      194: }
                    195: 
1.1.1.7   root      196: void tb_free(TranslationBlock *tb);
1.1.1.15! root      197: void tb_flush(CPUArchState *env);
1.1.1.11  root      198: void tb_link_page(TranslationBlock *tb,
                    199:                   tb_page_addr_t phys_pc, tb_page_addr_t phys_page2);
                    200: void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
1.1       root      201: 
                    202: extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
                    203: 
                    204: #if defined(USE_DIRECT_JUMP)
                    205: 
1.1.1.14  root      206: #if defined(CONFIG_TCG_INTERPRETER)
                    207: static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
                    208: {
                    209:     /* patch the branch destination */
                    210:     *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
                    211:     /* no need to flush icache explicitly */
                    212: }
                    213: #elif defined(_ARCH_PPC)
1.1.1.12  root      214: void ppc_tb_set_jmp_target(unsigned long jmp_addr, unsigned long addr);
1.1.1.7   root      215: #define tb_set_jmp_target1 ppc_tb_set_jmp_target
                    216: #elif defined(__i386__) || defined(__x86_64__)
1.1.1.15! root      217: static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
1.1       root      218: {
                    219:     /* patch the branch destination */
1.1.1.7   root      220:     *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
                    221:     /* no need to flush icache explicitly */
1.1       root      222: }
1.1.1.7   root      223: #elif defined(__arm__)
1.1.1.15! root      224: static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
1.1       root      225: {
1.1.1.12  root      226: #if !QEMU_GNUC_PREREQ(4, 1)
1.1.1.7   root      227:     register unsigned long _beg __asm ("a1");
                    228:     register unsigned long _end __asm ("a2");
                    229:     register unsigned long _flg __asm ("a3");
                    230: #endif
                    231: 
                    232:     /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
1.1.1.9   root      233:     *(uint32_t *)jmp_addr =
                    234:         (*(uint32_t *)jmp_addr & ~0xffffff)
                    235:         | (((addr - (jmp_addr + 8)) >> 2) & 0xffffff);
1.1.1.7   root      236: 
                    237: #if QEMU_GNUC_PREREQ(4, 1)
1.1.1.12  root      238:     __builtin___clear_cache((char *) jmp_addr, (char *) jmp_addr + 4);
1.1.1.7   root      239: #else
                    240:     /* flush icache */
                    241:     _beg = jmp_addr;
                    242:     _end = jmp_addr + 4;
                    243:     _flg = 0;
                    244:     __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
                    245: #endif
1.1       root      246: }
1.1.1.14  root      247: #else
                    248: #error tb_set_jmp_target1 is missing
1.1       root      249: #endif
                    250: 
1.1.1.6   root      251: static inline void tb_set_jmp_target(TranslationBlock *tb,
1.1.1.15! root      252:                                      int n, uintptr_t addr)
1.1       root      253: {
1.1.1.15! root      254:     uint16_t offset = tb->tb_jmp_offset[n];
        !           255:     tb_set_jmp_target1((uintptr_t)(tb->tc_ptr + offset), addr);
1.1       root      256: }
                    257: 
                    258: #else
                    259: 
                    260: /* set the jump target */
1.1.1.6   root      261: static inline void tb_set_jmp_target(TranslationBlock *tb,
1.1.1.15! root      262:                                      int n, uintptr_t addr)
1.1       root      263: {
                    264:     tb->tb_next[n] = addr;
                    265: }
                    266: 
                    267: #endif
                    268: 
1.1.1.6   root      269: static inline void tb_add_jump(TranslationBlock *tb, int n,
1.1       root      270:                                TranslationBlock *tb_next)
                    271: {
                    272:     /* NOTE: this test is only needed for thread safety */
                    273:     if (!tb->jmp_next[n]) {
                    274:         /* patch the native jump address */
1.1.1.15! root      275:         tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc_ptr);
1.1.1.6   root      276: 
1.1       root      277:         /* add in TB jmp circular list */
                    278:         tb->jmp_next[n] = tb_next->jmp_first;
1.1.1.15! root      279:         tb_next->jmp_first = (TranslationBlock *)((uintptr_t)(tb) | (n));
1.1       root      280:     }
                    281: }
                    282: 
1.1.1.15! root      283: TranslationBlock *tb_find_pc(uintptr_t pc_ptr);
1.1       root      284: 
1.1.1.7   root      285: #include "qemu-lock.h"
1.1       root      286: 
                    287: extern spinlock_t tb_lock;
                    288: 
                    289: extern int tb_invalidated_flag;
                    290: 
1.1.1.14  root      291: /* The return address may point to the start of the next instruction.
                    292:    Subtracting one gets us the call instruction itself.  */
                    293: #if defined(CONFIG_TCG_INTERPRETER)
                    294: /* Alpha and SH4 user mode emulations and Softmmu call GETPC().
                    295:    For all others, GETPC remains undefined (which makes TCI a little faster. */
                    296: # if defined(CONFIG_SOFTMMU) || defined(TARGET_ALPHA) || defined(TARGET_SH4)
1.1.1.15! root      297: extern uintptr_t tci_tb_ptr;
1.1.1.14  root      298: #  define GETPC() tci_tb_ptr
                    299: # endif
                    300: #elif defined(__s390__) && !defined(__s390x__)
1.1.1.15! root      301: # define GETPC() \
        !           302:     (((uintptr_t)__builtin_return_address(0) & 0x7fffffffUL) - 1)
1.1.1.14  root      303: #elif defined(__arm__)
                    304: /* Thumb return addresses have the low bit set, so we need to subtract two.
                    305:    This is still safe in ARM mode because instructions are 4 bytes.  */
1.1.1.15! root      306: # define GETPC() ((uintptr_t)__builtin_return_address(0) - 2)
1.1.1.14  root      307: #else
1.1.1.15! root      308: # define GETPC() ((uintptr_t)__builtin_return_address(0) - 1)
1.1.1.14  root      309: #endif
                    310: 
1.1       root      311: #if !defined(CONFIG_USER_ONLY)
                    312: 
1.1.1.15! root      313: struct MemoryRegion *iotlb_to_region(target_phys_addr_t index);
        !           314: uint64_t io_mem_read(struct MemoryRegion *mr, target_phys_addr_t addr,
        !           315:                      unsigned size);
        !           316: void io_mem_write(struct MemoryRegion *mr, target_phys_addr_t addr,
        !           317:                   uint64_t value, unsigned size);
1.1.1.11  root      318: 
1.1.1.15! root      319: void tlb_fill(CPUArchState *env1, target_ulong addr, int is_write, int mmu_idx,
        !           320:               uintptr_t retaddr);
1.1       root      321: 
1.1.1.7   root      322: #include "softmmu_defs.h"
                    323: 
1.1.1.6   root      324: #define ACCESS_TYPE (NB_MMU_MODES + 1)
1.1       root      325: #define MEMSUFFIX _code
1.1.1.15! root      326: #ifndef CONFIG_TCG_PASS_AREG0
1.1       root      327: #define env cpu_single_env
1.1.1.15! root      328: #endif
1.1       root      329: 
                    330: #define DATA_SIZE 1
                    331: #include "softmmu_header.h"
                    332: 
                    333: #define DATA_SIZE 2
                    334: #include "softmmu_header.h"
                    335: 
                    336: #define DATA_SIZE 4
                    337: #include "softmmu_header.h"
                    338: 
                    339: #define DATA_SIZE 8
                    340: #include "softmmu_header.h"
                    341: 
                    342: #undef ACCESS_TYPE
                    343: #undef MEMSUFFIX
                    344: #undef env
                    345: 
                    346: #endif
                    347: 
                    348: #if defined(CONFIG_USER_ONLY)
1.1.1.15! root      349: static inline tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
1.1       root      350: {
                    351:     return addr;
                    352: }
                    353: #else
1.1.1.15! root      354: /* cputlb.c */
        !           355: tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr);
1.1       root      356: #endif
                    357: 
1.1.1.15! root      358: typedef void (CPUDebugExcpHandler)(CPUArchState *env);
1.1.1.7   root      359: 
                    360: CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler);
1.1.1.8   root      361: 
                    362: /* vl.c */
                    363: extern int singlestep;
                    364: 
1.1.1.11  root      365: /* cpu-exec.c */
                    366: extern volatile sig_atomic_t exit_request;
                    367: 
1.1.1.14  root      368: /* Deterministic execution requires that IO only be performed on the last
                    369:    instruction of a TB so that interrupts take effect immediately.  */
1.1.1.15! root      370: static inline int can_do_io(CPUArchState *env)
1.1.1.14  root      371: {
                    372:     if (!use_icount) {
                    373:         return 1;
                    374:     }
                    375:     /* If not executing code then assume we are ok.  */
                    376:     if (!env->current_tb) {
                    377:         return 1;
                    378:     }
                    379:     return env->can_do_io != 0;
                    380: }
                    381: 
1.1.1.7   root      382: #endif

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