Annotation of qemu/exec.c, revision 1.1.1.12

1.1       root        1: /*
                      2:  *  virtual page mapping and translated block handling
1.1.1.6   root        3:  *
1.1       root        4:  *  Copyright (c) 2003 Fabrice Bellard
                      5:  *
                      6:  * This library is free software; you can redistribute it and/or
                      7:  * modify it under the terms of the GNU Lesser General Public
                      8:  * License as published by the Free Software Foundation; either
                      9:  * version 2 of the License, or (at your option) any later version.
                     10:  *
                     11:  * This library is distributed in the hope that it will be useful,
                     12:  * but WITHOUT ANY WARRANTY; without even the implied warranty of
                     13:  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
                     14:  * Lesser General Public License for more details.
                     15:  *
                     16:  * You should have received a copy of the GNU Lesser General Public
1.1.1.10  root       17:  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
1.1       root       18:  */
                     19: #include "config.h"
                     20: #ifdef _WIN32
                     21: #include <windows.h>
                     22: #else
                     23: #include <sys/types.h>
                     24: #include <sys/mman.h>
                     25: #endif
                     26: #include <stdlib.h>
                     27: #include <stdio.h>
                     28: #include <stdarg.h>
                     29: #include <string.h>
                     30: #include <errno.h>
                     31: #include <unistd.h>
                     32: #include <inttypes.h>
                     33: 
                     34: #include "cpu.h"
                     35: #include "exec-all.h"
1.1.1.7   root       36: #include "qemu-common.h"
                     37: #include "tcg.h"
                     38: #include "hw/hw.h"
                     39: #include "osdep.h"
                     40: #include "kvm.h"
1.1.1.3   root       41: #if defined(CONFIG_USER_ONLY)
                     42: #include <qemu.h>
                     43: #endif
1.1       root       44: 
                     45: //#define DEBUG_TB_INVALIDATE
                     46: //#define DEBUG_FLUSH
                     47: //#define DEBUG_TLB
1.1.1.5   root       48: //#define DEBUG_UNASSIGNED
1.1       root       49: 
                     50: /* make various TB consistency checks */
1.1.1.6   root       51: //#define DEBUG_TB_CHECK
                     52: //#define DEBUG_TLB_CHECK
                     53: 
                     54: //#define DEBUG_IOPORT
                     55: //#define DEBUG_SUBPAGE
1.1       root       56: 
1.1.1.3   root       57: #if !defined(CONFIG_USER_ONLY)
                     58: /* TB consistency checks only implemented for usermode emulation.  */
                     59: #undef DEBUG_TB_CHECK
                     60: #endif
                     61: 
1.1       root       62: #define SMC_BITMAP_USE_THRESHOLD 10
                     63: 
                     64: #if defined(TARGET_SPARC64)
                     65: #define TARGET_PHYS_ADDR_SPACE_BITS 41
1.1.1.6   root       66: #elif defined(TARGET_SPARC)
                     67: #define TARGET_PHYS_ADDR_SPACE_BITS 36
                     68: #elif defined(TARGET_ALPHA)
                     69: #define TARGET_PHYS_ADDR_SPACE_BITS 42
                     70: #define TARGET_VIRT_ADDR_SPACE_BITS 42
1.1       root       71: #elif defined(TARGET_PPC64)
                     72: #define TARGET_PHYS_ADDR_SPACE_BITS 42
1.1.1.11  root       73: #elif defined(TARGET_X86_64)
1.1.1.7   root       74: #define TARGET_PHYS_ADDR_SPACE_BITS 42
1.1.1.11  root       75: #elif defined(TARGET_I386)
1.1.1.7   root       76: #define TARGET_PHYS_ADDR_SPACE_BITS 36
1.1       root       77: #else
                     78: #define TARGET_PHYS_ADDR_SPACE_BITS 32
                     79: #endif
                     80: 
1.1.1.7   root       81: static TranslationBlock *tbs;
                     82: int code_gen_max_blocks;
1.1       root       83: TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
1.1.1.7   root       84: static int nb_tbs;
1.1       root       85: /* any access to the tbs or the page table must use this lock */
                     86: spinlock_t tb_lock = SPIN_LOCK_UNLOCKED;
                     87: 
1.1.1.7   root       88: #if defined(__arm__) || defined(__sparc_v9__)
                     89: /* The prologue must be reachable with a direct jump. ARM and Sparc64
                     90:  have limited branch ranges (possibly also PPC) so place it in a
                     91:  section close to code segment. */
                     92: #define code_gen_section                                \
                     93:     __attribute__((__section__(".gen_code")))           \
                     94:     __attribute__((aligned (32)))
1.1.1.10  root       95: #elif defined(_WIN32)
                     96: /* Maximum alignment for Win32 is 16. */
                     97: #define code_gen_section                                \
                     98:     __attribute__((aligned (16)))
1.1.1.7   root       99: #else
                    100: #define code_gen_section                                \
                    101:     __attribute__((aligned (32)))
                    102: #endif
                    103: 
                    104: uint8_t code_gen_prologue[1024] code_gen_section;
                    105: static uint8_t *code_gen_buffer;
                    106: static unsigned long code_gen_buffer_size;
                    107: /* threshold to flush the translated code buffer */
                    108: static unsigned long code_gen_buffer_max_size;
1.1       root      109: uint8_t *code_gen_ptr;
                    110: 
1.1.1.7   root      111: #if !defined(CONFIG_USER_ONLY)
1.1       root      112: int phys_ram_fd;
                    113: uint8_t *phys_ram_dirty;
1.1.1.7   root      114: static int in_migration;
1.1.1.10  root      115: 
                    116: typedef struct RAMBlock {
                    117:     uint8_t *host;
                    118:     ram_addr_t offset;
                    119:     ram_addr_t length;
                    120:     struct RAMBlock *next;
                    121: } RAMBlock;
                    122: 
                    123: static RAMBlock *ram_blocks;
                    124: /* TODO: When we implement (and use) ram deallocation (e.g. for hotplug)
                    125:    then we can no longer assume contiguous ram offsets, and external uses
                    126:    of this variable will break.  */
                    127: ram_addr_t last_ram_offset;
1.1.1.7   root      128: #endif
1.1       root      129: 
1.1.1.2   root      130: CPUState *first_cpu;
                    131: /* current CPU in the current thread. It is only valid inside
                    132:    cpu_exec() */
1.1.1.6   root      133: CPUState *cpu_single_env;
1.1.1.7   root      134: /* 0 = Do not count executed instructions.
                    135:    1 = Precise instruction counting.
                    136:    2 = Adaptive rate instruction counting.  */
                    137: int use_icount = 0;
                    138: /* Current instruction counter.  While executing translated code this may
                    139:    include some instructions that have not yet been executed.  */
                    140: int64_t qemu_icount;
1.1.1.2   root      141: 
1.1       root      142: typedef struct PageDesc {
                    143:     /* list of TBs intersecting this ram page */
                    144:     TranslationBlock *first_tb;
                    145:     /* in order to optimize self modifying code, we count the number
                    146:        of lookups we do to a given page to use a bitmap */
                    147:     unsigned int code_write_count;
                    148:     uint8_t *code_bitmap;
                    149: #if defined(CONFIG_USER_ONLY)
                    150:     unsigned long flags;
                    151: #endif
                    152: } PageDesc;
                    153: 
                    154: typedef struct PhysPageDesc {
1.1.1.7   root      155:     /* offset in host memory of the page + io_index in the low bits */
                    156:     ram_addr_t phys_offset;
                    157:     ram_addr_t region_offset;
1.1       root      158: } PhysPageDesc;
                    159: 
                    160: #define L2_BITS 10
1.1.1.6   root      161: #if defined(CONFIG_USER_ONLY) && defined(TARGET_VIRT_ADDR_SPACE_BITS)
                    162: /* XXX: this is a temporary hack for alpha target.
                    163:  *      In the future, this is to be replaced by a multi-level table
                    164:  *      to actually be able to handle the complete 64 bits address space.
                    165:  */
                    166: #define L1_BITS (TARGET_VIRT_ADDR_SPACE_BITS - L2_BITS - TARGET_PAGE_BITS)
                    167: #else
1.1       root      168: #define L1_BITS (32 - L2_BITS - TARGET_PAGE_BITS)
1.1.1.6   root      169: #endif
1.1       root      170: 
                    171: #define L1_SIZE (1 << L1_BITS)
                    172: #define L2_SIZE (1 << L2_BITS)
                    173: 
                    174: unsigned long qemu_real_host_page_size;
                    175: unsigned long qemu_host_page_bits;
                    176: unsigned long qemu_host_page_size;
                    177: unsigned long qemu_host_page_mask;
                    178: 
                    179: /* XXX: for system emulation, it could just be an array */
                    180: static PageDesc *l1_map[L1_SIZE];
1.1.1.7   root      181: static PhysPageDesc **l1_phys_map;
                    182: 
                    183: #if !defined(CONFIG_USER_ONLY)
                    184: static void io_mem_init(void);
1.1       root      185: 
                    186: /* io memory support */
                    187: CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
                    188: CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
                    189: void *io_mem_opaque[IO_MEM_NB_ENTRIES];
1.1.1.10  root      190: static char io_mem_used[IO_MEM_NB_ENTRIES];
1.1.1.6   root      191: static int io_mem_watch;
                    192: #endif
1.1       root      193: 
                    194: /* log support */
1.1.1.7   root      195: static const char *logfilename = "/tmp/qemu.log";
1.1       root      196: FILE *logfile;
                    197: int loglevel;
1.1.1.6   root      198: static int log_append = 0;
1.1       root      199: 
                    200: /* statistics */
                    201: static int tlb_flush_count;
                    202: static int tb_flush_count;
                    203: static int tb_phys_invalidate_count;
                    204: 
1.1.1.6   root      205: #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
                    206: typedef struct subpage_t {
                    207:     target_phys_addr_t base;
1.1.1.11  root      208:     CPUReadMemoryFunc * const *mem_read[TARGET_PAGE_SIZE][4];
                    209:     CPUWriteMemoryFunc * const *mem_write[TARGET_PAGE_SIZE][4];
1.1.1.6   root      210:     void *opaque[TARGET_PAGE_SIZE][2][4];
1.1.1.7   root      211:     ram_addr_t region_offset[TARGET_PAGE_SIZE][2][4];
1.1.1.6   root      212: } subpage_t;
                    213: 
1.1.1.7   root      214: #ifdef _WIN32
                    215: static void map_exec(void *addr, long size)
                    216: {
                    217:     DWORD old_protect;
                    218:     VirtualProtect(addr, size,
                    219:                    PAGE_EXECUTE_READWRITE, &old_protect);
                    220:     
                    221: }
                    222: #else
                    223: static void map_exec(void *addr, long size)
                    224: {
                    225:     unsigned long start, end, page_size;
                    226:     
                    227:     page_size = getpagesize();
                    228:     start = (unsigned long)addr;
                    229:     start &= ~(page_size - 1);
                    230:     
                    231:     end = (unsigned long)addr + size;
                    232:     end += page_size - 1;
                    233:     end &= ~(page_size - 1);
                    234:     
                    235:     mprotect((void *)start, end - start,
                    236:              PROT_READ | PROT_WRITE | PROT_EXEC);
                    237: }
                    238: #endif
                    239: 
1.1       root      240: static void page_init(void)
                    241: {
                    242:     /* NOTE: we can always suppose that qemu_host_page_size >=
                    243:        TARGET_PAGE_SIZE */
                    244: #ifdef _WIN32
                    245:     {
                    246:         SYSTEM_INFO system_info;
1.1.1.6   root      247: 
1.1       root      248:         GetSystemInfo(&system_info);
                    249:         qemu_real_host_page_size = system_info.dwPageSize;
                    250:     }
                    251: #else
                    252:     qemu_real_host_page_size = getpagesize();
                    253: #endif
                    254:     if (qemu_host_page_size == 0)
                    255:         qemu_host_page_size = qemu_real_host_page_size;
                    256:     if (qemu_host_page_size < TARGET_PAGE_SIZE)
                    257:         qemu_host_page_size = TARGET_PAGE_SIZE;
                    258:     qemu_host_page_bits = 0;
                    259:     while ((1 << qemu_host_page_bits) < qemu_host_page_size)
                    260:         qemu_host_page_bits++;
                    261:     qemu_host_page_mask = ~(qemu_host_page_size - 1);
                    262:     l1_phys_map = qemu_vmalloc(L1_SIZE * sizeof(void *));
                    263:     memset(l1_phys_map, 0, L1_SIZE * sizeof(void *));
1.1.1.6   root      264: 
                    265: #if !defined(_WIN32) && defined(CONFIG_USER_ONLY)
                    266:     {
                    267:         long long startaddr, endaddr;
                    268:         FILE *f;
                    269:         int n;
                    270: 
1.1.1.7   root      271:         mmap_lock();
                    272:         last_brk = (unsigned long)sbrk(0);
1.1.1.6   root      273:         f = fopen("/proc/self/maps", "r");
                    274:         if (f) {
                    275:             do {
                    276:                 n = fscanf (f, "%llx-%llx %*[^\n]\n", &startaddr, &endaddr);
                    277:                 if (n == 2) {
1.1.1.7   root      278:                     startaddr = MIN(startaddr,
                    279:                                     (1ULL << TARGET_PHYS_ADDR_SPACE_BITS) - 1);
                    280:                     endaddr = MIN(endaddr,
                    281:                                     (1ULL << TARGET_PHYS_ADDR_SPACE_BITS) - 1);
                    282:                     page_set_flags(startaddr & TARGET_PAGE_MASK,
1.1.1.6   root      283:                                    TARGET_PAGE_ALIGN(endaddr),
                    284:                                    PAGE_RESERVED); 
                    285:                 }
                    286:             } while (!feof(f));
                    287:             fclose(f);
                    288:         }
1.1.1.7   root      289:         mmap_unlock();
1.1.1.6   root      290:     }
                    291: #endif
1.1       root      292: }
                    293: 
1.1.1.7   root      294: static inline PageDesc **page_l1_map(target_ulong index)
                    295: {
                    296: #if TARGET_LONG_BITS > 32
                    297:     /* Host memory outside guest VM.  For 32-bit targets we have already
                    298:        excluded high addresses.  */
                    299:     if (index > ((target_ulong)L2_SIZE * L1_SIZE))
                    300:         return NULL;
                    301: #endif
                    302:     return &l1_map[index >> L2_BITS];
                    303: }
                    304: 
                    305: static inline PageDesc *page_find_alloc(target_ulong index)
1.1       root      306: {
                    307:     PageDesc **lp, *p;
1.1.1.7   root      308:     lp = page_l1_map(index);
                    309:     if (!lp)
                    310:         return NULL;
1.1       root      311: 
                    312:     p = *lp;
                    313:     if (!p) {
                    314:         /* allocate if not found */
1.1.1.7   root      315: #if defined(CONFIG_USER_ONLY)
                    316:         size_t len = sizeof(PageDesc) * L2_SIZE;
                    317:         /* Don't use qemu_malloc because it may recurse.  */
1.1.1.10  root      318:         p = mmap(NULL, len, PROT_READ | PROT_WRITE,
1.1.1.7   root      319:                  MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
1.1       root      320:         *lp = p;
1.1.1.7   root      321:         if (h2g_valid(p)) {
                    322:             unsigned long addr = h2g(p);
                    323:             page_set_flags(addr & TARGET_PAGE_MASK,
                    324:                            TARGET_PAGE_ALIGN(addr + len),
                    325:                            PAGE_RESERVED); 
                    326:         }
                    327: #else
                    328:         p = qemu_mallocz(sizeof(PageDesc) * L2_SIZE);
                    329:         *lp = p;
                    330: #endif
1.1       root      331:     }
                    332:     return p + (index & (L2_SIZE - 1));
                    333: }
                    334: 
1.1.1.7   root      335: static inline PageDesc *page_find(target_ulong index)
1.1       root      336: {
1.1.1.7   root      337:     PageDesc **lp, *p;
                    338:     lp = page_l1_map(index);
                    339:     if (!lp)
                    340:         return NULL;
1.1       root      341: 
1.1.1.7   root      342:     p = *lp;
1.1.1.10  root      343:     if (!p) {
                    344:         return NULL;
                    345:     }
1.1       root      346:     return p + (index & (L2_SIZE - 1));
                    347: }
                    348: 
                    349: static PhysPageDesc *phys_page_find_alloc(target_phys_addr_t index, int alloc)
                    350: {
                    351:     void **lp, **p;
1.1.1.3   root      352:     PhysPageDesc *pd;
1.1       root      353: 
                    354:     p = (void **)l1_phys_map;
                    355: #if TARGET_PHYS_ADDR_SPACE_BITS > 32
                    356: 
                    357: #if TARGET_PHYS_ADDR_SPACE_BITS > (32 + L1_BITS)
                    358: #error unsupported TARGET_PHYS_ADDR_SPACE_BITS
                    359: #endif
                    360:     lp = p + ((index >> (L1_BITS + L2_BITS)) & (L1_SIZE - 1));
                    361:     p = *lp;
                    362:     if (!p) {
                    363:         /* allocate if not found */
                    364:         if (!alloc)
                    365:             return NULL;
                    366:         p = qemu_vmalloc(sizeof(void *) * L1_SIZE);
                    367:         memset(p, 0, sizeof(void *) * L1_SIZE);
                    368:         *lp = p;
                    369:     }
                    370: #endif
                    371:     lp = p + ((index >> L2_BITS) & (L1_SIZE - 1));
1.1.1.3   root      372:     pd = *lp;
                    373:     if (!pd) {
                    374:         int i;
1.1       root      375:         /* allocate if not found */
                    376:         if (!alloc)
                    377:             return NULL;
1.1.1.3   root      378:         pd = qemu_vmalloc(sizeof(PhysPageDesc) * L2_SIZE);
                    379:         *lp = pd;
1.1.1.7   root      380:         for (i = 0; i < L2_SIZE; i++) {
1.1.1.3   root      381:           pd[i].phys_offset = IO_MEM_UNASSIGNED;
1.1.1.7   root      382:           pd[i].region_offset = (index + i) << TARGET_PAGE_BITS;
                    383:         }
1.1       root      384:     }
1.1.1.3   root      385:     return ((PhysPageDesc *)pd) + (index & (L2_SIZE - 1));
1.1       root      386: }
                    387: 
                    388: static inline PhysPageDesc *phys_page_find(target_phys_addr_t index)
                    389: {
                    390:     return phys_page_find_alloc(index, 0);
                    391: }
                    392: 
                    393: #if !defined(CONFIG_USER_ONLY)
1.1.1.2   root      394: static void tlb_protect_code(ram_addr_t ram_addr);
1.1.1.6   root      395: static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr,
1.1       root      396:                                     target_ulong vaddr);
1.1.1.7   root      397: #define mmap_lock() do { } while(0)
                    398: #define mmap_unlock() do { } while(0)
                    399: #endif
                    400: 
                    401: #define DEFAULT_CODE_GEN_BUFFER_SIZE (32 * 1024 * 1024)
                    402: 
                    403: #if defined(CONFIG_USER_ONLY)
1.1.1.10  root      404: /* Currently it is not recommended to allocate big chunks of data in
1.1.1.7   root      405:    user mode. It will change when a dedicated libc will be used */
                    406: #define USE_STATIC_CODE_GEN_BUFFER
                    407: #endif
                    408: 
                    409: #ifdef USE_STATIC_CODE_GEN_BUFFER
                    410: static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE];
                    411: #endif
                    412: 
                    413: static void code_gen_alloc(unsigned long tb_size)
                    414: {
                    415: #ifdef USE_STATIC_CODE_GEN_BUFFER
                    416:     code_gen_buffer = static_code_gen_buffer;
                    417:     code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE;
                    418:     map_exec(code_gen_buffer, code_gen_buffer_size);
                    419: #else
                    420:     code_gen_buffer_size = tb_size;
                    421:     if (code_gen_buffer_size == 0) {
                    422: #if defined(CONFIG_USER_ONLY)
                    423:         /* in user mode, phys_ram_size is not meaningful */
                    424:         code_gen_buffer_size = DEFAULT_CODE_GEN_BUFFER_SIZE;
                    425: #else
1.1.1.10  root      426:         /* XXX: needs adjustments */
                    427:         code_gen_buffer_size = (unsigned long)(ram_size / 4);
1.1.1.7   root      428: #endif
                    429:     }
                    430:     if (code_gen_buffer_size < MIN_CODE_GEN_BUFFER_SIZE)
                    431:         code_gen_buffer_size = MIN_CODE_GEN_BUFFER_SIZE;
                    432:     /* The code gen buffer location may have constraints depending on
                    433:        the host cpu and OS */
                    434: #if defined(__linux__) 
                    435:     {
                    436:         int flags;
                    437:         void *start = NULL;
                    438: 
                    439:         flags = MAP_PRIVATE | MAP_ANONYMOUS;
                    440: #if defined(__x86_64__)
                    441:         flags |= MAP_32BIT;
                    442:         /* Cannot map more than that */
                    443:         if (code_gen_buffer_size > (800 * 1024 * 1024))
                    444:             code_gen_buffer_size = (800 * 1024 * 1024);
                    445: #elif defined(__sparc_v9__)
                    446:         // Map the buffer below 2G, so we can use direct calls and branches
                    447:         flags |= MAP_FIXED;
                    448:         start = (void *) 0x60000000UL;
                    449:         if (code_gen_buffer_size > (512 * 1024 * 1024))
                    450:             code_gen_buffer_size = (512 * 1024 * 1024);
                    451: #elif defined(__arm__)
                    452:         /* Map the buffer below 32M, so we can use direct calls and branches */
                    453:         flags |= MAP_FIXED;
                    454:         start = (void *) 0x01000000UL;
                    455:         if (code_gen_buffer_size > 16 * 1024 * 1024)
                    456:             code_gen_buffer_size = 16 * 1024 * 1024;
                    457: #endif
                    458:         code_gen_buffer = mmap(start, code_gen_buffer_size,
                    459:                                PROT_WRITE | PROT_READ | PROT_EXEC,
                    460:                                flags, -1, 0);
                    461:         if (code_gen_buffer == MAP_FAILED) {
                    462:             fprintf(stderr, "Could not allocate dynamic translator buffer\n");
                    463:             exit(1);
                    464:         }
                    465:     }
1.1.1.11  root      466: #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__)
1.1.1.7   root      467:     {
                    468:         int flags;
                    469:         void *addr = NULL;
                    470:         flags = MAP_PRIVATE | MAP_ANONYMOUS;
                    471: #if defined(__x86_64__)
                    472:         /* FreeBSD doesn't have MAP_32BIT, use MAP_FIXED and assume
                    473:          * 0x40000000 is free */
                    474:         flags |= MAP_FIXED;
                    475:         addr = (void *)0x40000000;
                    476:         /* Cannot map more than that */
                    477:         if (code_gen_buffer_size > (800 * 1024 * 1024))
                    478:             code_gen_buffer_size = (800 * 1024 * 1024);
                    479: #endif
                    480:         code_gen_buffer = mmap(addr, code_gen_buffer_size,
                    481:                                PROT_WRITE | PROT_READ | PROT_EXEC, 
                    482:                                flags, -1, 0);
                    483:         if (code_gen_buffer == MAP_FAILED) {
                    484:             fprintf(stderr, "Could not allocate dynamic translator buffer\n");
                    485:             exit(1);
                    486:         }
                    487:     }
                    488: #else
                    489:     code_gen_buffer = qemu_malloc(code_gen_buffer_size);
                    490:     map_exec(code_gen_buffer, code_gen_buffer_size);
                    491: #endif
                    492: #endif /* !USE_STATIC_CODE_GEN_BUFFER */
                    493:     map_exec(code_gen_prologue, sizeof(code_gen_prologue));
                    494:     code_gen_buffer_max_size = code_gen_buffer_size - 
                    495:         code_gen_max_block_size();
                    496:     code_gen_max_blocks = code_gen_buffer_size / CODE_GEN_AVG_BLOCK_SIZE;
                    497:     tbs = qemu_malloc(code_gen_max_blocks * sizeof(TranslationBlock));
                    498: }
                    499: 
                    500: /* Must be called before using the QEMU cpus. 'tb_size' is the size
                    501:    (in bytes) allocated to the translation buffer. Zero means default
                    502:    size. */
                    503: void cpu_exec_init_all(unsigned long tb_size)
                    504: {
                    505:     cpu_gen_init();
                    506:     code_gen_alloc(tb_size);
                    507:     code_gen_ptr = code_gen_buffer;
                    508:     page_init();
                    509: #if !defined(CONFIG_USER_ONLY)
                    510:     io_mem_init();
                    511: #endif
                    512: }
                    513: 
                    514: #if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
                    515: 
1.1.1.11  root      516: static void cpu_common_pre_save(void *opaque)
1.1.1.7   root      517: {
                    518:     CPUState *env = opaque;
                    519: 
1.1.1.11  root      520:     cpu_synchronize_state(env);
1.1.1.7   root      521: }
                    522: 
1.1.1.11  root      523: static int cpu_common_pre_load(void *opaque)
1.1.1.7   root      524: {
                    525:     CPUState *env = opaque;
                    526: 
1.1.1.11  root      527:     cpu_synchronize_state(env);
                    528:     return 0;
                    529: }
                    530: 
                    531: static int cpu_common_post_load(void *opaque, int version_id)
                    532: {
                    533:     CPUState *env = opaque;
1.1.1.7   root      534: 
1.1.1.10  root      535:     /* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
                    536:        version_id is increased. */
                    537:     env->interrupt_request &= ~0x01;
1.1.1.7   root      538:     tlb_flush(env, 1);
                    539: 
                    540:     return 0;
                    541: }
1.1.1.11  root      542: 
                    543: static const VMStateDescription vmstate_cpu_common = {
                    544:     .name = "cpu_common",
                    545:     .version_id = 1,
                    546:     .minimum_version_id = 1,
                    547:     .minimum_version_id_old = 1,
                    548:     .pre_save = cpu_common_pre_save,
                    549:     .pre_load = cpu_common_pre_load,
                    550:     .post_load = cpu_common_post_load,
                    551:     .fields      = (VMStateField []) {
                    552:         VMSTATE_UINT32(halted, CPUState),
                    553:         VMSTATE_UINT32(interrupt_request, CPUState),
                    554:         VMSTATE_END_OF_LIST()
                    555:     }
                    556: };
1.1       root      557: #endif
                    558: 
1.1.1.10  root      559: CPUState *qemu_get_cpu(int cpu)
                    560: {
                    561:     CPUState *env = first_cpu;
                    562: 
                    563:     while (env) {
                    564:         if (env->cpu_index == cpu)
                    565:             break;
                    566:         env = env->next_cpu;
                    567:     }
                    568: 
                    569:     return env;
                    570: }
                    571: 
1.1.1.2   root      572: void cpu_exec_init(CPUState *env)
1.1       root      573: {
1.1.1.2   root      574:     CPUState **penv;
                    575:     int cpu_index;
1.1       root      576: 
1.1.1.10  root      577: #if defined(CONFIG_USER_ONLY)
                    578:     cpu_list_lock();
                    579: #endif
1.1.1.2   root      580:     env->next_cpu = NULL;
                    581:     penv = &first_cpu;
                    582:     cpu_index = 0;
                    583:     while (*penv != NULL) {
1.1.1.10  root      584:         penv = &(*penv)->next_cpu;
1.1.1.2   root      585:         cpu_index++;
                    586:     }
                    587:     env->cpu_index = cpu_index;
1.1.1.10  root      588:     env->numa_node = 0;
1.1.1.11  root      589:     QTAILQ_INIT(&env->breakpoints);
                    590:     QTAILQ_INIT(&env->watchpoints);
1.1.1.2   root      591:     *penv = env;
1.1.1.10  root      592: #if defined(CONFIG_USER_ONLY)
                    593:     cpu_list_unlock();
                    594: #endif
1.1.1.7   root      595: #if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
1.1.1.11  root      596:     vmstate_register(cpu_index, &vmstate_cpu_common, env);
1.1.1.7   root      597:     register_savevm("cpu", cpu_index, CPU_SAVE_VERSION,
                    598:                     cpu_save, cpu_load, env);
                    599: #endif
1.1       root      600: }
                    601: 
                    602: static inline void invalidate_page_bitmap(PageDesc *p)
                    603: {
                    604:     if (p->code_bitmap) {
                    605:         qemu_free(p->code_bitmap);
                    606:         p->code_bitmap = NULL;
                    607:     }
                    608:     p->code_write_count = 0;
                    609: }
                    610: 
                    611: /* set to NULL all the 'first_tb' fields in all PageDescs */
                    612: static void page_flush_tb(void)
                    613: {
                    614:     int i, j;
                    615:     PageDesc *p;
                    616: 
                    617:     for(i = 0; i < L1_SIZE; i++) {
                    618:         p = l1_map[i];
                    619:         if (p) {
                    620:             for(j = 0; j < L2_SIZE; j++) {
                    621:                 p->first_tb = NULL;
                    622:                 invalidate_page_bitmap(p);
                    623:                 p++;
                    624:             }
                    625:         }
                    626:     }
                    627: }
                    628: 
                    629: /* flush all the translation blocks */
                    630: /* XXX: tb_flush is currently not thread safe */
1.1.1.2   root      631: void tb_flush(CPUState *env1)
1.1       root      632: {
1.1.1.2   root      633:     CPUState *env;
1.1       root      634: #if defined(DEBUG_FLUSH)
1.1.1.6   root      635:     printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n",
                    636:            (unsigned long)(code_gen_ptr - code_gen_buffer),
                    637:            nb_tbs, nb_tbs > 0 ?
                    638:            ((unsigned long)(code_gen_ptr - code_gen_buffer)) / nb_tbs : 0);
1.1       root      639: #endif
1.1.1.7   root      640:     if ((unsigned long)(code_gen_ptr - code_gen_buffer) > code_gen_buffer_size)
                    641:         cpu_abort(env1, "Internal error: code buffer overflow\n");
                    642: 
1.1       root      643:     nb_tbs = 0;
1.1.1.6   root      644: 
1.1.1.2   root      645:     for(env = first_cpu; env != NULL; env = env->next_cpu) {
                    646:         memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *));
                    647:     }
1.1       root      648: 
                    649:     memset (tb_phys_hash, 0, CODE_GEN_PHYS_HASH_SIZE * sizeof (void *));
                    650:     page_flush_tb();
                    651: 
                    652:     code_gen_ptr = code_gen_buffer;
                    653:     /* XXX: flush processor icache at this point if cache flush is
                    654:        expensive */
                    655:     tb_flush_count++;
                    656: }
                    657: 
                    658: #ifdef DEBUG_TB_CHECK
                    659: 
1.1.1.6   root      660: static void tb_invalidate_check(target_ulong address)
1.1       root      661: {
                    662:     TranslationBlock *tb;
                    663:     int i;
                    664:     address &= TARGET_PAGE_MASK;
1.1.1.3   root      665:     for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) {
                    666:         for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) {
1.1       root      667:             if (!(address + TARGET_PAGE_SIZE <= tb->pc ||
                    668:                   address >= tb->pc + tb->size)) {
1.1.1.10  root      669:                 printf("ERROR invalidate: address=" TARGET_FMT_lx
                    670:                        " PC=%08lx size=%04x\n",
1.1.1.3   root      671:                        address, (long)tb->pc, tb->size);
1.1       root      672:             }
                    673:         }
                    674:     }
                    675: }
                    676: 
                    677: /* verify that all the pages have correct rights for code */
                    678: static void tb_page_check(void)
                    679: {
                    680:     TranslationBlock *tb;
                    681:     int i, flags1, flags2;
1.1.1.6   root      682: 
1.1.1.3   root      683:     for(i = 0;i < CODE_GEN_PHYS_HASH_SIZE; i++) {
                    684:         for(tb = tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) {
1.1       root      685:             flags1 = page_get_flags(tb->pc);
                    686:             flags2 = page_get_flags(tb->pc + tb->size - 1);
                    687:             if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) {
                    688:                 printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n",
1.1.1.3   root      689:                        (long)tb->pc, tb->size, flags1, flags2);
1.1       root      690:             }
                    691:         }
                    692:     }
                    693: }
                    694: 
                    695: #endif
                    696: 
                    697: /* invalidate one TB */
                    698: static inline void tb_remove(TranslationBlock **ptb, TranslationBlock *tb,
                    699:                              int next_offset)
                    700: {
                    701:     TranslationBlock *tb1;
                    702:     for(;;) {
                    703:         tb1 = *ptb;
                    704:         if (tb1 == tb) {
                    705:             *ptb = *(TranslationBlock **)((char *)tb1 + next_offset);
                    706:             break;
                    707:         }
                    708:         ptb = (TranslationBlock **)((char *)tb1 + next_offset);
                    709:     }
                    710: }
                    711: 
                    712: static inline void tb_page_remove(TranslationBlock **ptb, TranslationBlock *tb)
                    713: {
                    714:     TranslationBlock *tb1;
                    715:     unsigned int n1;
                    716: 
                    717:     for(;;) {
                    718:         tb1 = *ptb;
                    719:         n1 = (long)tb1 & 3;
                    720:         tb1 = (TranslationBlock *)((long)tb1 & ~3);
                    721:         if (tb1 == tb) {
                    722:             *ptb = tb1->page_next[n1];
                    723:             break;
                    724:         }
                    725:         ptb = &tb1->page_next[n1];
                    726:     }
                    727: }
                    728: 
                    729: static inline void tb_jmp_remove(TranslationBlock *tb, int n)
                    730: {
                    731:     TranslationBlock *tb1, **ptb;
                    732:     unsigned int n1;
                    733: 
                    734:     ptb = &tb->jmp_next[n];
                    735:     tb1 = *ptb;
                    736:     if (tb1) {
                    737:         /* find tb(n) in circular list */
                    738:         for(;;) {
                    739:             tb1 = *ptb;
                    740:             n1 = (long)tb1 & 3;
                    741:             tb1 = (TranslationBlock *)((long)tb1 & ~3);
                    742:             if (n1 == n && tb1 == tb)
                    743:                 break;
                    744:             if (n1 == 2) {
                    745:                 ptb = &tb1->jmp_first;
                    746:             } else {
                    747:                 ptb = &tb1->jmp_next[n1];
                    748:             }
                    749:         }
                    750:         /* now we can suppress tb(n) from the list */
                    751:         *ptb = tb->jmp_next[n];
                    752: 
                    753:         tb->jmp_next[n] = NULL;
                    754:     }
                    755: }
                    756: 
                    757: /* reset the jump entry 'n' of a TB so that it is not chained to
                    758:    another TB */
                    759: static inline void tb_reset_jump(TranslationBlock *tb, int n)
                    760: {
                    761:     tb_set_jmp_target(tb, n, (unsigned long)(tb->tc_ptr + tb->tb_next_offset[n]));
                    762: }
                    763: 
1.1.1.7   root      764: void tb_phys_invalidate(TranslationBlock *tb, target_ulong page_addr)
1.1       root      765: {
1.1.1.2   root      766:     CPUState *env;
                    767:     PageDesc *p;
1.1       root      768:     unsigned int h, n1;
1.1.1.7   root      769:     target_phys_addr_t phys_pc;
1.1.1.2   root      770:     TranslationBlock *tb1, *tb2;
1.1.1.6   root      771: 
1.1.1.2   root      772:     /* remove the TB from the hash list */
                    773:     phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
                    774:     h = tb_phys_hash_func(phys_pc);
1.1.1.6   root      775:     tb_remove(&tb_phys_hash[h], tb,
1.1.1.2   root      776:               offsetof(TranslationBlock, phys_hash_next));
                    777: 
                    778:     /* remove the TB from the page list */
                    779:     if (tb->page_addr[0] != page_addr) {
                    780:         p = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS);
                    781:         tb_page_remove(&p->first_tb, tb);
                    782:         invalidate_page_bitmap(p);
                    783:     }
                    784:     if (tb->page_addr[1] != -1 && tb->page_addr[1] != page_addr) {
                    785:         p = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS);
                    786:         tb_page_remove(&p->first_tb, tb);
                    787:         invalidate_page_bitmap(p);
                    788:     }
                    789: 
1.1       root      790:     tb_invalidated_flag = 1;
                    791: 
                    792:     /* remove the TB from the hash list */
1.1.1.2   root      793:     h = tb_jmp_cache_hash_func(tb->pc);
                    794:     for(env = first_cpu; env != NULL; env = env->next_cpu) {
                    795:         if (env->tb_jmp_cache[h] == tb)
                    796:             env->tb_jmp_cache[h] = NULL;
1.1       root      797:     }
                    798: 
                    799:     /* suppress this TB from the two jump lists */
                    800:     tb_jmp_remove(tb, 0);
                    801:     tb_jmp_remove(tb, 1);
                    802: 
                    803:     /* suppress any remaining jumps to this TB */
                    804:     tb1 = tb->jmp_first;
                    805:     for(;;) {
                    806:         n1 = (long)tb1 & 3;
                    807:         if (n1 == 2)
                    808:             break;
                    809:         tb1 = (TranslationBlock *)((long)tb1 & ~3);
                    810:         tb2 = tb1->jmp_next[n1];
                    811:         tb_reset_jump(tb1, n1);
                    812:         tb1->jmp_next[n1] = NULL;
                    813:         tb1 = tb2;
                    814:     }
                    815:     tb->jmp_first = (TranslationBlock *)((long)tb | 2); /* fail safe */
                    816: 
                    817:     tb_phys_invalidate_count++;
                    818: }
                    819: 
                    820: static inline void set_bits(uint8_t *tab, int start, int len)
                    821: {
                    822:     int end, mask, end1;
                    823: 
                    824:     end = start + len;
                    825:     tab += start >> 3;
                    826:     mask = 0xff << (start & 7);
                    827:     if ((start & ~7) == (end & ~7)) {
                    828:         if (start < end) {
                    829:             mask &= ~(0xff << (end & 7));
                    830:             *tab |= mask;
                    831:         }
                    832:     } else {
                    833:         *tab++ |= mask;
                    834:         start = (start + 8) & ~7;
                    835:         end1 = end & ~7;
                    836:         while (start < end1) {
                    837:             *tab++ = 0xff;
                    838:             start += 8;
                    839:         }
                    840:         if (start < end) {
                    841:             mask = ~(0xff << (end & 7));
                    842:             *tab |= mask;
                    843:         }
                    844:     }
                    845: }
                    846: 
                    847: static void build_page_bitmap(PageDesc *p)
                    848: {
                    849:     int n, tb_start, tb_end;
                    850:     TranslationBlock *tb;
1.1.1.6   root      851: 
1.1.1.7   root      852:     p->code_bitmap = qemu_mallocz(TARGET_PAGE_SIZE / 8);
1.1       root      853: 
                    854:     tb = p->first_tb;
                    855:     while (tb != NULL) {
                    856:         n = (long)tb & 3;
                    857:         tb = (TranslationBlock *)((long)tb & ~3);
                    858:         /* NOTE: this is subtle as a TB may span two physical pages */
                    859:         if (n == 0) {
                    860:             /* NOTE: tb_end may be after the end of the page, but
                    861:                it is not a problem */
                    862:             tb_start = tb->pc & ~TARGET_PAGE_MASK;
                    863:             tb_end = tb_start + tb->size;
                    864:             if (tb_end > TARGET_PAGE_SIZE)
                    865:                 tb_end = TARGET_PAGE_SIZE;
                    866:         } else {
                    867:             tb_start = 0;
                    868:             tb_end = ((tb->pc + tb->size) & ~TARGET_PAGE_MASK);
                    869:         }
                    870:         set_bits(p->code_bitmap, tb_start, tb_end - tb_start);
                    871:         tb = tb->page_next[n];
                    872:     }
                    873: }
                    874: 
1.1.1.7   root      875: TranslationBlock *tb_gen_code(CPUState *env,
                    876:                               target_ulong pc, target_ulong cs_base,
                    877:                               int flags, int cflags)
1.1       root      878: {
                    879:     TranslationBlock *tb;
                    880:     uint8_t *tc_ptr;
                    881:     target_ulong phys_pc, phys_page2, virt_page2;
                    882:     int code_gen_size;
                    883: 
                    884:     phys_pc = get_phys_addr_code(env, pc);
                    885:     tb = tb_alloc(pc);
                    886:     if (!tb) {
                    887:         /* flush must be done */
                    888:         tb_flush(env);
                    889:         /* cannot fail at this point */
                    890:         tb = tb_alloc(pc);
1.1.1.7   root      891:         /* Don't forget to invalidate previous TB info.  */
                    892:         tb_invalidated_flag = 1;
1.1       root      893:     }
                    894:     tc_ptr = code_gen_ptr;
                    895:     tb->tc_ptr = tc_ptr;
                    896:     tb->cs_base = cs_base;
                    897:     tb->flags = flags;
                    898:     tb->cflags = cflags;
1.1.1.6   root      899:     cpu_gen_code(env, tb, &code_gen_size);
1.1       root      900:     code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
1.1.1.6   root      901: 
1.1       root      902:     /* check next page if needed */
                    903:     virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
                    904:     phys_page2 = -1;
                    905:     if ((pc & TARGET_PAGE_MASK) != virt_page2) {
                    906:         phys_page2 = get_phys_addr_code(env, virt_page2);
                    907:     }
                    908:     tb_link_phys(tb, phys_pc, phys_page2);
1.1.1.7   root      909:     return tb;
1.1       root      910: }
1.1.1.6   root      911: 
1.1       root      912: /* invalidate all TBs which intersect with the target physical page
                    913:    starting in range [start;end[. NOTE: start and end must refer to
                    914:    the same physical page. 'is_cpu_write_access' should be true if called
                    915:    from a real cpu write access: the virtual CPU will exit the current
                    916:    TB if code is modified inside this TB. */
1.1.1.7   root      917: void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
1.1       root      918:                                    int is_cpu_write_access)
                    919: {
1.1.1.7   root      920:     TranslationBlock *tb, *tb_next, *saved_tb;
1.1       root      921:     CPUState *env = cpu_single_env;
                    922:     target_ulong tb_start, tb_end;
1.1.1.7   root      923:     PageDesc *p;
                    924:     int n;
                    925: #ifdef TARGET_HAS_PRECISE_SMC
                    926:     int current_tb_not_found = is_cpu_write_access;
                    927:     TranslationBlock *current_tb = NULL;
                    928:     int current_tb_modified = 0;
                    929:     target_ulong current_pc = 0;
                    930:     target_ulong current_cs_base = 0;
                    931:     int current_flags = 0;
                    932: #endif /* TARGET_HAS_PRECISE_SMC */
1.1       root      933: 
                    934:     p = page_find(start >> TARGET_PAGE_BITS);
1.1.1.6   root      935:     if (!p)
1.1       root      936:         return;
1.1.1.6   root      937:     if (!p->code_bitmap &&
1.1       root      938:         ++p->code_write_count >= SMC_BITMAP_USE_THRESHOLD &&
                    939:         is_cpu_write_access) {
                    940:         /* build code bitmap */
                    941:         build_page_bitmap(p);
                    942:     }
                    943: 
                    944:     /* we remove all the TBs in the range [start, end[ */
                    945:     /* XXX: see if in some cases it could be faster to invalidate all the code */
                    946:     tb = p->first_tb;
                    947:     while (tb != NULL) {
                    948:         n = (long)tb & 3;
                    949:         tb = (TranslationBlock *)((long)tb & ~3);
                    950:         tb_next = tb->page_next[n];
                    951:         /* NOTE: this is subtle as a TB may span two physical pages */
                    952:         if (n == 0) {
                    953:             /* NOTE: tb_end may be after the end of the page, but
                    954:                it is not a problem */
                    955:             tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
                    956:             tb_end = tb_start + tb->size;
                    957:         } else {
                    958:             tb_start = tb->page_addr[1];
                    959:             tb_end = tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK);
                    960:         }
                    961:         if (!(tb_end <= start || tb_start >= end)) {
                    962: #ifdef TARGET_HAS_PRECISE_SMC
                    963:             if (current_tb_not_found) {
                    964:                 current_tb_not_found = 0;
                    965:                 current_tb = NULL;
1.1.1.7   root      966:                 if (env->mem_io_pc) {
1.1       root      967:                     /* now we have a real cpu fault */
1.1.1.7   root      968:                     current_tb = tb_find_pc(env->mem_io_pc);
1.1       root      969:                 }
                    970:             }
                    971:             if (current_tb == tb &&
1.1.1.7   root      972:                 (current_tb->cflags & CF_COUNT_MASK) != 1) {
1.1       root      973:                 /* If we are modifying the current TB, we must stop
                    974:                 its execution. We could be more precise by checking
                    975:                 that the modification is after the current PC, but it
                    976:                 would require a specialized function to partially
                    977:                 restore the CPU state */
1.1.1.6   root      978: 
1.1       root      979:                 current_tb_modified = 1;
1.1.1.6   root      980:                 cpu_restore_state(current_tb, env,
1.1.1.7   root      981:                                   env->mem_io_pc, NULL);
                    982:                 cpu_get_tb_cpu_state(env, &current_pc, &current_cs_base,
                    983:                                      &current_flags);
1.1       root      984:             }
                    985: #endif /* TARGET_HAS_PRECISE_SMC */
1.1.1.2   root      986:             /* we need to do that to handle the case where a signal
                    987:                occurs while doing tb_phys_invalidate() */
                    988:             saved_tb = NULL;
                    989:             if (env) {
                    990:                 saved_tb = env->current_tb;
                    991:                 env->current_tb = NULL;
                    992:             }
1.1       root      993:             tb_phys_invalidate(tb, -1);
1.1.1.2   root      994:             if (env) {
                    995:                 env->current_tb = saved_tb;
                    996:                 if (env->interrupt_request && env->current_tb)
                    997:                     cpu_interrupt(env, env->interrupt_request);
                    998:             }
1.1       root      999:         }
                   1000:         tb = tb_next;
                   1001:     }
                   1002: #if !defined(CONFIG_USER_ONLY)
                   1003:     /* if no code remaining, no need to continue to use slow writes */
                   1004:     if (!p->first_tb) {
                   1005:         invalidate_page_bitmap(p);
                   1006:         if (is_cpu_write_access) {
1.1.1.7   root     1007:             tlb_unprotect_code_phys(env, start, env->mem_io_vaddr);
1.1       root     1008:         }
                   1009:     }
                   1010: #endif
                   1011: #ifdef TARGET_HAS_PRECISE_SMC
                   1012:     if (current_tb_modified) {
                   1013:         /* we generate a block containing just the instruction
                   1014:            modifying the memory. It will ensure that it cannot modify
                   1015:            itself */
                   1016:         env->current_tb = NULL;
1.1.1.7   root     1017:         tb_gen_code(env, current_pc, current_cs_base, current_flags, 1);
1.1       root     1018:         cpu_resume_from_signal(env, NULL);
                   1019:     }
                   1020: #endif
                   1021: }
                   1022: 
                   1023: /* len must be <= 8 and start must be a multiple of len */
1.1.1.7   root     1024: static inline void tb_invalidate_phys_page_fast(target_phys_addr_t start, int len)
1.1       root     1025: {
                   1026:     PageDesc *p;
                   1027:     int offset, b;
                   1028: #if 0
                   1029:     if (1) {
1.1.1.7   root     1030:         qemu_log("modifying code at 0x%x size=%d EIP=%x PC=%08x\n",
                   1031:                   cpu_single_env->mem_io_vaddr, len,
                   1032:                   cpu_single_env->eip,
                   1033:                   cpu_single_env->eip + (long)cpu_single_env->segs[R_CS].base);
1.1       root     1034:     }
                   1035: #endif
                   1036:     p = page_find(start >> TARGET_PAGE_BITS);
1.1.1.6   root     1037:     if (!p)
1.1       root     1038:         return;
                   1039:     if (p->code_bitmap) {
                   1040:         offset = start & ~TARGET_PAGE_MASK;
                   1041:         b = p->code_bitmap[offset >> 3] >> (offset & 7);
                   1042:         if (b & ((1 << len) - 1))
                   1043:             goto do_invalidate;
                   1044:     } else {
                   1045:     do_invalidate:
                   1046:         tb_invalidate_phys_page_range(start, start + len, 1);
                   1047:     }
                   1048: }
                   1049: 
                   1050: #if !defined(CONFIG_SOFTMMU)
1.1.1.7   root     1051: static void tb_invalidate_phys_page(target_phys_addr_t addr,
1.1       root     1052:                                     unsigned long pc, void *puc)
                   1053: {
1.1.1.7   root     1054:     TranslationBlock *tb;
1.1       root     1055:     PageDesc *p;
1.1.1.7   root     1056:     int n;
1.1       root     1057: #ifdef TARGET_HAS_PRECISE_SMC
1.1.1.7   root     1058:     TranslationBlock *current_tb = NULL;
1.1       root     1059:     CPUState *env = cpu_single_env;
1.1.1.7   root     1060:     int current_tb_modified = 0;
                   1061:     target_ulong current_pc = 0;
                   1062:     target_ulong current_cs_base = 0;
                   1063:     int current_flags = 0;
1.1       root     1064: #endif
                   1065: 
                   1066:     addr &= TARGET_PAGE_MASK;
                   1067:     p = page_find(addr >> TARGET_PAGE_BITS);
1.1.1.6   root     1068:     if (!p)
1.1       root     1069:         return;
                   1070:     tb = p->first_tb;
                   1071: #ifdef TARGET_HAS_PRECISE_SMC
                   1072:     if (tb && pc != 0) {
                   1073:         current_tb = tb_find_pc(pc);
                   1074:     }
                   1075: #endif
                   1076:     while (tb != NULL) {
                   1077:         n = (long)tb & 3;
                   1078:         tb = (TranslationBlock *)((long)tb & ~3);
                   1079: #ifdef TARGET_HAS_PRECISE_SMC
                   1080:         if (current_tb == tb &&
1.1.1.7   root     1081:             (current_tb->cflags & CF_COUNT_MASK) != 1) {
1.1       root     1082:                 /* If we are modifying the current TB, we must stop
                   1083:                    its execution. We could be more precise by checking
                   1084:                    that the modification is after the current PC, but it
                   1085:                    would require a specialized function to partially
                   1086:                    restore the CPU state */
1.1.1.6   root     1087: 
1.1       root     1088:             current_tb_modified = 1;
                   1089:             cpu_restore_state(current_tb, env, pc, puc);
1.1.1.7   root     1090:             cpu_get_tb_cpu_state(env, &current_pc, &current_cs_base,
                   1091:                                  &current_flags);
1.1       root     1092:         }
                   1093: #endif /* TARGET_HAS_PRECISE_SMC */
                   1094:         tb_phys_invalidate(tb, addr);
                   1095:         tb = tb->page_next[n];
                   1096:     }
                   1097:     p->first_tb = NULL;
                   1098: #ifdef TARGET_HAS_PRECISE_SMC
                   1099:     if (current_tb_modified) {
                   1100:         /* we generate a block containing just the instruction
                   1101:            modifying the memory. It will ensure that it cannot modify
                   1102:            itself */
                   1103:         env->current_tb = NULL;
1.1.1.7   root     1104:         tb_gen_code(env, current_pc, current_cs_base, current_flags, 1);
1.1       root     1105:         cpu_resume_from_signal(env, puc);
                   1106:     }
                   1107: #endif
                   1108: }
                   1109: #endif
                   1110: 
                   1111: /* add the tb in the target page and protect it if necessary */
1.1.1.6   root     1112: static inline void tb_alloc_page(TranslationBlock *tb,
1.1.1.3   root     1113:                                  unsigned int n, target_ulong page_addr)
1.1       root     1114: {
                   1115:     PageDesc *p;
                   1116:     TranslationBlock *last_first_tb;
                   1117: 
                   1118:     tb->page_addr[n] = page_addr;
                   1119:     p = page_find_alloc(page_addr >> TARGET_PAGE_BITS);
                   1120:     tb->page_next[n] = p->first_tb;
                   1121:     last_first_tb = p->first_tb;
                   1122:     p->first_tb = (TranslationBlock *)((long)tb | n);
                   1123:     invalidate_page_bitmap(p);
                   1124: 
                   1125: #if defined(TARGET_HAS_SMC) || 1
                   1126: 
                   1127: #if defined(CONFIG_USER_ONLY)
                   1128:     if (p->flags & PAGE_WRITE) {
1.1.1.3   root     1129:         target_ulong addr;
                   1130:         PageDesc *p2;
1.1       root     1131:         int prot;
                   1132: 
                   1133:         /* force the host page as non writable (writes will have a
                   1134:            page fault + mprotect overhead) */
1.1.1.3   root     1135:         page_addr &= qemu_host_page_mask;
1.1       root     1136:         prot = 0;
1.1.1.3   root     1137:         for(addr = page_addr; addr < page_addr + qemu_host_page_size;
                   1138:             addr += TARGET_PAGE_SIZE) {
                   1139: 
                   1140:             p2 = page_find (addr >> TARGET_PAGE_BITS);
                   1141:             if (!p2)
                   1142:                 continue;
                   1143:             prot |= p2->flags;
                   1144:             p2->flags &= ~PAGE_WRITE;
                   1145:             page_get_flags(addr);
                   1146:           }
1.1.1.6   root     1147:         mprotect(g2h(page_addr), qemu_host_page_size,
1.1       root     1148:                  (prot & PAGE_BITS) & ~PAGE_WRITE);
                   1149: #ifdef DEBUG_TB_INVALIDATE
1.1.1.6   root     1150:         printf("protecting code page: 0x" TARGET_FMT_lx "\n",
1.1.1.3   root     1151:                page_addr);
1.1       root     1152: #endif
                   1153:     }
                   1154: #else
                   1155:     /* if some code is already present, then the pages are already
                   1156:        protected. So we handle the case where only the first TB is
                   1157:        allocated in a physical page */
                   1158:     if (!last_first_tb) {
1.1.1.2   root     1159:         tlb_protect_code(page_addr);
1.1       root     1160:     }
                   1161: #endif
                   1162: 
                   1163: #endif /* TARGET_HAS_SMC */
                   1164: }
                   1165: 
                   1166: /* Allocate a new translation block. Flush the translation buffer if
                   1167:    too many translation blocks or too much generated code. */
                   1168: TranslationBlock *tb_alloc(target_ulong pc)
                   1169: {
                   1170:     TranslationBlock *tb;
                   1171: 
1.1.1.7   root     1172:     if (nb_tbs >= code_gen_max_blocks ||
                   1173:         (code_gen_ptr - code_gen_buffer) >= code_gen_buffer_max_size)
1.1       root     1174:         return NULL;
                   1175:     tb = &tbs[nb_tbs++];
                   1176:     tb->pc = pc;
                   1177:     tb->cflags = 0;
                   1178:     return tb;
                   1179: }
                   1180: 
1.1.1.7   root     1181: void tb_free(TranslationBlock *tb)
                   1182: {
                   1183:     /* In practice this is mostly used for single use temporary TB
                   1184:        Ignore the hard cases and just back up if this TB happens to
                   1185:        be the last one generated.  */
                   1186:     if (nb_tbs > 0 && tb == &tbs[nb_tbs - 1]) {
                   1187:         code_gen_ptr = tb->tc_ptr;
                   1188:         nb_tbs--;
                   1189:     }
                   1190: }
                   1191: 
1.1       root     1192: /* add a new TB and link it to the physical page tables. phys_page2 is
                   1193:    (-1) to indicate that only one page contains the TB. */
1.1.1.6   root     1194: void tb_link_phys(TranslationBlock *tb,
1.1       root     1195:                   target_ulong phys_pc, target_ulong phys_page2)
                   1196: {
                   1197:     unsigned int h;
                   1198:     TranslationBlock **ptb;
                   1199: 
1.1.1.7   root     1200:     /* Grab the mmap lock to stop another thread invalidating this TB
                   1201:        before we are done.  */
                   1202:     mmap_lock();
1.1       root     1203:     /* add in the physical hash table */
                   1204:     h = tb_phys_hash_func(phys_pc);
                   1205:     ptb = &tb_phys_hash[h];
                   1206:     tb->phys_hash_next = *ptb;
                   1207:     *ptb = tb;
                   1208: 
                   1209:     /* add in the page list */
                   1210:     tb_alloc_page(tb, 0, phys_pc & TARGET_PAGE_MASK);
                   1211:     if (phys_page2 != -1)
                   1212:         tb_alloc_page(tb, 1, phys_page2);
                   1213:     else
                   1214:         tb->page_addr[1] = -1;
                   1215: 
                   1216:     tb->jmp_first = (TranslationBlock *)((long)tb | 2);
                   1217:     tb->jmp_next[0] = NULL;
                   1218:     tb->jmp_next[1] = NULL;
                   1219: 
                   1220:     /* init original jump addresses */
                   1221:     if (tb->tb_next_offset[0] != 0xffff)
                   1222:         tb_reset_jump(tb, 0);
                   1223:     if (tb->tb_next_offset[1] != 0xffff)
                   1224:         tb_reset_jump(tb, 1);
1.1.1.2   root     1225: 
                   1226: #ifdef DEBUG_TB_CHECK
                   1227:     tb_page_check();
                   1228: #endif
1.1.1.7   root     1229:     mmap_unlock();
1.1       root     1230: }
                   1231: 
                   1232: /* find the TB 'tb' such that tb[0].tc_ptr <= tc_ptr <
                   1233:    tb[1].tc_ptr. Return NULL if not found */
                   1234: TranslationBlock *tb_find_pc(unsigned long tc_ptr)
                   1235: {
                   1236:     int m_min, m_max, m;
                   1237:     unsigned long v;
                   1238:     TranslationBlock *tb;
                   1239: 
                   1240:     if (nb_tbs <= 0)
                   1241:         return NULL;
                   1242:     if (tc_ptr < (unsigned long)code_gen_buffer ||
                   1243:         tc_ptr >= (unsigned long)code_gen_ptr)
                   1244:         return NULL;
                   1245:     /* binary search (cf Knuth) */
                   1246:     m_min = 0;
                   1247:     m_max = nb_tbs - 1;
                   1248:     while (m_min <= m_max) {
                   1249:         m = (m_min + m_max) >> 1;
                   1250:         tb = &tbs[m];
                   1251:         v = (unsigned long)tb->tc_ptr;
                   1252:         if (v == tc_ptr)
                   1253:             return tb;
                   1254:         else if (tc_ptr < v) {
                   1255:             m_max = m - 1;
                   1256:         } else {
                   1257:             m_min = m + 1;
                   1258:         }
1.1.1.6   root     1259:     }
1.1       root     1260:     return &tbs[m_max];
                   1261: }
                   1262: 
                   1263: static void tb_reset_jump_recursive(TranslationBlock *tb);
                   1264: 
                   1265: static inline void tb_reset_jump_recursive2(TranslationBlock *tb, int n)
                   1266: {
                   1267:     TranslationBlock *tb1, *tb_next, **ptb;
                   1268:     unsigned int n1;
                   1269: 
                   1270:     tb1 = tb->jmp_next[n];
                   1271:     if (tb1 != NULL) {
                   1272:         /* find head of list */
                   1273:         for(;;) {
                   1274:             n1 = (long)tb1 & 3;
                   1275:             tb1 = (TranslationBlock *)((long)tb1 & ~3);
                   1276:             if (n1 == 2)
                   1277:                 break;
                   1278:             tb1 = tb1->jmp_next[n1];
                   1279:         }
                   1280:         /* we are now sure now that tb jumps to tb1 */
                   1281:         tb_next = tb1;
                   1282: 
                   1283:         /* remove tb from the jmp_first list */
                   1284:         ptb = &tb_next->jmp_first;
                   1285:         for(;;) {
                   1286:             tb1 = *ptb;
                   1287:             n1 = (long)tb1 & 3;
                   1288:             tb1 = (TranslationBlock *)((long)tb1 & ~3);
                   1289:             if (n1 == n && tb1 == tb)
                   1290:                 break;
                   1291:             ptb = &tb1->jmp_next[n1];
                   1292:         }
                   1293:         *ptb = tb->jmp_next[n];
                   1294:         tb->jmp_next[n] = NULL;
1.1.1.6   root     1295: 
1.1       root     1296:         /* suppress the jump to next tb in generated code */
                   1297:         tb_reset_jump(tb, n);
                   1298: 
                   1299:         /* suppress jumps in the tb on which we could have jumped */
                   1300:         tb_reset_jump_recursive(tb_next);
                   1301:     }
                   1302: }
                   1303: 
                   1304: static void tb_reset_jump_recursive(TranslationBlock *tb)
                   1305: {
                   1306:     tb_reset_jump_recursive2(tb, 0);
                   1307:     tb_reset_jump_recursive2(tb, 1);
                   1308: }
                   1309: 
                   1310: #if defined(TARGET_HAS_ICE)
                   1311: static void breakpoint_invalidate(CPUState *env, target_ulong pc)
                   1312: {
1.1.1.6   root     1313:     target_phys_addr_t addr;
                   1314:     target_ulong pd;
1.1.1.3   root     1315:     ram_addr_t ram_addr;
                   1316:     PhysPageDesc *p;
1.1       root     1317: 
1.1.1.3   root     1318:     addr = cpu_get_phys_page_debug(env, pc);
                   1319:     p = phys_page_find(addr >> TARGET_PAGE_BITS);
                   1320:     if (!p) {
                   1321:         pd = IO_MEM_UNASSIGNED;
                   1322:     } else {
                   1323:         pd = p->phys_offset;
                   1324:     }
                   1325:     ram_addr = (pd & TARGET_PAGE_MASK) | (pc & ~TARGET_PAGE_MASK);
                   1326:     tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0);
1.1       root     1327: }
                   1328: #endif
                   1329: 
1.1.1.6   root     1330: /* Add a watchpoint.  */
1.1.1.7   root     1331: int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len,
                   1332:                           int flags, CPUWatchpoint **watchpoint)
1.1.1.6   root     1333: {
1.1.1.7   root     1334:     target_ulong len_mask = ~(len - 1);
                   1335:     CPUWatchpoint *wp;
                   1336: 
                   1337:     /* sanity checks: allow power-of-2 lengths, deny unaligned watchpoints */
                   1338:     if ((len != 1 && len != 2 && len != 4 && len != 8) || (addr & ~len_mask)) {
                   1339:         fprintf(stderr, "qemu: tried to set invalid watchpoint at "
                   1340:                 TARGET_FMT_lx ", len=" TARGET_FMT_lu "\n", addr, len);
                   1341:         return -EINVAL;
                   1342:     }
                   1343:     wp = qemu_malloc(sizeof(*wp));
                   1344: 
                   1345:     wp->vaddr = addr;
                   1346:     wp->len_mask = len_mask;
                   1347:     wp->flags = flags;
                   1348: 
                   1349:     /* keep all GDB-injected watchpoints in front */
                   1350:     if (flags & BP_GDB)
1.1.1.11  root     1351:         QTAILQ_INSERT_HEAD(&env->watchpoints, wp, entry);
1.1.1.7   root     1352:     else
1.1.1.11  root     1353:         QTAILQ_INSERT_TAIL(&env->watchpoints, wp, entry);
1.1.1.7   root     1354: 
                   1355:     tlb_flush_page(env, addr);
                   1356: 
                   1357:     if (watchpoint)
                   1358:         *watchpoint = wp;
                   1359:     return 0;
                   1360: }
1.1.1.6   root     1361: 
1.1.1.7   root     1362: /* Remove a specific watchpoint.  */
                   1363: int cpu_watchpoint_remove(CPUState *env, target_ulong addr, target_ulong len,
                   1364:                           int flags)
                   1365: {
                   1366:     target_ulong len_mask = ~(len - 1);
                   1367:     CPUWatchpoint *wp;
                   1368: 
1.1.1.11  root     1369:     QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
1.1.1.7   root     1370:         if (addr == wp->vaddr && len_mask == wp->len_mask
                   1371:                 && flags == (wp->flags & ~BP_WATCHPOINT_HIT)) {
                   1372:             cpu_watchpoint_remove_by_ref(env, wp);
1.1.1.6   root     1373:             return 0;
1.1.1.7   root     1374:         }
1.1.1.6   root     1375:     }
1.1.1.7   root     1376:     return -ENOENT;
                   1377: }
1.1.1.6   root     1378: 
1.1.1.7   root     1379: /* Remove a specific watchpoint by reference.  */
                   1380: void cpu_watchpoint_remove_by_ref(CPUState *env, CPUWatchpoint *watchpoint)
                   1381: {
1.1.1.11  root     1382:     QTAILQ_REMOVE(&env->watchpoints, watchpoint, entry);
1.1.1.7   root     1383: 
                   1384:     tlb_flush_page(env, watchpoint->vaddr);
                   1385: 
                   1386:     qemu_free(watchpoint);
1.1.1.6   root     1387: }
                   1388: 
1.1.1.7   root     1389: /* Remove all matching watchpoints.  */
                   1390: void cpu_watchpoint_remove_all(CPUState *env, int mask)
1.1.1.6   root     1391: {
1.1.1.7   root     1392:     CPUWatchpoint *wp, *next;
1.1.1.6   root     1393: 
1.1.1.11  root     1394:     QTAILQ_FOREACH_SAFE(wp, &env->watchpoints, entry, next) {
1.1.1.7   root     1395:         if (wp->flags & mask)
                   1396:             cpu_watchpoint_remove_by_ref(env, wp);
1.1.1.6   root     1397:     }
                   1398: }
                   1399: 
1.1.1.7   root     1400: /* Add a breakpoint.  */
                   1401: int cpu_breakpoint_insert(CPUState *env, target_ulong pc, int flags,
                   1402:                           CPUBreakpoint **breakpoint)
1.1       root     1403: {
                   1404: #if defined(TARGET_HAS_ICE)
1.1.1.7   root     1405:     CPUBreakpoint *bp;
1.1.1.6   root     1406: 
1.1.1.7   root     1407:     bp = qemu_malloc(sizeof(*bp));
1.1       root     1408: 
1.1.1.7   root     1409:     bp->pc = pc;
                   1410:     bp->flags = flags;
                   1411: 
                   1412:     /* keep all GDB-injected breakpoints in front */
                   1413:     if (flags & BP_GDB)
1.1.1.11  root     1414:         QTAILQ_INSERT_HEAD(&env->breakpoints, bp, entry);
1.1.1.7   root     1415:     else
1.1.1.11  root     1416:         QTAILQ_INSERT_TAIL(&env->breakpoints, bp, entry);
1.1.1.6   root     1417: 
1.1       root     1418:     breakpoint_invalidate(env, pc);
1.1.1.7   root     1419: 
                   1420:     if (breakpoint)
                   1421:         *breakpoint = bp;
1.1       root     1422:     return 0;
                   1423: #else
1.1.1.7   root     1424:     return -ENOSYS;
1.1       root     1425: #endif
                   1426: }
                   1427: 
1.1.1.7   root     1428: /* Remove a specific breakpoint.  */
                   1429: int cpu_breakpoint_remove(CPUState *env, target_ulong pc, int flags)
1.1       root     1430: {
                   1431: #if defined(TARGET_HAS_ICE)
1.1.1.7   root     1432:     CPUBreakpoint *bp;
1.1       root     1433: 
1.1.1.11  root     1434:     QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
1.1.1.7   root     1435:         if (bp->pc == pc && bp->flags == flags) {
                   1436:             cpu_breakpoint_remove_by_ref(env, bp);
                   1437:             return 0;
                   1438:         }
                   1439:     }
                   1440:     return -ENOENT;
1.1       root     1441: #else
1.1.1.7   root     1442:     return -ENOSYS;
                   1443: #endif
                   1444: }
                   1445: 
                   1446: /* Remove a specific breakpoint by reference.  */
                   1447: void cpu_breakpoint_remove_by_ref(CPUState *env, CPUBreakpoint *breakpoint)
                   1448: {
                   1449: #if defined(TARGET_HAS_ICE)
1.1.1.11  root     1450:     QTAILQ_REMOVE(&env->breakpoints, breakpoint, entry);
1.1.1.7   root     1451: 
                   1452:     breakpoint_invalidate(env, breakpoint->pc);
                   1453: 
                   1454:     qemu_free(breakpoint);
                   1455: #endif
                   1456: }
                   1457: 
                   1458: /* Remove all matching breakpoints. */
                   1459: void cpu_breakpoint_remove_all(CPUState *env, int mask)
                   1460: {
                   1461: #if defined(TARGET_HAS_ICE)
                   1462:     CPUBreakpoint *bp, *next;
                   1463: 
1.1.1.11  root     1464:     QTAILQ_FOREACH_SAFE(bp, &env->breakpoints, entry, next) {
1.1.1.7   root     1465:         if (bp->flags & mask)
                   1466:             cpu_breakpoint_remove_by_ref(env, bp);
                   1467:     }
1.1       root     1468: #endif
                   1469: }
                   1470: 
                   1471: /* enable or disable single step mode. EXCP_DEBUG is returned by the
                   1472:    CPU loop after each instruction */
                   1473: void cpu_single_step(CPUState *env, int enabled)
                   1474: {
                   1475: #if defined(TARGET_HAS_ICE)
                   1476:     if (env->singlestep_enabled != enabled) {
                   1477:         env->singlestep_enabled = enabled;
1.1.1.10  root     1478:         if (kvm_enabled())
                   1479:             kvm_update_guest_debug(env, 0);
                   1480:         else {
                   1481:             /* must flush all the translated code to avoid inconsistencies */
                   1482:             /* XXX: only flush what is necessary */
                   1483:             tb_flush(env);
                   1484:         }
1.1       root     1485:     }
                   1486: #endif
                   1487: }
                   1488: 
                   1489: /* enable or disable low levels log */
                   1490: void cpu_set_log(int log_flags)
                   1491: {
                   1492:     loglevel = log_flags;
                   1493:     if (loglevel && !logfile) {
1.1.1.6   root     1494:         logfile = fopen(logfilename, log_append ? "a" : "w");
1.1       root     1495:         if (!logfile) {
                   1496:             perror(logfilename);
                   1497:             _exit(1);
                   1498:         }
                   1499: #if !defined(CONFIG_SOFTMMU)
                   1500:         /* must avoid mmap() usage of glibc by setting a buffer "by hand" */
                   1501:         {
1.1.1.7   root     1502:             static char logfile_buf[4096];
1.1       root     1503:             setvbuf(logfile, logfile_buf, _IOLBF, sizeof(logfile_buf));
                   1504:         }
1.1.1.11  root     1505: #elif !defined(_WIN32)
                   1506:         /* Win32 doesn't support line-buffering and requires size >= 2 */
1.1       root     1507:         setvbuf(logfile, NULL, _IOLBF, 0);
                   1508: #endif
1.1.1.6   root     1509:         log_append = 1;
                   1510:     }
                   1511:     if (!loglevel && logfile) {
                   1512:         fclose(logfile);
                   1513:         logfile = NULL;
1.1       root     1514:     }
                   1515: }
                   1516: 
                   1517: void cpu_set_log_filename(const char *filename)
                   1518: {
                   1519:     logfilename = strdup(filename);
1.1.1.6   root     1520:     if (logfile) {
                   1521:         fclose(logfile);
                   1522:         logfile = NULL;
                   1523:     }
                   1524:     cpu_set_log(loglevel);
1.1       root     1525: }
                   1526: 
1.1.1.10  root     1527: static void cpu_unlink_tb(CPUState *env)
1.1       root     1528: {
1.1.1.11  root     1529: #if defined(CONFIG_USE_NPTL)
1.1.1.10  root     1530:     /* FIXME: TB unchaining isn't SMP safe.  For now just ignore the
                   1531:        problem and hope the cpu will stop of its own accord.  For userspace
                   1532:        emulation this often isn't actually as bad as it sounds.  Often
                   1533:        signals are used primarily to interrupt blocking syscalls.  */
                   1534: #else
1.1       root     1535:     TranslationBlock *tb;
1.1.1.7   root     1536:     static spinlock_t interrupt_lock = SPIN_LOCK_UNLOCKED;
1.1       root     1537: 
1.1.1.10  root     1538:     tb = env->current_tb;
                   1539:     /* if the cpu is currently executing code, we must unlink it and
                   1540:        all the potentially executing TB */
                   1541:     if (tb && !testandset(&interrupt_lock)) {
                   1542:         env->current_tb = NULL;
                   1543:         tb_reset_jump_recursive(tb);
                   1544:         resetlock(&interrupt_lock);
1.1.1.8   root     1545:     }
1.1.1.10  root     1546: #endif
                   1547: }
                   1548: 
                   1549: /* mask must never be zero, except for A20 change call */
                   1550: void cpu_interrupt(CPUState *env, int mask)
                   1551: {
                   1552:     int old_mask;
1.1.1.8   root     1553: 
1.1.1.7   root     1554:     old_mask = env->interrupt_request;
1.1       root     1555:     env->interrupt_request |= mask;
1.1.1.10  root     1556: 
                   1557: #ifndef CONFIG_USER_ONLY
                   1558:     /*
                   1559:      * If called from iothread context, wake the target cpu in
                   1560:      * case its halted.
                   1561:      */
                   1562:     if (!qemu_cpu_self(env)) {
                   1563:         qemu_cpu_kick(env);
                   1564:         return;
                   1565:     }
                   1566: #endif
                   1567: 
1.1.1.7   root     1568:     if (use_icount) {
                   1569:         env->icount_decr.u16.high = 0xffff;
                   1570: #ifndef CONFIG_USER_ONLY
                   1571:         if (!can_do_io(env)
1.1.1.8   root     1572:             && (mask & ~old_mask) != 0) {
1.1.1.7   root     1573:             cpu_abort(env, "Raised interrupt while not in I/O function");
                   1574:         }
                   1575: #endif
                   1576:     } else {
1.1.1.10  root     1577:         cpu_unlink_tb(env);
1.1       root     1578:     }
                   1579: }
                   1580: 
                   1581: void cpu_reset_interrupt(CPUState *env, int mask)
                   1582: {
                   1583:     env->interrupt_request &= ~mask;
                   1584: }
                   1585: 
1.1.1.10  root     1586: void cpu_exit(CPUState *env)
                   1587: {
                   1588:     env->exit_request = 1;
                   1589:     cpu_unlink_tb(env);
                   1590: }
                   1591: 
1.1.1.7   root     1592: const CPULogItem cpu_log_items[] = {
1.1.1.6   root     1593:     { CPU_LOG_TB_OUT_ASM, "out_asm",
1.1       root     1594:       "show generated host assembly code for each compiled TB" },
                   1595:     { CPU_LOG_TB_IN_ASM, "in_asm",
                   1596:       "show target assembly code for each compiled TB" },
1.1.1.6   root     1597:     { CPU_LOG_TB_OP, "op",
1.1.1.7   root     1598:       "show micro ops for each compiled TB" },
1.1       root     1599:     { CPU_LOG_TB_OP_OPT, "op_opt",
1.1.1.7   root     1600:       "show micro ops "
                   1601: #ifdef TARGET_I386
                   1602:       "before eflags optimization and "
1.1       root     1603: #endif
1.1.1.7   root     1604:       "after liveness analysis" },
1.1       root     1605:     { CPU_LOG_INT, "int",
                   1606:       "show interrupts/exceptions in short format" },
                   1607:     { CPU_LOG_EXEC, "exec",
                   1608:       "show trace before each executed TB (lots of logs)" },
                   1609:     { CPU_LOG_TB_CPU, "cpu",
1.1.1.6   root     1610:       "show CPU state before block translation" },
1.1       root     1611: #ifdef TARGET_I386
                   1612:     { CPU_LOG_PCALL, "pcall",
                   1613:       "show protected mode far calls/returns/exceptions" },
1.1.1.7   root     1614:     { CPU_LOG_RESET, "cpu_reset",
                   1615:       "show CPU state before CPU resets" },
1.1       root     1616: #endif
                   1617: #ifdef DEBUG_IOPORT
                   1618:     { CPU_LOG_IOPORT, "ioport",
                   1619:       "show all i/o ports accesses" },
                   1620: #endif
                   1621:     { 0, NULL, NULL },
                   1622: };
                   1623: 
                   1624: static int cmp1(const char *s1, int n, const char *s2)
                   1625: {
                   1626:     if (strlen(s2) != n)
                   1627:         return 0;
                   1628:     return memcmp(s1, s2, n) == 0;
                   1629: }
1.1.1.6   root     1630: 
1.1       root     1631: /* takes a comma separated list of log masks. Return 0 if error. */
                   1632: int cpu_str_to_log_mask(const char *str)
                   1633: {
1.1.1.7   root     1634:     const CPULogItem *item;
1.1       root     1635:     int mask;
                   1636:     const char *p, *p1;
                   1637: 
                   1638:     p = str;
                   1639:     mask = 0;
                   1640:     for(;;) {
                   1641:         p1 = strchr(p, ',');
                   1642:         if (!p1)
                   1643:             p1 = p + strlen(p);
                   1644:        if(cmp1(p,p1-p,"all")) {
                   1645:                for(item = cpu_log_items; item->mask != 0; item++) {
                   1646:                        mask |= item->mask;
                   1647:                }
                   1648:        } else {
                   1649:         for(item = cpu_log_items; item->mask != 0; item++) {
                   1650:             if (cmp1(p, p1 - p, item->name))
                   1651:                 goto found;
                   1652:         }
                   1653:         return 0;
                   1654:        }
                   1655:     found:
                   1656:         mask |= item->mask;
                   1657:         if (*p1 != ',')
                   1658:             break;
                   1659:         p = p1 + 1;
                   1660:     }
                   1661:     return mask;
                   1662: }
                   1663: 
                   1664: void cpu_abort(CPUState *env, const char *fmt, ...)
                   1665: {
                   1666:     va_list ap;
1.1.1.6   root     1667:     va_list ap2;
1.1       root     1668: 
                   1669:     va_start(ap, fmt);
1.1.1.6   root     1670:     va_copy(ap2, ap);
1.1       root     1671:     fprintf(stderr, "qemu: fatal: ");
                   1672:     vfprintf(stderr, fmt, ap);
                   1673:     fprintf(stderr, "\n");
                   1674: #ifdef TARGET_I386
                   1675:     cpu_dump_state(env, stderr, fprintf, X86_DUMP_FPU | X86_DUMP_CCOP);
                   1676: #else
                   1677:     cpu_dump_state(env, stderr, fprintf, 0);
                   1678: #endif
1.1.1.7   root     1679:     if (qemu_log_enabled()) {
                   1680:         qemu_log("qemu: fatal: ");
                   1681:         qemu_log_vprintf(fmt, ap2);
                   1682:         qemu_log("\n");
1.1.1.6   root     1683: #ifdef TARGET_I386
1.1.1.7   root     1684:         log_cpu_state(env, X86_DUMP_FPU | X86_DUMP_CCOP);
1.1.1.6   root     1685: #else
1.1.1.7   root     1686:         log_cpu_state(env, 0);
1.1.1.6   root     1687: #endif
1.1.1.7   root     1688:         qemu_log_flush();
                   1689:         qemu_log_close();
1.1.1.6   root     1690:     }
                   1691:     va_end(ap2);
1.1       root     1692:     va_end(ap);
                   1693:     abort();
                   1694: }
                   1695: 
1.1.1.6   root     1696: CPUState *cpu_copy(CPUState *env)
                   1697: {
                   1698:     CPUState *new_env = cpu_init(env->cpu_model_str);
                   1699:     CPUState *next_cpu = new_env->next_cpu;
                   1700:     int cpu_index = new_env->cpu_index;
1.1.1.7   root     1701: #if defined(TARGET_HAS_ICE)
                   1702:     CPUBreakpoint *bp;
                   1703:     CPUWatchpoint *wp;
                   1704: #endif
                   1705: 
1.1.1.6   root     1706:     memcpy(new_env, env, sizeof(CPUState));
1.1.1.7   root     1707: 
                   1708:     /* Preserve chaining and index. */
1.1.1.6   root     1709:     new_env->next_cpu = next_cpu;
                   1710:     new_env->cpu_index = cpu_index;
1.1.1.7   root     1711: 
                   1712:     /* Clone all break/watchpoints.
                   1713:        Note: Once we support ptrace with hw-debug register access, make sure
                   1714:        BP_CPU break/watchpoints are handled correctly on clone. */
1.1.1.11  root     1715:     QTAILQ_INIT(&env->breakpoints);
                   1716:     QTAILQ_INIT(&env->watchpoints);
1.1.1.7   root     1717: #if defined(TARGET_HAS_ICE)
1.1.1.11  root     1718:     QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
1.1.1.7   root     1719:         cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL);
                   1720:     }
1.1.1.11  root     1721:     QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
1.1.1.7   root     1722:         cpu_watchpoint_insert(new_env, wp->vaddr, (~wp->len_mask) + 1,
                   1723:                               wp->flags, NULL);
                   1724:     }
                   1725: #endif
                   1726: 
1.1.1.6   root     1727:     return new_env;
                   1728: }
                   1729: 
1.1       root     1730: #if !defined(CONFIG_USER_ONLY)
                   1731: 
1.1.1.7   root     1732: static inline void tlb_flush_jmp_cache(CPUState *env, target_ulong addr)
                   1733: {
                   1734:     unsigned int i;
                   1735: 
                   1736:     /* Discard jump cache entries for any tb which might potentially
                   1737:        overlap the flushed page.  */
                   1738:     i = tb_jmp_cache_hash_page(addr - TARGET_PAGE_SIZE);
                   1739:     memset (&env->tb_jmp_cache[i], 0, 
                   1740:            TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *));
                   1741: 
                   1742:     i = tb_jmp_cache_hash_page(addr);
                   1743:     memset (&env->tb_jmp_cache[i], 0, 
                   1744:            TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *));
                   1745: }
                   1746: 
1.1.1.10  root     1747: static CPUTLBEntry s_cputlb_empty_entry = {
                   1748:     .addr_read  = -1,
                   1749:     .addr_write = -1,
                   1750:     .addr_code  = -1,
                   1751:     .addend     = -1,
                   1752: };
                   1753: 
1.1       root     1754: /* NOTE: if flush_global is true, also flush global entries (not
                   1755:    implemented yet) */
                   1756: void tlb_flush(CPUState *env, int flush_global)
                   1757: {
                   1758:     int i;
                   1759: 
                   1760: #if defined(DEBUG_TLB)
                   1761:     printf("tlb_flush:\n");
                   1762: #endif
                   1763:     /* must reset current TB so that interrupts cannot modify the
                   1764:        links while we are modifying them */
                   1765:     env->current_tb = NULL;
                   1766: 
                   1767:     for(i = 0; i < CPU_TLB_SIZE; i++) {
1.1.1.10  root     1768:         int mmu_idx;
                   1769:         for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
                   1770:             env->tlb_table[mmu_idx][i] = s_cputlb_empty_entry;
                   1771:         }
1.1       root     1772:     }
                   1773: 
1.1.1.2   root     1774:     memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *));
1.1       root     1775: 
                   1776:     tlb_flush_count++;
                   1777: }
                   1778: 
                   1779: static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr)
                   1780: {
1.1.1.6   root     1781:     if (addr == (tlb_entry->addr_read &
1.1.1.2   root     1782:                  (TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
1.1.1.6   root     1783:         addr == (tlb_entry->addr_write &
1.1.1.2   root     1784:                  (TARGET_PAGE_MASK | TLB_INVALID_MASK)) ||
1.1.1.6   root     1785:         addr == (tlb_entry->addr_code &
1.1.1.2   root     1786:                  (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
1.1.1.10  root     1787:         *tlb_entry = s_cputlb_empty_entry;
1.1.1.2   root     1788:     }
1.1       root     1789: }
                   1790: 
                   1791: void tlb_flush_page(CPUState *env, target_ulong addr)
                   1792: {
1.1.1.2   root     1793:     int i;
1.1.1.10  root     1794:     int mmu_idx;
1.1       root     1795: 
                   1796: #if defined(DEBUG_TLB)
                   1797:     printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr);
                   1798: #endif
                   1799:     /* must reset current TB so that interrupts cannot modify the
                   1800:        links while we are modifying them */
                   1801:     env->current_tb = NULL;
                   1802: 
                   1803:     addr &= TARGET_PAGE_MASK;
                   1804:     i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
1.1.1.10  root     1805:     for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++)
                   1806:         tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr);
1.1       root     1807: 
1.1.1.7   root     1808:     tlb_flush_jmp_cache(env, addr);
1.1       root     1809: }
                   1810: 
                   1811: /* update the TLBs so that writes to code in the virtual page 'addr'
                   1812:    can be detected */
1.1.1.2   root     1813: static void tlb_protect_code(ram_addr_t ram_addr)
1.1       root     1814: {
1.1.1.6   root     1815:     cpu_physical_memory_reset_dirty(ram_addr,
1.1.1.2   root     1816:                                     ram_addr + TARGET_PAGE_SIZE,
                   1817:                                     CODE_DIRTY_FLAG);
1.1       root     1818: }
                   1819: 
                   1820: /* update the TLB so that writes in physical page 'phys_addr' are no longer
                   1821:    tested for self modifying code */
1.1.1.6   root     1822: static void tlb_unprotect_code_phys(CPUState *env, ram_addr_t ram_addr,
1.1       root     1823:                                     target_ulong vaddr)
                   1824: {
                   1825:     phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] |= CODE_DIRTY_FLAG;
                   1826: }
                   1827: 
1.1.1.6   root     1828: static inline void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry,
1.1       root     1829:                                          unsigned long start, unsigned long length)
                   1830: {
                   1831:     unsigned long addr;
1.1.1.2   root     1832:     if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) {
                   1833:         addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend;
1.1       root     1834:         if ((addr - start) < length) {
1.1.1.7   root     1835:             tlb_entry->addr_write = (tlb_entry->addr_write & TARGET_PAGE_MASK) | TLB_NOTDIRTY;
1.1       root     1836:         }
                   1837:     }
                   1838: }
                   1839: 
1.1.1.10  root     1840: /* Note: start and end must be within the same ram block.  */
1.1       root     1841: void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
                   1842:                                      int dirty_flags)
                   1843: {
                   1844:     CPUState *env;
                   1845:     unsigned long length, start1;
                   1846:     int i, mask, len;
                   1847:     uint8_t *p;
                   1848: 
                   1849:     start &= TARGET_PAGE_MASK;
                   1850:     end = TARGET_PAGE_ALIGN(end);
                   1851: 
                   1852:     length = end - start;
                   1853:     if (length == 0)
                   1854:         return;
                   1855:     len = length >> TARGET_PAGE_BITS;
                   1856:     mask = ~dirty_flags;
                   1857:     p = phys_ram_dirty + (start >> TARGET_PAGE_BITS);
                   1858:     for(i = 0; i < len; i++)
                   1859:         p[i] &= mask;
                   1860: 
                   1861:     /* we modify the TLB cache so that the dirty bit will be set again
                   1862:        when accessing the range */
1.1.1.10  root     1863:     start1 = (unsigned long)qemu_get_ram_ptr(start);
                   1864:     /* Chek that we don't span multiple blocks - this breaks the
                   1865:        address comparisons below.  */
                   1866:     if ((unsigned long)qemu_get_ram_ptr(end - 1) - start1
                   1867:             != (end - 1) - start) {
                   1868:         abort();
                   1869:     }
                   1870: 
1.1.1.2   root     1871:     for(env = first_cpu; env != NULL; env = env->next_cpu) {
1.1.1.10  root     1872:         int mmu_idx;
                   1873:         for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
                   1874:             for(i = 0; i < CPU_TLB_SIZE; i++)
                   1875:                 tlb_reset_dirty_range(&env->tlb_table[mmu_idx][i],
                   1876:                                       start1, length);
                   1877:         }
1.1.1.2   root     1878:     }
1.1.1.7   root     1879: }
1.1       root     1880: 
1.1.1.7   root     1881: int cpu_physical_memory_set_dirty_tracking(int enable)
                   1882: {
                   1883:     in_migration = enable;
1.1.1.10  root     1884:     if (kvm_enabled()) {
                   1885:         return kvm_set_migration_log(enable);
                   1886:     }
1.1.1.7   root     1887:     return 0;
                   1888: }
1.1       root     1889: 
1.1.1.7   root     1890: int cpu_physical_memory_get_dirty_tracking(void)
                   1891: {
                   1892:     return in_migration;
                   1893: }
                   1894: 
1.1.1.10  root     1895: int cpu_physical_sync_dirty_bitmap(target_phys_addr_t start_addr,
                   1896:                                    target_phys_addr_t end_addr)
1.1.1.7   root     1897: {
1.1.1.10  root     1898:     int ret = 0;
                   1899: 
1.1.1.7   root     1900:     if (kvm_enabled())
1.1.1.10  root     1901:         ret = kvm_physical_sync_dirty_bitmap(start_addr, end_addr);
                   1902:     return ret;
1.1       root     1903: }
                   1904: 
                   1905: static inline void tlb_update_dirty(CPUTLBEntry *tlb_entry)
                   1906: {
                   1907:     ram_addr_t ram_addr;
1.1.1.10  root     1908:     void *p;
1.1       root     1909: 
1.1.1.2   root     1910:     if ((tlb_entry->addr_write & ~TARGET_PAGE_MASK) == IO_MEM_RAM) {
1.1.1.10  root     1911:         p = (void *)(unsigned long)((tlb_entry->addr_write & TARGET_PAGE_MASK)
                   1912:             + tlb_entry->addend);
                   1913:         ram_addr = qemu_ram_addr_from_host(p);
1.1       root     1914:         if (!cpu_physical_memory_is_dirty(ram_addr)) {
1.1.1.7   root     1915:             tlb_entry->addr_write |= TLB_NOTDIRTY;
1.1       root     1916:         }
                   1917:     }
                   1918: }
                   1919: 
                   1920: /* update the TLB according to the current state of the dirty bits */
                   1921: void cpu_tlb_update_dirty(CPUState *env)
                   1922: {
                   1923:     int i;
1.1.1.10  root     1924:     int mmu_idx;
                   1925:     for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
                   1926:         for(i = 0; i < CPU_TLB_SIZE; i++)
                   1927:             tlb_update_dirty(&env->tlb_table[mmu_idx][i]);
                   1928:     }
1.1       root     1929: }
                   1930: 
1.1.1.7   root     1931: static inline void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr)
1.1       root     1932: {
1.1.1.7   root     1933:     if (tlb_entry->addr_write == (vaddr | TLB_NOTDIRTY))
                   1934:         tlb_entry->addr_write = vaddr;
1.1       root     1935: }
                   1936: 
1.1.1.7   root     1937: /* update the TLB corresponding to virtual page vaddr
                   1938:    so that it is no longer dirty */
                   1939: static inline void tlb_set_dirty(CPUState *env, target_ulong vaddr)
1.1       root     1940: {
                   1941:     int i;
1.1.1.10  root     1942:     int mmu_idx;
1.1       root     1943: 
1.1.1.7   root     1944:     vaddr &= TARGET_PAGE_MASK;
1.1       root     1945:     i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
1.1.1.10  root     1946:     for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++)
                   1947:         tlb_set_dirty1(&env->tlb_table[mmu_idx][i], vaddr);
1.1       root     1948: }
                   1949: 
                   1950: /* add a new TLB entry. At most one entry for a given virtual address
                   1951:    is permitted. Return 0 if OK or 2 if the page could not be mapped
                   1952:    (can only happen in non SOFTMMU mode for I/O pages or pages
                   1953:    conflicting with the host address space). */
1.1.1.6   root     1954: int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
                   1955:                       target_phys_addr_t paddr, int prot,
                   1956:                       int mmu_idx, int is_softmmu)
1.1       root     1957: {
                   1958:     PhysPageDesc *p;
                   1959:     unsigned long pd;
                   1960:     unsigned int index;
                   1961:     target_ulong address;
1.1.1.7   root     1962:     target_ulong code_address;
1.1       root     1963:     target_phys_addr_t addend;
                   1964:     int ret;
1.1.1.2   root     1965:     CPUTLBEntry *te;
1.1.1.7   root     1966:     CPUWatchpoint *wp;
                   1967:     target_phys_addr_t iotlb;
1.1       root     1968: 
                   1969:     p = phys_page_find(paddr >> TARGET_PAGE_BITS);
                   1970:     if (!p) {
                   1971:         pd = IO_MEM_UNASSIGNED;
                   1972:     } else {
                   1973:         pd = p->phys_offset;
                   1974:     }
                   1975: #if defined(DEBUG_TLB)
1.1.1.6   root     1976:     printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x%08x prot=%x idx=%d smmu=%d pd=0x%08lx\n",
                   1977:            vaddr, (int)paddr, prot, mmu_idx, is_softmmu, pd);
1.1       root     1978: #endif
                   1979: 
                   1980:     ret = 0;
1.1.1.7   root     1981:     address = vaddr;
                   1982:     if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
                   1983:         /* IO memory case (romd handled later) */
                   1984:         address |= TLB_MMIO;
                   1985:     }
1.1.1.10  root     1986:     addend = (unsigned long)qemu_get_ram_ptr(pd & TARGET_PAGE_MASK);
1.1.1.7   root     1987:     if ((pd & ~TARGET_PAGE_MASK) <= IO_MEM_ROM) {
                   1988:         /* Normal RAM.  */
                   1989:         iotlb = pd & TARGET_PAGE_MASK;
                   1990:         if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM)
                   1991:             iotlb |= IO_MEM_NOTDIRTY;
                   1992:         else
                   1993:             iotlb |= IO_MEM_ROM;
                   1994:     } else {
1.1.1.10  root     1995:         /* IO handlers are currently passed a physical address.
1.1.1.7   root     1996:            It would be nice to pass an offset from the base address
                   1997:            of that region.  This would avoid having to special case RAM,
                   1998:            and avoid full address decoding in every device.
                   1999:            We can't use the high bits of pd for this because
                   2000:            IO_MEM_ROMD uses these as a ram address.  */
                   2001:         iotlb = (pd & ~TARGET_PAGE_MASK);
                   2002:         if (p) {
                   2003:             iotlb += p->region_offset;
1.1       root     2004:         } else {
1.1.1.7   root     2005:             iotlb += paddr;
1.1       root     2006:         }
1.1.1.7   root     2007:     }
1.1.1.6   root     2008: 
1.1.1.7   root     2009:     code_address = address;
                   2010:     /* Make accesses to pages with watchpoints go via the
                   2011:        watchpoint trap routines.  */
1.1.1.11  root     2012:     QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
1.1.1.7   root     2013:         if (vaddr == (wp->vaddr & TARGET_PAGE_MASK)) {
                   2014:             iotlb = io_mem_watch + paddr;
                   2015:             /* TODO: The memory case can be optimized by not trapping
                   2016:                reads of pages with a write breakpoint.  */
                   2017:             address |= TLB_MMIO;
1.1.1.6   root     2018:         }
1.1.1.7   root     2019:     }
1.1.1.6   root     2020: 
1.1.1.7   root     2021:     index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
                   2022:     env->iotlb[mmu_idx][index] = iotlb - vaddr;
                   2023:     te = &env->tlb_table[mmu_idx][index];
                   2024:     te->addend = addend - vaddr;
                   2025:     if (prot & PAGE_READ) {
                   2026:         te->addr_read = address;
                   2027:     } else {
                   2028:         te->addr_read = -1;
1.1       root     2029:     }
                   2030: 
1.1.1.7   root     2031:     if (prot & PAGE_EXEC) {
                   2032:         te->addr_code = code_address;
                   2033:     } else {
                   2034:         te->addr_code = -1;
                   2035:     }
                   2036:     if (prot & PAGE_WRITE) {
                   2037:         if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_ROM ||
                   2038:             (pd & IO_MEM_ROMD)) {
                   2039:             /* Write access calls the I/O callback.  */
                   2040:             te->addr_write = address | TLB_MMIO;
                   2041:         } else if ((pd & ~TARGET_PAGE_MASK) == IO_MEM_RAM &&
                   2042:                    !cpu_physical_memory_is_dirty(pd)) {
                   2043:             te->addr_write = address | TLB_NOTDIRTY;
                   2044:         } else {
                   2045:             te->addr_write = address;
1.1       root     2046:         }
1.1.1.7   root     2047:     } else {
                   2048:         te->addr_write = -1;
1.1       root     2049:     }
                   2050:     return ret;
                   2051: }
                   2052: 
                   2053: #else
                   2054: 
                   2055: void tlb_flush(CPUState *env, int flush_global)
                   2056: {
                   2057: }
                   2058: 
                   2059: void tlb_flush_page(CPUState *env, target_ulong addr)
                   2060: {
                   2061: }
                   2062: 
1.1.1.6   root     2063: int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
                   2064:                       target_phys_addr_t paddr, int prot,
                   2065:                       int mmu_idx, int is_softmmu)
1.1       root     2066: {
                   2067:     return 0;
                   2068: }
                   2069: 
1.1.1.10  root     2070: /*
                   2071:  * Walks guest process memory "regions" one by one
                   2072:  * and calls callback function 'fn' for each region.
                   2073:  */
                   2074: int walk_memory_regions(void *priv,
                   2075:     int (*fn)(void *, unsigned long, unsigned long, unsigned long))
1.1       root     2076: {
                   2077:     unsigned long start, end;
1.1.1.10  root     2078:     PageDesc *p = NULL;
1.1       root     2079:     int i, j, prot, prot1;
1.1.1.10  root     2080:     int rc = 0;
1.1       root     2081: 
1.1.1.10  root     2082:     start = end = -1;
1.1       root     2083:     prot = 0;
1.1.1.10  root     2084: 
                   2085:     for (i = 0; i <= L1_SIZE; i++) {
                   2086:         p = (i < L1_SIZE) ? l1_map[i] : NULL;
                   2087:         for (j = 0; j < L2_SIZE; j++) {
                   2088:             prot1 = (p == NULL) ? 0 : p[j].flags;
                   2089:             /*
                   2090:              * "region" is one continuous chunk of memory
                   2091:              * that has same protection flags set.
                   2092:              */
1.1       root     2093:             if (prot1 != prot) {
                   2094:                 end = (i << (32 - L1_BITS)) | (j << TARGET_PAGE_BITS);
                   2095:                 if (start != -1) {
1.1.1.10  root     2096:                     rc = (*fn)(priv, start, end, prot);
                   2097:                     /* callback can stop iteration by returning != 0 */
                   2098:                     if (rc != 0)
                   2099:                         return (rc);
1.1       root     2100:                 }
                   2101:                 if (prot1 != 0)
                   2102:                     start = end;
                   2103:                 else
                   2104:                     start = -1;
                   2105:                 prot = prot1;
                   2106:             }
1.1.1.10  root     2107:             if (p == NULL)
1.1       root     2108:                 break;
                   2109:         }
                   2110:     }
1.1.1.10  root     2111:     return (rc);
                   2112: }
                   2113: 
                   2114: static int dump_region(void *priv, unsigned long start,
                   2115:     unsigned long end, unsigned long prot)
                   2116: {
                   2117:     FILE *f = (FILE *)priv;
                   2118: 
                   2119:     (void) fprintf(f, "%08lx-%08lx %08lx %c%c%c\n",
                   2120:         start, end, end - start,
                   2121:         ((prot & PAGE_READ) ? 'r' : '-'),
                   2122:         ((prot & PAGE_WRITE) ? 'w' : '-'),
                   2123:         ((prot & PAGE_EXEC) ? 'x' : '-'));
                   2124: 
                   2125:     return (0);
                   2126: }
                   2127: 
                   2128: /* dump memory mappings */
                   2129: void page_dump(FILE *f)
                   2130: {
                   2131:     (void) fprintf(f, "%-8s %-8s %-8s %s\n",
                   2132:             "start", "end", "size", "prot");
                   2133:     walk_memory_regions(f, dump_region);
1.1       root     2134: }
                   2135: 
1.1.1.3   root     2136: int page_get_flags(target_ulong address)
1.1       root     2137: {
                   2138:     PageDesc *p;
                   2139: 
                   2140:     p = page_find(address >> TARGET_PAGE_BITS);
                   2141:     if (!p)
                   2142:         return 0;
                   2143:     return p->flags;
                   2144: }
                   2145: 
                   2146: /* modify the flags of a page and invalidate the code if
1.1.1.10  root     2147:    necessary. The flag PAGE_WRITE_ORG is positioned automatically
1.1       root     2148:    depending on PAGE_WRITE */
1.1.1.3   root     2149: void page_set_flags(target_ulong start, target_ulong end, int flags)
1.1       root     2150: {
                   2151:     PageDesc *p;
1.1.1.3   root     2152:     target_ulong addr;
1.1       root     2153: 
1.1.1.7   root     2154:     /* mmap_lock should already be held.  */
1.1       root     2155:     start = start & TARGET_PAGE_MASK;
                   2156:     end = TARGET_PAGE_ALIGN(end);
                   2157:     if (flags & PAGE_WRITE)
                   2158:         flags |= PAGE_WRITE_ORG;
                   2159:     for(addr = start; addr < end; addr += TARGET_PAGE_SIZE) {
                   2160:         p = page_find_alloc(addr >> TARGET_PAGE_BITS);
1.1.1.7   root     2161:         /* We may be called for host regions that are outside guest
                   2162:            address space.  */
                   2163:         if (!p)
                   2164:             return;
1.1       root     2165:         /* if the write protection is set, then we invalidate the code
                   2166:            inside */
1.1.1.6   root     2167:         if (!(p->flags & PAGE_WRITE) &&
1.1       root     2168:             (flags & PAGE_WRITE) &&
                   2169:             p->first_tb) {
                   2170:             tb_invalidate_phys_page(addr, 0, NULL);
                   2171:         }
                   2172:         p->flags = flags;
                   2173:     }
                   2174: }
                   2175: 
1.1.1.6   root     2176: int page_check_range(target_ulong start, target_ulong len, int flags)
                   2177: {
                   2178:     PageDesc *p;
                   2179:     target_ulong end;
                   2180:     target_ulong addr;
                   2181: 
1.1.1.7   root     2182:     if (start + len < start)
                   2183:         /* we've wrapped around */
                   2184:         return -1;
                   2185: 
1.1.1.6   root     2186:     end = TARGET_PAGE_ALIGN(start+len); /* must do before we loose bits in the next step */
                   2187:     start = start & TARGET_PAGE_MASK;
                   2188: 
                   2189:     for(addr = start; addr < end; addr += TARGET_PAGE_SIZE) {
                   2190:         p = page_find(addr >> TARGET_PAGE_BITS);
                   2191:         if( !p )
                   2192:             return -1;
                   2193:         if( !(p->flags & PAGE_VALID) )
                   2194:             return -1;
                   2195: 
                   2196:         if ((flags & PAGE_READ) && !(p->flags & PAGE_READ))
                   2197:             return -1;
                   2198:         if (flags & PAGE_WRITE) {
                   2199:             if (!(p->flags & PAGE_WRITE_ORG))
                   2200:                 return -1;
                   2201:             /* unprotect the page if it was put read-only because it
                   2202:                contains translated code */
                   2203:             if (!(p->flags & PAGE_WRITE)) {
                   2204:                 if (!page_unprotect(addr, 0, NULL))
                   2205:                     return -1;
                   2206:             }
                   2207:             return 0;
                   2208:         }
                   2209:     }
                   2210:     return 0;
                   2211: }
                   2212: 
1.1       root     2213: /* called from signal handler: invalidate the code and unprotect the
1.1.1.10  root     2214:    page. Return TRUE if the fault was successfully handled. */
1.1.1.3   root     2215: int page_unprotect(target_ulong address, unsigned long pc, void *puc)
1.1       root     2216: {
                   2217:     unsigned int page_index, prot, pindex;
                   2218:     PageDesc *p, *p1;
1.1.1.3   root     2219:     target_ulong host_start, host_end, addr;
1.1       root     2220: 
1.1.1.7   root     2221:     /* Technically this isn't safe inside a signal handler.  However we
                   2222:        know this only ever happens in a synchronous SEGV handler, so in
                   2223:        practice it seems to be ok.  */
                   2224:     mmap_lock();
                   2225: 
1.1       root     2226:     host_start = address & qemu_host_page_mask;
                   2227:     page_index = host_start >> TARGET_PAGE_BITS;
                   2228:     p1 = page_find(page_index);
1.1.1.7   root     2229:     if (!p1) {
                   2230:         mmap_unlock();
1.1       root     2231:         return 0;
1.1.1.7   root     2232:     }
1.1       root     2233:     host_end = host_start + qemu_host_page_size;
                   2234:     p = p1;
                   2235:     prot = 0;
                   2236:     for(addr = host_start;addr < host_end; addr += TARGET_PAGE_SIZE) {
                   2237:         prot |= p->flags;
                   2238:         p++;
                   2239:     }
                   2240:     /* if the page was really writable, then we change its
                   2241:        protection back to writable */
                   2242:     if (prot & PAGE_WRITE_ORG) {
                   2243:         pindex = (address - host_start) >> TARGET_PAGE_BITS;
                   2244:         if (!(p1[pindex].flags & PAGE_WRITE)) {
1.1.1.6   root     2245:             mprotect((void *)g2h(host_start), qemu_host_page_size,
1.1       root     2246:                      (prot & PAGE_BITS) | PAGE_WRITE);
                   2247:             p1[pindex].flags |= PAGE_WRITE;
                   2248:             /* and since the content will be modified, we must invalidate
                   2249:                the corresponding translated code. */
                   2250:             tb_invalidate_phys_page(address, pc, puc);
                   2251: #ifdef DEBUG_TB_CHECK
                   2252:             tb_invalidate_check(address);
                   2253: #endif
1.1.1.7   root     2254:             mmap_unlock();
1.1       root     2255:             return 1;
                   2256:         }
                   2257:     }
1.1.1.7   root     2258:     mmap_unlock();
1.1       root     2259:     return 0;
                   2260: }
                   2261: 
1.1.1.2   root     2262: static inline void tlb_set_dirty(CPUState *env,
                   2263:                                  unsigned long addr, target_ulong vaddr)
1.1       root     2264: {
                   2265: }
                   2266: #endif /* defined(CONFIG_USER_ONLY) */
                   2267: 
1.1.1.7   root     2268: #if !defined(CONFIG_USER_ONLY)
                   2269: 
1.1.1.6   root     2270: static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
1.1.1.7   root     2271:                              ram_addr_t memory, ram_addr_t region_offset);
                   2272: static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
                   2273:                            ram_addr_t orig_memory, ram_addr_t region_offset);
1.1.1.6   root     2274: #define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \
                   2275:                       need_subpage)                                     \
                   2276:     do {                                                                \
                   2277:         if (addr > start_addr)                                          \
                   2278:             start_addr2 = 0;                                            \
                   2279:         else {                                                          \
                   2280:             start_addr2 = start_addr & ~TARGET_PAGE_MASK;               \
                   2281:             if (start_addr2 > 0)                                        \
                   2282:                 need_subpage = 1;                                       \
                   2283:         }                                                               \
                   2284:                                                                         \
                   2285:         if ((start_addr + orig_size) - addr >= TARGET_PAGE_SIZE)        \
                   2286:             end_addr2 = TARGET_PAGE_SIZE - 1;                           \
                   2287:         else {                                                          \
                   2288:             end_addr2 = (start_addr + orig_size - 1) & ~TARGET_PAGE_MASK; \
                   2289:             if (end_addr2 < TARGET_PAGE_SIZE - 1)                       \
                   2290:                 need_subpage = 1;                                       \
                   2291:         }                                                               \
                   2292:     } while (0)
                   2293: 
1.1.1.11  root     2294: /* register physical memory.
                   2295:    For RAM, 'size' must be a multiple of the target page size.
                   2296:    If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an
1.1.1.7   root     2297:    io memory page.  The address used when calling the IO function is
                   2298:    the offset from the start of the region, plus region_offset.  Both
1.1.1.10  root     2299:    start_addr and region_offset are rounded down to a page boundary
1.1.1.7   root     2300:    before calculating this offset.  This should not be a problem unless
                   2301:    the low bits of start_addr and region_offset differ.  */
                   2302: void cpu_register_physical_memory_offset(target_phys_addr_t start_addr,
                   2303:                                          ram_addr_t size,
                   2304:                                          ram_addr_t phys_offset,
                   2305:                                          ram_addr_t region_offset)
1.1       root     2306: {
                   2307:     target_phys_addr_t addr, end_addr;
                   2308:     PhysPageDesc *p;
1.1.1.4   root     2309:     CPUState *env;
1.1.1.7   root     2310:     ram_addr_t orig_size = size;
1.1.1.6   root     2311:     void *subpage;
1.1       root     2312: 
1.1.1.7   root     2313:     if (kvm_enabled())
                   2314:         kvm_set_phys_mem(start_addr, size, phys_offset);
                   2315: 
                   2316:     if (phys_offset == IO_MEM_UNASSIGNED) {
                   2317:         region_offset = start_addr;
                   2318:     }
                   2319:     region_offset &= TARGET_PAGE_MASK;
1.1       root     2320:     size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
1.1.1.6   root     2321:     end_addr = start_addr + (target_phys_addr_t)size;
1.1       root     2322:     for(addr = start_addr; addr != end_addr; addr += TARGET_PAGE_SIZE) {
1.1.1.6   root     2323:         p = phys_page_find(addr >> TARGET_PAGE_BITS);
                   2324:         if (p && p->phys_offset != IO_MEM_UNASSIGNED) {
1.1.1.7   root     2325:             ram_addr_t orig_memory = p->phys_offset;
1.1.1.6   root     2326:             target_phys_addr_t start_addr2, end_addr2;
                   2327:             int need_subpage = 0;
                   2328: 
                   2329:             CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2,
                   2330:                           need_subpage);
                   2331:             if (need_subpage || phys_offset & IO_MEM_SUBWIDTH) {
                   2332:                 if (!(orig_memory & IO_MEM_SUBPAGE)) {
                   2333:                     subpage = subpage_init((addr & TARGET_PAGE_MASK),
1.1.1.7   root     2334:                                            &p->phys_offset, orig_memory,
                   2335:                                            p->region_offset);
1.1.1.6   root     2336:                 } else {
                   2337:                     subpage = io_mem_opaque[(orig_memory & ~TARGET_PAGE_MASK)
                   2338:                                             >> IO_MEM_SHIFT];
                   2339:                 }
1.1.1.7   root     2340:                 subpage_register(subpage, start_addr2, end_addr2, phys_offset,
                   2341:                                  region_offset);
                   2342:                 p->region_offset = 0;
1.1.1.6   root     2343:             } else {
                   2344:                 p->phys_offset = phys_offset;
                   2345:                 if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM ||
                   2346:                     (phys_offset & IO_MEM_ROMD))
                   2347:                     phys_offset += TARGET_PAGE_SIZE;
                   2348:             }
                   2349:         } else {
                   2350:             p = phys_page_find_alloc(addr >> TARGET_PAGE_BITS, 1);
                   2351:             p->phys_offset = phys_offset;
1.1.1.7   root     2352:             p->region_offset = region_offset;
1.1.1.6   root     2353:             if ((phys_offset & ~TARGET_PAGE_MASK) <= IO_MEM_ROM ||
1.1.1.7   root     2354:                 (phys_offset & IO_MEM_ROMD)) {
1.1.1.6   root     2355:                 phys_offset += TARGET_PAGE_SIZE;
1.1.1.7   root     2356:             } else {
1.1.1.6   root     2357:                 target_phys_addr_t start_addr2, end_addr2;
                   2358:                 int need_subpage = 0;
                   2359: 
                   2360:                 CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr,
                   2361:                               end_addr2, need_subpage);
                   2362: 
                   2363:                 if (need_subpage || phys_offset & IO_MEM_SUBWIDTH) {
                   2364:                     subpage = subpage_init((addr & TARGET_PAGE_MASK),
1.1.1.7   root     2365:                                            &p->phys_offset, IO_MEM_UNASSIGNED,
                   2366:                                            addr & TARGET_PAGE_MASK);
1.1.1.6   root     2367:                     subpage_register(subpage, start_addr2, end_addr2,
1.1.1.7   root     2368:                                      phys_offset, region_offset);
                   2369:                     p->region_offset = 0;
1.1.1.6   root     2370:                 }
                   2371:             }
                   2372:         }
1.1.1.7   root     2373:         region_offset += TARGET_PAGE_SIZE;
1.1       root     2374:     }
1.1.1.6   root     2375: 
1.1.1.4   root     2376:     /* since each CPU stores ram addresses in its TLB cache, we must
                   2377:        reset the modified entries */
                   2378:     /* XXX: slow ! */
                   2379:     for(env = first_cpu; env != NULL; env = env->next_cpu) {
                   2380:         tlb_flush(env, 1);
                   2381:     }
1.1       root     2382: }
                   2383: 
1.1.1.5   root     2384: /* XXX: temporary until new memory mapping API */
1.1.1.7   root     2385: ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr)
1.1.1.5   root     2386: {
                   2387:     PhysPageDesc *p;
                   2388: 
                   2389:     p = phys_page_find(addr >> TARGET_PAGE_BITS);
                   2390:     if (!p)
                   2391:         return IO_MEM_UNASSIGNED;
                   2392:     return p->phys_offset;
                   2393: }
                   2394: 
1.1.1.7   root     2395: void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size)
                   2396: {
                   2397:     if (kvm_enabled())
                   2398:         kvm_coalesce_mmio_region(addr, size);
                   2399: }
                   2400: 
                   2401: void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size)
                   2402: {
                   2403:     if (kvm_enabled())
                   2404:         kvm_uncoalesce_mmio_region(addr, size);
                   2405: }
                   2406: 
1.1.1.10  root     2407: ram_addr_t qemu_ram_alloc(ram_addr_t size)
                   2408: {
                   2409:     RAMBlock *new_block;
                   2410: 
                   2411:     size = TARGET_PAGE_ALIGN(size);
                   2412:     new_block = qemu_malloc(sizeof(*new_block));
                   2413: 
1.1.1.11  root     2414: #if defined(TARGET_S390X) && defined(CONFIG_KVM)
                   2415:     /* XXX S390 KVM requires the topmost vma of the RAM to be < 256GB */
                   2416:     new_block->host = mmap((void*)0x1000000, size, PROT_EXEC|PROT_READ|PROT_WRITE,
                   2417:                            MAP_SHARED | MAP_ANONYMOUS, -1, 0);
                   2418: #else
1.1.1.10  root     2419:     new_block->host = qemu_vmalloc(size);
1.1.1.11  root     2420: #endif
                   2421: #ifdef MADV_MERGEABLE
                   2422:     madvise(new_block->host, size, MADV_MERGEABLE);
                   2423: #endif
1.1.1.10  root     2424:     new_block->offset = last_ram_offset;
                   2425:     new_block->length = size;
                   2426: 
                   2427:     new_block->next = ram_blocks;
                   2428:     ram_blocks = new_block;
                   2429: 
                   2430:     phys_ram_dirty = qemu_realloc(phys_ram_dirty,
                   2431:         (last_ram_offset + size) >> TARGET_PAGE_BITS);
                   2432:     memset(phys_ram_dirty + (last_ram_offset >> TARGET_PAGE_BITS),
                   2433:            0xff, size >> TARGET_PAGE_BITS);
                   2434: 
                   2435:     last_ram_offset += size;
1.1.1.9   root     2436: 
                   2437:     if (kvm_enabled())
1.1.1.10  root     2438:         kvm_setup_guest_memory(new_block->host, size);
1.1.1.9   root     2439: 
1.1.1.10  root     2440:     return new_block->offset;
1.1.1.6   root     2441: }
                   2442: 
                   2443: void qemu_ram_free(ram_addr_t addr)
                   2444: {
1.1.1.10  root     2445:     /* TODO: implement this.  */
                   2446: }
                   2447: 
                   2448: /* Return a host pointer to ram allocated with qemu_ram_alloc.
                   2449:    With the exception of the softmmu code in this file, this should
                   2450:    only be used for local memory (e.g. video ram) that the device owns,
                   2451:    and knows it isn't going to access beyond the end of the block.
                   2452: 
                   2453:    It should not be used for general purpose DMA.
                   2454:    Use cpu_physical_memory_map/cpu_physical_memory_rw instead.
                   2455:  */
                   2456: void *qemu_get_ram_ptr(ram_addr_t addr)
                   2457: {
                   2458:     RAMBlock *prev;
                   2459:     RAMBlock **prevp;
                   2460:     RAMBlock *block;
                   2461: 
                   2462:     prev = NULL;
                   2463:     prevp = &ram_blocks;
                   2464:     block = ram_blocks;
                   2465:     while (block && (block->offset > addr
                   2466:                      || block->offset + block->length <= addr)) {
                   2467:         if (prev)
                   2468:           prevp = &prev->next;
                   2469:         prev = block;
                   2470:         block = block->next;
                   2471:     }
                   2472:     if (!block) {
                   2473:         fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr);
                   2474:         abort();
                   2475:     }
                   2476:     /* Move this entry to to start of the list.  */
                   2477:     if (prev) {
                   2478:         prev->next = block->next;
                   2479:         block->next = *prevp;
                   2480:         *prevp = block;
                   2481:     }
                   2482:     return block->host + (addr - block->offset);
                   2483: }
                   2484: 
                   2485: /* Some of the softmmu routines need to translate from a host pointer
                   2486:    (typically a TLB entry) back to a ram offset.  */
                   2487: ram_addr_t qemu_ram_addr_from_host(void *ptr)
                   2488: {
                   2489:     RAMBlock *prev;
                   2490:     RAMBlock **prevp;
                   2491:     RAMBlock *block;
                   2492:     uint8_t *host = ptr;
                   2493: 
                   2494:     prev = NULL;
                   2495:     prevp = &ram_blocks;
                   2496:     block = ram_blocks;
                   2497:     while (block && (block->host > host
                   2498:                      || block->host + block->length <= host)) {
                   2499:         if (prev)
                   2500:           prevp = &prev->next;
                   2501:         prev = block;
                   2502:         block = block->next;
                   2503:     }
                   2504:     if (!block) {
                   2505:         fprintf(stderr, "Bad ram pointer %p\n", ptr);
                   2506:         abort();
                   2507:     }
                   2508:     return block->offset + (host - block->host);
1.1.1.6   root     2509: }
                   2510: 
1.1       root     2511: static uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr)
                   2512: {
1.1.1.5   root     2513: #ifdef DEBUG_UNASSIGNED
1.1.1.6   root     2514:     printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
                   2515: #endif
1.1.1.11  root     2516: #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE)
1.1.1.7   root     2517:     do_unassigned_access(addr, 0, 0, 0, 1);
                   2518: #endif
                   2519:     return 0;
                   2520: }
                   2521: 
                   2522: static uint32_t unassigned_mem_readw(void *opaque, target_phys_addr_t addr)
                   2523: {
                   2524: #ifdef DEBUG_UNASSIGNED
                   2525:     printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
                   2526: #endif
1.1.1.11  root     2527: #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE)
1.1.1.7   root     2528:     do_unassigned_access(addr, 0, 0, 0, 2);
                   2529: #endif
                   2530:     return 0;
                   2531: }
                   2532: 
                   2533: static uint32_t unassigned_mem_readl(void *opaque, target_phys_addr_t addr)
                   2534: {
                   2535: #ifdef DEBUG_UNASSIGNED
                   2536:     printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
                   2537: #endif
1.1.1.11  root     2538: #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE)
1.1.1.7   root     2539:     do_unassigned_access(addr, 0, 0, 0, 4);
1.1.1.5   root     2540: #endif
1.1       root     2541:     return 0;
                   2542: }
                   2543: 
                   2544: static void unassigned_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
                   2545: {
1.1.1.5   root     2546: #ifdef DEBUG_UNASSIGNED
1.1.1.6   root     2547:     printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
                   2548: #endif
1.1.1.11  root     2549: #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE)
1.1.1.7   root     2550:     do_unassigned_access(addr, 1, 0, 0, 1);
                   2551: #endif
                   2552: }
                   2553: 
                   2554: static void unassigned_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
                   2555: {
                   2556: #ifdef DEBUG_UNASSIGNED
                   2557:     printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
                   2558: #endif
1.1.1.11  root     2559: #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE)
1.1.1.7   root     2560:     do_unassigned_access(addr, 1, 0, 0, 2);
                   2561: #endif
                   2562: }
                   2563: 
                   2564: static void unassigned_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
                   2565: {
                   2566: #ifdef DEBUG_UNASSIGNED
                   2567:     printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
                   2568: #endif
1.1.1.11  root     2569: #if defined(TARGET_SPARC) || defined(TARGET_MICROBLAZE)
1.1.1.7   root     2570:     do_unassigned_access(addr, 1, 0, 0, 4);
1.1.1.5   root     2571: #endif
1.1       root     2572: }
                   2573: 
1.1.1.11  root     2574: static CPUReadMemoryFunc * const unassigned_mem_read[3] = {
1.1       root     2575:     unassigned_mem_readb,
1.1.1.7   root     2576:     unassigned_mem_readw,
                   2577:     unassigned_mem_readl,
1.1       root     2578: };
                   2579: 
1.1.1.11  root     2580: static CPUWriteMemoryFunc * const unassigned_mem_write[3] = {
1.1       root     2581:     unassigned_mem_writeb,
1.1.1.7   root     2582:     unassigned_mem_writew,
                   2583:     unassigned_mem_writel,
1.1       root     2584: };
                   2585: 
1.1.1.7   root     2586: static void notdirty_mem_writeb(void *opaque, target_phys_addr_t ram_addr,
                   2587:                                 uint32_t val)
1.1       root     2588: {
                   2589:     int dirty_flags;
                   2590:     dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
                   2591:     if (!(dirty_flags & CODE_DIRTY_FLAG)) {
                   2592: #if !defined(CONFIG_USER_ONLY)
                   2593:         tb_invalidate_phys_page_fast(ram_addr, 1);
                   2594:         dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
                   2595: #endif
                   2596:     }
1.1.1.10  root     2597:     stb_p(qemu_get_ram_ptr(ram_addr), val);
1.1       root     2598:     dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
                   2599:     phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags;
                   2600:     /* we remove the notdirty callback only if the code has been
                   2601:        flushed */
                   2602:     if (dirty_flags == 0xff)
1.1.1.7   root     2603:         tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
1.1       root     2604: }
                   2605: 
1.1.1.7   root     2606: static void notdirty_mem_writew(void *opaque, target_phys_addr_t ram_addr,
                   2607:                                 uint32_t val)
1.1       root     2608: {
                   2609:     int dirty_flags;
                   2610:     dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
                   2611:     if (!(dirty_flags & CODE_DIRTY_FLAG)) {
                   2612: #if !defined(CONFIG_USER_ONLY)
                   2613:         tb_invalidate_phys_page_fast(ram_addr, 2);
                   2614:         dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
                   2615: #endif
                   2616:     }
1.1.1.10  root     2617:     stw_p(qemu_get_ram_ptr(ram_addr), val);
1.1       root     2618:     dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
                   2619:     phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags;
                   2620:     /* we remove the notdirty callback only if the code has been
                   2621:        flushed */
                   2622:     if (dirty_flags == 0xff)
1.1.1.7   root     2623:         tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
1.1       root     2624: }
                   2625: 
1.1.1.7   root     2626: static void notdirty_mem_writel(void *opaque, target_phys_addr_t ram_addr,
                   2627:                                 uint32_t val)
1.1       root     2628: {
                   2629:     int dirty_flags;
                   2630:     dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
                   2631:     if (!(dirty_flags & CODE_DIRTY_FLAG)) {
                   2632: #if !defined(CONFIG_USER_ONLY)
                   2633:         tb_invalidate_phys_page_fast(ram_addr, 4);
                   2634:         dirty_flags = phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS];
                   2635: #endif
                   2636:     }
1.1.1.10  root     2637:     stl_p(qemu_get_ram_ptr(ram_addr), val);
1.1       root     2638:     dirty_flags |= (0xff & ~CODE_DIRTY_FLAG);
                   2639:     phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] = dirty_flags;
                   2640:     /* we remove the notdirty callback only if the code has been
                   2641:        flushed */
                   2642:     if (dirty_flags == 0xff)
1.1.1.7   root     2643:         tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
1.1       root     2644: }
                   2645: 
1.1.1.11  root     2646: static CPUReadMemoryFunc * const error_mem_read[3] = {
1.1       root     2647:     NULL, /* never used */
                   2648:     NULL, /* never used */
                   2649:     NULL, /* never used */
                   2650: };
                   2651: 
1.1.1.11  root     2652: static CPUWriteMemoryFunc * const notdirty_mem_write[3] = {
1.1       root     2653:     notdirty_mem_writeb,
                   2654:     notdirty_mem_writew,
                   2655:     notdirty_mem_writel,
                   2656: };
                   2657: 
1.1.1.7   root     2658: /* Generate a debug exception if a watchpoint has been hit.  */
                   2659: static void check_watchpoint(int offset, int len_mask, int flags)
                   2660: {
                   2661:     CPUState *env = cpu_single_env;
                   2662:     target_ulong pc, cs_base;
                   2663:     TranslationBlock *tb;
                   2664:     target_ulong vaddr;
                   2665:     CPUWatchpoint *wp;
                   2666:     int cpu_flags;
                   2667: 
                   2668:     if (env->watchpoint_hit) {
                   2669:         /* We re-entered the check after replacing the TB. Now raise
                   2670:          * the debug interrupt so that is will trigger after the
                   2671:          * current instruction. */
                   2672:         cpu_interrupt(env, CPU_INTERRUPT_DEBUG);
                   2673:         return;
                   2674:     }
                   2675:     vaddr = (env->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
1.1.1.11  root     2676:     QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
1.1.1.7   root     2677:         if ((vaddr == (wp->vaddr & len_mask) ||
                   2678:              (vaddr & wp->len_mask) == wp->vaddr) && (wp->flags & flags)) {
                   2679:             wp->flags |= BP_WATCHPOINT_HIT;
                   2680:             if (!env->watchpoint_hit) {
                   2681:                 env->watchpoint_hit = wp;
                   2682:                 tb = tb_find_pc(env->mem_io_pc);
                   2683:                 if (!tb) {
                   2684:                     cpu_abort(env, "check_watchpoint: could not find TB for "
                   2685:                               "pc=%p", (void *)env->mem_io_pc);
                   2686:                 }
                   2687:                 cpu_restore_state(tb, env, env->mem_io_pc, NULL);
                   2688:                 tb_phys_invalidate(tb, -1);
                   2689:                 if (wp->flags & BP_STOP_BEFORE_ACCESS) {
                   2690:                     env->exception_index = EXCP_DEBUG;
                   2691:                 } else {
                   2692:                     cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags);
                   2693:                     tb_gen_code(env, pc, cs_base, cpu_flags, 1);
                   2694:                 }
                   2695:                 cpu_resume_from_signal(env, NULL);
                   2696:             }
                   2697:         } else {
                   2698:             wp->flags &= ~BP_WATCHPOINT_HIT;
                   2699:         }
                   2700:     }
                   2701: }
                   2702: 
1.1.1.6   root     2703: /* Watchpoint access routines.  Watchpoints are inserted using TLB tricks,
                   2704:    so these check for a hit then pass through to the normal out-of-line
                   2705:    phys routines.  */
                   2706: static uint32_t watch_mem_readb(void *opaque, target_phys_addr_t addr)
                   2707: {
1.1.1.7   root     2708:     check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_READ);
1.1.1.6   root     2709:     return ldub_phys(addr);
                   2710: }
                   2711: 
                   2712: static uint32_t watch_mem_readw(void *opaque, target_phys_addr_t addr)
                   2713: {
1.1.1.7   root     2714:     check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_READ);
1.1.1.6   root     2715:     return lduw_phys(addr);
                   2716: }
                   2717: 
                   2718: static uint32_t watch_mem_readl(void *opaque, target_phys_addr_t addr)
                   2719: {
1.1.1.7   root     2720:     check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_READ);
1.1.1.6   root     2721:     return ldl_phys(addr);
                   2722: }
                   2723: 
                   2724: static void watch_mem_writeb(void *opaque, target_phys_addr_t addr,
                   2725:                              uint32_t val)
                   2726: {
1.1.1.7   root     2727:     check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_WRITE);
1.1.1.6   root     2728:     stb_phys(addr, val);
                   2729: }
                   2730: 
                   2731: static void watch_mem_writew(void *opaque, target_phys_addr_t addr,
                   2732:                              uint32_t val)
                   2733: {
1.1.1.7   root     2734:     check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_WRITE);
1.1.1.6   root     2735:     stw_phys(addr, val);
                   2736: }
                   2737: 
                   2738: static void watch_mem_writel(void *opaque, target_phys_addr_t addr,
                   2739:                              uint32_t val)
                   2740: {
1.1.1.7   root     2741:     check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_WRITE);
1.1.1.6   root     2742:     stl_phys(addr, val);
                   2743: }
                   2744: 
1.1.1.11  root     2745: static CPUReadMemoryFunc * const watch_mem_read[3] = {
1.1.1.6   root     2746:     watch_mem_readb,
                   2747:     watch_mem_readw,
                   2748:     watch_mem_readl,
                   2749: };
                   2750: 
1.1.1.11  root     2751: static CPUWriteMemoryFunc * const watch_mem_write[3] = {
1.1.1.6   root     2752:     watch_mem_writeb,
                   2753:     watch_mem_writew,
                   2754:     watch_mem_writel,
                   2755: };
                   2756: 
                   2757: static inline uint32_t subpage_readlen (subpage_t *mmio, target_phys_addr_t addr,
                   2758:                                  unsigned int len)
                   2759: {
                   2760:     uint32_t ret;
                   2761:     unsigned int idx;
                   2762: 
1.1.1.7   root     2763:     idx = SUBPAGE_IDX(addr);
1.1.1.6   root     2764: #if defined(DEBUG_SUBPAGE)
                   2765:     printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d\n", __func__,
                   2766:            mmio, len, addr, idx);
                   2767: #endif
1.1.1.7   root     2768:     ret = (**mmio->mem_read[idx][len])(mmio->opaque[idx][0][len],
                   2769:                                        addr + mmio->region_offset[idx][0][len]);
1.1.1.6   root     2770: 
                   2771:     return ret;
                   2772: }
                   2773: 
                   2774: static inline void subpage_writelen (subpage_t *mmio, target_phys_addr_t addr,
                   2775:                               uint32_t value, unsigned int len)
                   2776: {
                   2777:     unsigned int idx;
                   2778: 
1.1.1.7   root     2779:     idx = SUBPAGE_IDX(addr);
1.1.1.6   root     2780: #if defined(DEBUG_SUBPAGE)
                   2781:     printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d value %08x\n", __func__,
                   2782:            mmio, len, addr, idx, value);
                   2783: #endif
1.1.1.7   root     2784:     (**mmio->mem_write[idx][len])(mmio->opaque[idx][1][len],
                   2785:                                   addr + mmio->region_offset[idx][1][len],
                   2786:                                   value);
1.1.1.6   root     2787: }
                   2788: 
                   2789: static uint32_t subpage_readb (void *opaque, target_phys_addr_t addr)
                   2790: {
                   2791: #if defined(DEBUG_SUBPAGE)
                   2792:     printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
                   2793: #endif
                   2794: 
                   2795:     return subpage_readlen(opaque, addr, 0);
                   2796: }
                   2797: 
                   2798: static void subpage_writeb (void *opaque, target_phys_addr_t addr,
                   2799:                             uint32_t value)
                   2800: {
                   2801: #if defined(DEBUG_SUBPAGE)
                   2802:     printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value);
                   2803: #endif
                   2804:     subpage_writelen(opaque, addr, value, 0);
                   2805: }
                   2806: 
                   2807: static uint32_t subpage_readw (void *opaque, target_phys_addr_t addr)
                   2808: {
                   2809: #if defined(DEBUG_SUBPAGE)
                   2810:     printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
                   2811: #endif
                   2812: 
                   2813:     return subpage_readlen(opaque, addr, 1);
                   2814: }
                   2815: 
                   2816: static void subpage_writew (void *opaque, target_phys_addr_t addr,
                   2817:                             uint32_t value)
                   2818: {
                   2819: #if defined(DEBUG_SUBPAGE)
                   2820:     printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value);
                   2821: #endif
                   2822:     subpage_writelen(opaque, addr, value, 1);
                   2823: }
                   2824: 
                   2825: static uint32_t subpage_readl (void *opaque, target_phys_addr_t addr)
                   2826: {
                   2827: #if defined(DEBUG_SUBPAGE)
                   2828:     printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
                   2829: #endif
                   2830: 
                   2831:     return subpage_readlen(opaque, addr, 2);
                   2832: }
                   2833: 
                   2834: static void subpage_writel (void *opaque,
                   2835:                          target_phys_addr_t addr, uint32_t value)
                   2836: {
                   2837: #if defined(DEBUG_SUBPAGE)
                   2838:     printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value);
                   2839: #endif
                   2840:     subpage_writelen(opaque, addr, value, 2);
                   2841: }
                   2842: 
1.1.1.11  root     2843: static CPUReadMemoryFunc * const subpage_read[] = {
1.1.1.6   root     2844:     &subpage_readb,
                   2845:     &subpage_readw,
                   2846:     &subpage_readl,
                   2847: };
                   2848: 
1.1.1.11  root     2849: static CPUWriteMemoryFunc * const subpage_write[] = {
1.1.1.6   root     2850:     &subpage_writeb,
                   2851:     &subpage_writew,
                   2852:     &subpage_writel,
                   2853: };
                   2854: 
                   2855: static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
1.1.1.7   root     2856:                              ram_addr_t memory, ram_addr_t region_offset)
1.1.1.6   root     2857: {
                   2858:     int idx, eidx;
                   2859:     unsigned int i;
                   2860: 
                   2861:     if (start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE)
                   2862:         return -1;
                   2863:     idx = SUBPAGE_IDX(start);
                   2864:     eidx = SUBPAGE_IDX(end);
                   2865: #if defined(DEBUG_SUBPAGE)
1.1.1.10  root     2866:     printf("%s: %p start %08x end %08x idx %08x eidx %08x mem %ld\n", __func__,
1.1.1.6   root     2867:            mmio, start, end, idx, eidx, memory);
                   2868: #endif
                   2869:     memory >>= IO_MEM_SHIFT;
                   2870:     for (; idx <= eidx; idx++) {
                   2871:         for (i = 0; i < 4; i++) {
                   2872:             if (io_mem_read[memory][i]) {
                   2873:                 mmio->mem_read[idx][i] = &io_mem_read[memory][i];
                   2874:                 mmio->opaque[idx][0][i] = io_mem_opaque[memory];
1.1.1.7   root     2875:                 mmio->region_offset[idx][0][i] = region_offset;
1.1.1.6   root     2876:             }
                   2877:             if (io_mem_write[memory][i]) {
                   2878:                 mmio->mem_write[idx][i] = &io_mem_write[memory][i];
                   2879:                 mmio->opaque[idx][1][i] = io_mem_opaque[memory];
1.1.1.7   root     2880:                 mmio->region_offset[idx][1][i] = region_offset;
1.1.1.6   root     2881:             }
                   2882:         }
                   2883:     }
                   2884: 
                   2885:     return 0;
                   2886: }
                   2887: 
1.1.1.7   root     2888: static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
                   2889:                            ram_addr_t orig_memory, ram_addr_t region_offset)
1.1.1.6   root     2890: {
                   2891:     subpage_t *mmio;
                   2892:     int subpage_memory;
                   2893: 
                   2894:     mmio = qemu_mallocz(sizeof(subpage_t));
1.1.1.7   root     2895: 
                   2896:     mmio->base = base;
1.1.1.10  root     2897:     subpage_memory = cpu_register_io_memory(subpage_read, subpage_write, mmio);
1.1.1.6   root     2898: #if defined(DEBUG_SUBPAGE)
1.1.1.7   root     2899:     printf("%s: %p base " TARGET_FMT_plx " len %08x %d\n", __func__,
                   2900:            mmio, base, TARGET_PAGE_SIZE, subpage_memory);
1.1.1.6   root     2901: #endif
1.1.1.7   root     2902:     *phys = subpage_memory | IO_MEM_SUBPAGE;
                   2903:     subpage_register(mmio, 0, TARGET_PAGE_SIZE - 1, orig_memory,
                   2904:                          region_offset);
1.1.1.6   root     2905: 
                   2906:     return mmio;
                   2907: }
                   2908: 
1.1.1.7   root     2909: static int get_free_io_mem_idx(void)
                   2910: {
                   2911:     int i;
                   2912: 
                   2913:     for (i = 0; i<IO_MEM_NB_ENTRIES; i++)
                   2914:         if (!io_mem_used[i]) {
                   2915:             io_mem_used[i] = 1;
                   2916:             return i;
                   2917:         }
                   2918: 
                   2919:     return -1;
                   2920: }
                   2921: 
1.1       root     2922: /* mem_read and mem_write are arrays of functions containing the
                   2923:    function to access byte (index 0), word (index 1) and dword (index
1.1.1.10  root     2924:    2). Functions can be omitted with a NULL function pointer.
1.1.1.6   root     2925:    If io_index is non zero, the corresponding io zone is
                   2926:    modified. If it is zero, a new io zone is allocated. The return
                   2927:    value can be used with cpu_register_physical_memory(). (-1) is
                   2928:    returned if error. */
1.1.1.10  root     2929: static int cpu_register_io_memory_fixed(int io_index,
1.1.1.11  root     2930:                                         CPUReadMemoryFunc * const *mem_read,
                   2931:                                         CPUWriteMemoryFunc * const *mem_write,
1.1.1.10  root     2932:                                         void *opaque)
1.1       root     2933: {
1.1.1.6   root     2934:     int i, subwidth = 0;
1.1       root     2935: 
                   2936:     if (io_index <= 0) {
1.1.1.7   root     2937:         io_index = get_free_io_mem_idx();
                   2938:         if (io_index == -1)
                   2939:             return io_index;
1.1       root     2940:     } else {
1.1.1.10  root     2941:         io_index >>= IO_MEM_SHIFT;
1.1       root     2942:         if (io_index >= IO_MEM_NB_ENTRIES)
                   2943:             return -1;
                   2944:     }
1.1.1.2   root     2945: 
1.1       root     2946:     for(i = 0;i < 3; i++) {
1.1.1.6   root     2947:         if (!mem_read[i] || !mem_write[i])
                   2948:             subwidth = IO_MEM_SUBWIDTH;
1.1       root     2949:         io_mem_read[io_index][i] = mem_read[i];
                   2950:         io_mem_write[io_index][i] = mem_write[i];
                   2951:     }
                   2952:     io_mem_opaque[io_index] = opaque;
1.1.1.6   root     2953:     return (io_index << IO_MEM_SHIFT) | subwidth;
1.1       root     2954: }
                   2955: 
1.1.1.11  root     2956: int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read,
                   2957:                            CPUWriteMemoryFunc * const *mem_write,
1.1.1.10  root     2958:                            void *opaque)
                   2959: {
                   2960:     return cpu_register_io_memory_fixed(0, mem_read, mem_write, opaque);
                   2961: }
                   2962: 
1.1.1.7   root     2963: void cpu_unregister_io_memory(int io_table_address)
                   2964: {
                   2965:     int i;
                   2966:     int io_index = io_table_address >> IO_MEM_SHIFT;
                   2967: 
                   2968:     for (i=0;i < 3; i++) {
                   2969:         io_mem_read[io_index][i] = unassigned_mem_read[i];
                   2970:         io_mem_write[io_index][i] = unassigned_mem_write[i];
                   2971:     }
                   2972:     io_mem_opaque[io_index] = NULL;
                   2973:     io_mem_used[io_index] = 0;
                   2974: }
                   2975: 
1.1.1.10  root     2976: static void io_mem_init(void)
1.1       root     2977: {
1.1.1.10  root     2978:     int i;
1.1       root     2979: 
1.1.1.10  root     2980:     cpu_register_io_memory_fixed(IO_MEM_ROM, error_mem_read, unassigned_mem_write, NULL);
                   2981:     cpu_register_io_memory_fixed(IO_MEM_UNASSIGNED, unassigned_mem_read, unassigned_mem_write, NULL);
                   2982:     cpu_register_io_memory_fixed(IO_MEM_NOTDIRTY, error_mem_read, notdirty_mem_write, NULL);
                   2983:     for (i=0; i<5; i++)
                   2984:         io_mem_used[i] = 1;
                   2985: 
                   2986:     io_mem_watch = cpu_register_io_memory(watch_mem_read,
                   2987:                                           watch_mem_write, NULL);
1.1       root     2988: }
                   2989: 
1.1.1.7   root     2990: #endif /* !defined(CONFIG_USER_ONLY) */
                   2991: 
1.1       root     2992: /* physical memory access (slow version, mainly for debug) */
                   2993: #if defined(CONFIG_USER_ONLY)
1.1.1.6   root     2994: void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
1.1       root     2995:                             int len, int is_write)
                   2996: {
                   2997:     int l, flags;
                   2998:     target_ulong page;
1.1.1.3   root     2999:     void * p;
1.1       root     3000: 
                   3001:     while (len > 0) {
                   3002:         page = addr & TARGET_PAGE_MASK;
                   3003:         l = (page + TARGET_PAGE_SIZE) - addr;
                   3004:         if (l > len)
                   3005:             l = len;
                   3006:         flags = page_get_flags(page);
                   3007:         if (!(flags & PAGE_VALID))
                   3008:             return;
                   3009:         if (is_write) {
                   3010:             if (!(flags & PAGE_WRITE))
                   3011:                 return;
1.1.1.6   root     3012:             /* XXX: this code should not depend on lock_user */
1.1.1.7   root     3013:             if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
1.1.1.6   root     3014:                 /* FIXME - should this return an error rather than just fail? */
                   3015:                 return;
1.1.1.7   root     3016:             memcpy(p, buf, l);
                   3017:             unlock_user(p, addr, l);
1.1       root     3018:         } else {
                   3019:             if (!(flags & PAGE_READ))
                   3020:                 return;
1.1.1.6   root     3021:             /* XXX: this code should not depend on lock_user */
1.1.1.7   root     3022:             if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
1.1.1.6   root     3023:                 /* FIXME - should this return an error rather than just fail? */
                   3024:                 return;
1.1.1.7   root     3025:             memcpy(buf, p, l);
1.1.1.3   root     3026:             unlock_user(p, addr, 0);
1.1       root     3027:         }
                   3028:         len -= l;
                   3029:         buf += l;
                   3030:         addr += l;
                   3031:     }
                   3032: }
                   3033: 
                   3034: #else
1.1.1.6   root     3035: void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
1.1       root     3036:                             int len, int is_write)
                   3037: {
                   3038:     int l, io_index;
                   3039:     uint8_t *ptr;
                   3040:     uint32_t val;
                   3041:     target_phys_addr_t page;
                   3042:     unsigned long pd;
                   3043:     PhysPageDesc *p;
1.1.1.6   root     3044: 
1.1       root     3045:     while (len > 0) {
                   3046:         page = addr & TARGET_PAGE_MASK;
                   3047:         l = (page + TARGET_PAGE_SIZE) - addr;
                   3048:         if (l > len)
                   3049:             l = len;
                   3050:         p = phys_page_find(page >> TARGET_PAGE_BITS);
                   3051:         if (!p) {
                   3052:             pd = IO_MEM_UNASSIGNED;
                   3053:         } else {
                   3054:             pd = p->phys_offset;
                   3055:         }
1.1.1.6   root     3056: 
1.1       root     3057:         if (is_write) {
                   3058:             if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
1.1.1.7   root     3059:                 target_phys_addr_t addr1 = addr;
1.1       root     3060:                 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
1.1.1.7   root     3061:                 if (p)
                   3062:                     addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
1.1.1.2   root     3063:                 /* XXX: could force cpu_single_env to NULL to avoid
                   3064:                    potential bugs */
1.1.1.7   root     3065:                 if (l >= 4 && ((addr1 & 3) == 0)) {
1.1       root     3066:                     /* 32 bit write access */
                   3067:                     val = ldl_p(buf);
1.1.1.7   root     3068:                     io_mem_write[io_index][2](io_mem_opaque[io_index], addr1, val);
1.1       root     3069:                     l = 4;
1.1.1.7   root     3070:                 } else if (l >= 2 && ((addr1 & 1) == 0)) {
1.1       root     3071:                     /* 16 bit write access */
                   3072:                     val = lduw_p(buf);
1.1.1.7   root     3073:                     io_mem_write[io_index][1](io_mem_opaque[io_index], addr1, val);
1.1       root     3074:                     l = 2;
                   3075:                 } else {
                   3076:                     /* 8 bit write access */
                   3077:                     val = ldub_p(buf);
1.1.1.7   root     3078:                     io_mem_write[io_index][0](io_mem_opaque[io_index], addr1, val);
1.1       root     3079:                     l = 1;
                   3080:                 }
                   3081:             } else {
                   3082:                 unsigned long addr1;
                   3083:                 addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
                   3084:                 /* RAM case */
1.1.1.10  root     3085:                 ptr = qemu_get_ram_ptr(addr1);
1.1       root     3086:                 memcpy(ptr, buf, l);
                   3087:                 if (!cpu_physical_memory_is_dirty(addr1)) {
                   3088:                     /* invalidate code */
                   3089:                     tb_invalidate_phys_page_range(addr1, addr1 + l, 0);
                   3090:                     /* set dirty bit */
1.1.1.6   root     3091:                     phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |=
1.1       root     3092:                         (0xff & ~CODE_DIRTY_FLAG);
                   3093:                 }
                   3094:             }
                   3095:         } else {
1.1.1.6   root     3096:             if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
1.1.1.4   root     3097:                 !(pd & IO_MEM_ROMD)) {
1.1.1.7   root     3098:                 target_phys_addr_t addr1 = addr;
1.1       root     3099:                 /* I/O case */
                   3100:                 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
1.1.1.7   root     3101:                 if (p)
                   3102:                     addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
                   3103:                 if (l >= 4 && ((addr1 & 3) == 0)) {
1.1       root     3104:                     /* 32 bit read access */
1.1.1.7   root     3105:                     val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr1);
1.1       root     3106:                     stl_p(buf, val);
                   3107:                     l = 4;
1.1.1.7   root     3108:                 } else if (l >= 2 && ((addr1 & 1) == 0)) {
1.1       root     3109:                     /* 16 bit read access */
1.1.1.7   root     3110:                     val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr1);
1.1       root     3111:                     stw_p(buf, val);
                   3112:                     l = 2;
                   3113:                 } else {
                   3114:                     /* 8 bit read access */
1.1.1.7   root     3115:                     val = io_mem_read[io_index][0](io_mem_opaque[io_index], addr1);
1.1       root     3116:                     stb_p(buf, val);
                   3117:                     l = 1;
                   3118:                 }
                   3119:             } else {
                   3120:                 /* RAM case */
1.1.1.10  root     3121:                 ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) +
1.1       root     3122:                     (addr & ~TARGET_PAGE_MASK);
                   3123:                 memcpy(buf, ptr, l);
                   3124:             }
                   3125:         }
                   3126:         len -= l;
                   3127:         buf += l;
                   3128:         addr += l;
                   3129:     }
                   3130: }
                   3131: 
1.1.1.3   root     3132: /* used for ROM loading : can write in RAM and ROM */
1.1.1.6   root     3133: void cpu_physical_memory_write_rom(target_phys_addr_t addr,
1.1.1.3   root     3134:                                    const uint8_t *buf, int len)
                   3135: {
                   3136:     int l;
                   3137:     uint8_t *ptr;
                   3138:     target_phys_addr_t page;
                   3139:     unsigned long pd;
                   3140:     PhysPageDesc *p;
1.1.1.6   root     3141: 
1.1.1.3   root     3142:     while (len > 0) {
                   3143:         page = addr & TARGET_PAGE_MASK;
                   3144:         l = (page + TARGET_PAGE_SIZE) - addr;
                   3145:         if (l > len)
                   3146:             l = len;
                   3147:         p = phys_page_find(page >> TARGET_PAGE_BITS);
                   3148:         if (!p) {
                   3149:             pd = IO_MEM_UNASSIGNED;
                   3150:         } else {
                   3151:             pd = p->phys_offset;
                   3152:         }
1.1.1.6   root     3153: 
1.1.1.3   root     3154:         if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM &&
1.1.1.4   root     3155:             (pd & ~TARGET_PAGE_MASK) != IO_MEM_ROM &&
                   3156:             !(pd & IO_MEM_ROMD)) {
1.1.1.3   root     3157:             /* do nothing */
                   3158:         } else {
                   3159:             unsigned long addr1;
                   3160:             addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
                   3161:             /* ROM/RAM case */
1.1.1.10  root     3162:             ptr = qemu_get_ram_ptr(addr1);
1.1.1.3   root     3163:             memcpy(ptr, buf, l);
                   3164:         }
                   3165:         len -= l;
                   3166:         buf += l;
                   3167:         addr += l;
                   3168:     }
                   3169: }
                   3170: 
1.1.1.7   root     3171: typedef struct {
                   3172:     void *buffer;
                   3173:     target_phys_addr_t addr;
                   3174:     target_phys_addr_t len;
                   3175: } BounceBuffer;
                   3176: 
                   3177: static BounceBuffer bounce;
                   3178: 
                   3179: typedef struct MapClient {
                   3180:     void *opaque;
                   3181:     void (*callback)(void *opaque);
1.1.1.11  root     3182:     QLIST_ENTRY(MapClient) link;
1.1.1.7   root     3183: } MapClient;
                   3184: 
1.1.1.11  root     3185: static QLIST_HEAD(map_client_list, MapClient) map_client_list
                   3186:     = QLIST_HEAD_INITIALIZER(map_client_list);
1.1.1.7   root     3187: 
                   3188: void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque))
                   3189: {
                   3190:     MapClient *client = qemu_malloc(sizeof(*client));
                   3191: 
                   3192:     client->opaque = opaque;
                   3193:     client->callback = callback;
1.1.1.11  root     3194:     QLIST_INSERT_HEAD(&map_client_list, client, link);
1.1.1.7   root     3195:     return client;
                   3196: }
                   3197: 
                   3198: void cpu_unregister_map_client(void *_client)
                   3199: {
                   3200:     MapClient *client = (MapClient *)_client;
                   3201: 
1.1.1.11  root     3202:     QLIST_REMOVE(client, link);
1.1.1.10  root     3203:     qemu_free(client);
1.1.1.7   root     3204: }
                   3205: 
                   3206: static void cpu_notify_map_clients(void)
                   3207: {
                   3208:     MapClient *client;
                   3209: 
1.1.1.11  root     3210:     while (!QLIST_EMPTY(&map_client_list)) {
                   3211:         client = QLIST_FIRST(&map_client_list);
1.1.1.7   root     3212:         client->callback(client->opaque);
1.1.1.10  root     3213:         cpu_unregister_map_client(client);
1.1.1.7   root     3214:     }
                   3215: }
                   3216: 
                   3217: /* Map a physical memory region into a host virtual address.
                   3218:  * May map a subset of the requested range, given by and returned in *plen.
                   3219:  * May return NULL if resources needed to perform the mapping are exhausted.
                   3220:  * Use only for reads OR writes - not for read-modify-write operations.
                   3221:  * Use cpu_register_map_client() to know when retrying the map operation is
                   3222:  * likely to succeed.
                   3223:  */
                   3224: void *cpu_physical_memory_map(target_phys_addr_t addr,
                   3225:                               target_phys_addr_t *plen,
                   3226:                               int is_write)
                   3227: {
                   3228:     target_phys_addr_t len = *plen;
                   3229:     target_phys_addr_t done = 0;
                   3230:     int l;
                   3231:     uint8_t *ret = NULL;
                   3232:     uint8_t *ptr;
                   3233:     target_phys_addr_t page;
                   3234:     unsigned long pd;
                   3235:     PhysPageDesc *p;
                   3236:     unsigned long addr1;
                   3237: 
                   3238:     while (len > 0) {
                   3239:         page = addr & TARGET_PAGE_MASK;
                   3240:         l = (page + TARGET_PAGE_SIZE) - addr;
                   3241:         if (l > len)
                   3242:             l = len;
                   3243:         p = phys_page_find(page >> TARGET_PAGE_BITS);
                   3244:         if (!p) {
                   3245:             pd = IO_MEM_UNASSIGNED;
                   3246:         } else {
                   3247:             pd = p->phys_offset;
                   3248:         }
                   3249: 
                   3250:         if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
                   3251:             if (done || bounce.buffer) {
                   3252:                 break;
                   3253:             }
                   3254:             bounce.buffer = qemu_memalign(TARGET_PAGE_SIZE, TARGET_PAGE_SIZE);
                   3255:             bounce.addr = addr;
                   3256:             bounce.len = l;
                   3257:             if (!is_write) {
                   3258:                 cpu_physical_memory_rw(addr, bounce.buffer, l, 0);
                   3259:             }
                   3260:             ptr = bounce.buffer;
                   3261:         } else {
                   3262:             addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
1.1.1.10  root     3263:             ptr = qemu_get_ram_ptr(addr1);
1.1.1.7   root     3264:         }
                   3265:         if (!done) {
                   3266:             ret = ptr;
                   3267:         } else if (ret + done != ptr) {
                   3268:             break;
                   3269:         }
                   3270: 
                   3271:         len -= l;
                   3272:         addr += l;
                   3273:         done += l;
                   3274:     }
                   3275:     *plen = done;
                   3276:     return ret;
                   3277: }
                   3278: 
                   3279: /* Unmaps a memory region previously mapped by cpu_physical_memory_map().
                   3280:  * Will also mark the memory as dirty if is_write == 1.  access_len gives
                   3281:  * the amount of memory that was actually read or written by the caller.
                   3282:  */
                   3283: void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len,
                   3284:                                int is_write, target_phys_addr_t access_len)
                   3285: {
                   3286:     if (buffer != bounce.buffer) {
                   3287:         if (is_write) {
1.1.1.10  root     3288:             ram_addr_t addr1 = qemu_ram_addr_from_host(buffer);
1.1.1.7   root     3289:             while (access_len) {
                   3290:                 unsigned l;
                   3291:                 l = TARGET_PAGE_SIZE;
                   3292:                 if (l > access_len)
                   3293:                     l = access_len;
                   3294:                 if (!cpu_physical_memory_is_dirty(addr1)) {
                   3295:                     /* invalidate code */
                   3296:                     tb_invalidate_phys_page_range(addr1, addr1 + l, 0);
                   3297:                     /* set dirty bit */
                   3298:                     phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |=
                   3299:                         (0xff & ~CODE_DIRTY_FLAG);
                   3300:                 }
                   3301:                 addr1 += l;
                   3302:                 access_len -= l;
                   3303:             }
                   3304:         }
                   3305:         return;
                   3306:     }
                   3307:     if (is_write) {
                   3308:         cpu_physical_memory_write(bounce.addr, bounce.buffer, access_len);
                   3309:     }
1.1.1.12! root     3310:     qemu_vfree(bounce.buffer);
1.1.1.7   root     3311:     bounce.buffer = NULL;
                   3312:     cpu_notify_map_clients();
                   3313: }
1.1.1.3   root     3314: 
1.1       root     3315: /* warning: addr must be aligned */
                   3316: uint32_t ldl_phys(target_phys_addr_t addr)
                   3317: {
                   3318:     int io_index;
                   3319:     uint8_t *ptr;
                   3320:     uint32_t val;
                   3321:     unsigned long pd;
                   3322:     PhysPageDesc *p;
                   3323: 
                   3324:     p = phys_page_find(addr >> TARGET_PAGE_BITS);
                   3325:     if (!p) {
                   3326:         pd = IO_MEM_UNASSIGNED;
                   3327:     } else {
                   3328:         pd = p->phys_offset;
                   3329:     }
1.1.1.6   root     3330: 
                   3331:     if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
1.1.1.4   root     3332:         !(pd & IO_MEM_ROMD)) {
1.1       root     3333:         /* I/O case */
                   3334:         io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
1.1.1.7   root     3335:         if (p)
                   3336:             addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
1.1       root     3337:         val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
                   3338:     } else {
                   3339:         /* RAM case */
1.1.1.10  root     3340:         ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) +
1.1       root     3341:             (addr & ~TARGET_PAGE_MASK);
                   3342:         val = ldl_p(ptr);
                   3343:     }
                   3344:     return val;
                   3345: }
                   3346: 
1.1.1.2   root     3347: /* warning: addr must be aligned */
                   3348: uint64_t ldq_phys(target_phys_addr_t addr)
                   3349: {
                   3350:     int io_index;
                   3351:     uint8_t *ptr;
                   3352:     uint64_t val;
                   3353:     unsigned long pd;
                   3354:     PhysPageDesc *p;
                   3355: 
                   3356:     p = phys_page_find(addr >> TARGET_PAGE_BITS);
                   3357:     if (!p) {
                   3358:         pd = IO_MEM_UNASSIGNED;
                   3359:     } else {
                   3360:         pd = p->phys_offset;
                   3361:     }
1.1.1.6   root     3362: 
1.1.1.4   root     3363:     if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
                   3364:         !(pd & IO_MEM_ROMD)) {
1.1.1.2   root     3365:         /* I/O case */
                   3366:         io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
1.1.1.7   root     3367:         if (p)
                   3368:             addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
1.1.1.2   root     3369: #ifdef TARGET_WORDS_BIGENDIAN
                   3370:         val = (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr) << 32;
                   3371:         val |= io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4);
                   3372: #else
                   3373:         val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
                   3374:         val |= (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4) << 32;
                   3375: #endif
                   3376:     } else {
                   3377:         /* RAM case */
1.1.1.10  root     3378:         ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) +
1.1.1.2   root     3379:             (addr & ~TARGET_PAGE_MASK);
                   3380:         val = ldq_p(ptr);
                   3381:     }
                   3382:     return val;
                   3383: }
                   3384: 
                   3385: /* XXX: optimize */
                   3386: uint32_t ldub_phys(target_phys_addr_t addr)
                   3387: {
                   3388:     uint8_t val;
                   3389:     cpu_physical_memory_read(addr, &val, 1);
                   3390:     return val;
                   3391: }
                   3392: 
                   3393: /* XXX: optimize */
                   3394: uint32_t lduw_phys(target_phys_addr_t addr)
                   3395: {
                   3396:     uint16_t val;
                   3397:     cpu_physical_memory_read(addr, (uint8_t *)&val, 2);
                   3398:     return tswap16(val);
                   3399: }
                   3400: 
1.1       root     3401: /* warning: addr must be aligned. The ram page is not masked as dirty
                   3402:    and the code inside is not invalidated. It is useful if the dirty
                   3403:    bits are used to track modified PTEs */
                   3404: void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val)
                   3405: {
                   3406:     int io_index;
                   3407:     uint8_t *ptr;
                   3408:     unsigned long pd;
                   3409:     PhysPageDesc *p;
                   3410: 
                   3411:     p = phys_page_find(addr >> TARGET_PAGE_BITS);
                   3412:     if (!p) {
                   3413:         pd = IO_MEM_UNASSIGNED;
                   3414:     } else {
                   3415:         pd = p->phys_offset;
                   3416:     }
1.1.1.6   root     3417: 
1.1       root     3418:     if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
                   3419:         io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
1.1.1.7   root     3420:         if (p)
                   3421:             addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
1.1       root     3422:         io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
                   3423:     } else {
1.1.1.7   root     3424:         unsigned long addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
1.1.1.10  root     3425:         ptr = qemu_get_ram_ptr(addr1);
1.1       root     3426:         stl_p(ptr, val);
1.1.1.7   root     3427: 
                   3428:         if (unlikely(in_migration)) {
                   3429:             if (!cpu_physical_memory_is_dirty(addr1)) {
                   3430:                 /* invalidate code */
                   3431:                 tb_invalidate_phys_page_range(addr1, addr1 + 4, 0);
                   3432:                 /* set dirty bit */
                   3433:                 phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |=
                   3434:                     (0xff & ~CODE_DIRTY_FLAG);
                   3435:             }
                   3436:         }
1.1       root     3437:     }
                   3438: }
                   3439: 
1.1.1.6   root     3440: void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val)
                   3441: {
                   3442:     int io_index;
                   3443:     uint8_t *ptr;
                   3444:     unsigned long pd;
                   3445:     PhysPageDesc *p;
                   3446: 
                   3447:     p = phys_page_find(addr >> TARGET_PAGE_BITS);
                   3448:     if (!p) {
                   3449:         pd = IO_MEM_UNASSIGNED;
                   3450:     } else {
                   3451:         pd = p->phys_offset;
                   3452:     }
                   3453: 
                   3454:     if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
                   3455:         io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
1.1.1.7   root     3456:         if (p)
                   3457:             addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
1.1.1.6   root     3458: #ifdef TARGET_WORDS_BIGENDIAN
                   3459:         io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val >> 32);
                   3460:         io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val);
                   3461: #else
                   3462:         io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
                   3463:         io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val >> 32);
                   3464: #endif
                   3465:     } else {
1.1.1.10  root     3466:         ptr = qemu_get_ram_ptr(pd & TARGET_PAGE_MASK) +
1.1.1.6   root     3467:             (addr & ~TARGET_PAGE_MASK);
                   3468:         stq_p(ptr, val);
                   3469:     }
                   3470: }
                   3471: 
1.1       root     3472: /* warning: addr must be aligned */
                   3473: void stl_phys(target_phys_addr_t addr, uint32_t val)
                   3474: {
                   3475:     int io_index;
                   3476:     uint8_t *ptr;
                   3477:     unsigned long pd;
                   3478:     PhysPageDesc *p;
                   3479: 
                   3480:     p = phys_page_find(addr >> TARGET_PAGE_BITS);
                   3481:     if (!p) {
                   3482:         pd = IO_MEM_UNASSIGNED;
                   3483:     } else {
                   3484:         pd = p->phys_offset;
                   3485:     }
1.1.1.6   root     3486: 
1.1       root     3487:     if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
                   3488:         io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
1.1.1.7   root     3489:         if (p)
                   3490:             addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
1.1       root     3491:         io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
                   3492:     } else {
                   3493:         unsigned long addr1;
                   3494:         addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
                   3495:         /* RAM case */
1.1.1.10  root     3496:         ptr = qemu_get_ram_ptr(addr1);
1.1       root     3497:         stl_p(ptr, val);
                   3498:         if (!cpu_physical_memory_is_dirty(addr1)) {
                   3499:             /* invalidate code */
                   3500:             tb_invalidate_phys_page_range(addr1, addr1 + 4, 0);
                   3501:             /* set dirty bit */
                   3502:             phys_ram_dirty[addr1 >> TARGET_PAGE_BITS] |=
                   3503:                 (0xff & ~CODE_DIRTY_FLAG);
                   3504:         }
                   3505:     }
                   3506: }
                   3507: 
1.1.1.2   root     3508: /* XXX: optimize */
                   3509: void stb_phys(target_phys_addr_t addr, uint32_t val)
                   3510: {
                   3511:     uint8_t v = val;
                   3512:     cpu_physical_memory_write(addr, &v, 1);
                   3513: }
                   3514: 
                   3515: /* XXX: optimize */
                   3516: void stw_phys(target_phys_addr_t addr, uint32_t val)
                   3517: {
                   3518:     uint16_t v = tswap16(val);
                   3519:     cpu_physical_memory_write(addr, (const uint8_t *)&v, 2);
                   3520: }
                   3521: 
                   3522: /* XXX: optimize */
                   3523: void stq_phys(target_phys_addr_t addr, uint64_t val)
                   3524: {
                   3525:     val = tswap64(val);
                   3526:     cpu_physical_memory_write(addr, (const uint8_t *)&val, 8);
                   3527: }
                   3528: 
1.1       root     3529: #endif
                   3530: 
1.1.1.10  root     3531: /* virtual memory access for debug (includes writing to ROM) */
1.1.1.6   root     3532: int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
1.1       root     3533:                         uint8_t *buf, int len, int is_write)
                   3534: {
                   3535:     int l;
1.1.1.6   root     3536:     target_phys_addr_t phys_addr;
                   3537:     target_ulong page;
1.1       root     3538: 
                   3539:     while (len > 0) {
                   3540:         page = addr & TARGET_PAGE_MASK;
                   3541:         phys_addr = cpu_get_phys_page_debug(env, page);
                   3542:         /* if no physical page mapped, return an error */
                   3543:         if (phys_addr == -1)
                   3544:             return -1;
                   3545:         l = (page + TARGET_PAGE_SIZE) - addr;
                   3546:         if (l > len)
                   3547:             l = len;
1.1.1.10  root     3548:         phys_addr += (addr & ~TARGET_PAGE_MASK);
                   3549: #if !defined(CONFIG_USER_ONLY)
                   3550:         if (is_write)
                   3551:             cpu_physical_memory_write_rom(phys_addr, buf, l);
                   3552:         else
                   3553: #endif
                   3554:             cpu_physical_memory_rw(phys_addr, buf, l, is_write);
1.1       root     3555:         len -= l;
                   3556:         buf += l;
                   3557:         addr += l;
                   3558:     }
                   3559:     return 0;
                   3560: }
                   3561: 
1.1.1.7   root     3562: /* in deterministic execution mode, instructions doing device I/Os
                   3563:    must be at the end of the TB */
                   3564: void cpu_io_recompile(CPUState *env, void *retaddr)
                   3565: {
                   3566:     TranslationBlock *tb;
                   3567:     uint32_t n, cflags;
                   3568:     target_ulong pc, cs_base;
                   3569:     uint64_t flags;
                   3570: 
                   3571:     tb = tb_find_pc((unsigned long)retaddr);
                   3572:     if (!tb) {
                   3573:         cpu_abort(env, "cpu_io_recompile: could not find TB for pc=%p", 
                   3574:                   retaddr);
                   3575:     }
                   3576:     n = env->icount_decr.u16.low + tb->icount;
                   3577:     cpu_restore_state(tb, env, (unsigned long)retaddr, NULL);
                   3578:     /* Calculate how many instructions had been executed before the fault
                   3579:        occurred.  */
                   3580:     n = n - env->icount_decr.u16.low;
                   3581:     /* Generate a new TB ending on the I/O insn.  */
                   3582:     n++;
                   3583:     /* On MIPS and SH, delay slot instructions can only be restarted if
                   3584:        they were already the first instruction in the TB.  If this is not
                   3585:        the first instruction in a TB then re-execute the preceding
                   3586:        branch.  */
                   3587: #if defined(TARGET_MIPS)
                   3588:     if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && n > 1) {
                   3589:         env->active_tc.PC -= 4;
                   3590:         env->icount_decr.u16.low++;
                   3591:         env->hflags &= ~MIPS_HFLAG_BMASK;
                   3592:     }
                   3593: #elif defined(TARGET_SH4)
                   3594:     if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0
                   3595:             && n > 1) {
                   3596:         env->pc -= 2;
                   3597:         env->icount_decr.u16.low++;
                   3598:         env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL);
                   3599:     }
                   3600: #endif
                   3601:     /* This should never happen.  */
                   3602:     if (n > CF_COUNT_MASK)
                   3603:         cpu_abort(env, "TB too big during recompile");
                   3604: 
                   3605:     cflags = n | CF_LAST_IO;
                   3606:     pc = tb->pc;
                   3607:     cs_base = tb->cs_base;
                   3608:     flags = tb->flags;
                   3609:     tb_phys_invalidate(tb, -1);
                   3610:     /* FIXME: In theory this could raise an exception.  In practice
                   3611:        we have already translated the block once so it's probably ok.  */
                   3612:     tb_gen_code(env, pc, cs_base, flags, cflags);
                   3613:     /* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not
                   3614:        the first in the TB) then we end up generating a whole new TB and
                   3615:        repeating the fault, which is horribly inefficient.
                   3616:        Better would be to execute just this insn uncached, or generate a
                   3617:        second new TB.  */
                   3618:     cpu_resume_from_signal(env, NULL);
                   3619: }
                   3620: 
1.1       root     3621: void dump_exec_info(FILE *f,
                   3622:                     int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
                   3623: {
                   3624:     int i, target_code_size, max_target_code_size;
                   3625:     int direct_jmp_count, direct_jmp2_count, cross_page;
                   3626:     TranslationBlock *tb;
1.1.1.6   root     3627: 
1.1       root     3628:     target_code_size = 0;
                   3629:     max_target_code_size = 0;
                   3630:     cross_page = 0;
                   3631:     direct_jmp_count = 0;
                   3632:     direct_jmp2_count = 0;
                   3633:     for(i = 0; i < nb_tbs; i++) {
                   3634:         tb = &tbs[i];
                   3635:         target_code_size += tb->size;
                   3636:         if (tb->size > max_target_code_size)
                   3637:             max_target_code_size = tb->size;
                   3638:         if (tb->page_addr[1] != -1)
                   3639:             cross_page++;
                   3640:         if (tb->tb_next_offset[0] != 0xffff) {
                   3641:             direct_jmp_count++;
                   3642:             if (tb->tb_next_offset[1] != 0xffff) {
                   3643:                 direct_jmp2_count++;
                   3644:             }
                   3645:         }
                   3646:     }
                   3647:     /* XXX: avoid using doubles ? */
1.1.1.7   root     3648:     cpu_fprintf(f, "Translation buffer state:\n");
                   3649:     cpu_fprintf(f, "gen code size       %ld/%ld\n",
                   3650:                 code_gen_ptr - code_gen_buffer, code_gen_buffer_max_size);
                   3651:     cpu_fprintf(f, "TB count            %d/%d\n", 
                   3652:                 nb_tbs, code_gen_max_blocks);
1.1.1.6   root     3653:     cpu_fprintf(f, "TB avg target size  %d max=%d bytes\n",
1.1       root     3654:                 nb_tbs ? target_code_size / nb_tbs : 0,
                   3655:                 max_target_code_size);
1.1.1.6   root     3656:     cpu_fprintf(f, "TB avg host size    %d bytes (expansion ratio: %0.1f)\n",
1.1       root     3657:                 nb_tbs ? (code_gen_ptr - code_gen_buffer) / nb_tbs : 0,
                   3658:                 target_code_size ? (double) (code_gen_ptr - code_gen_buffer) / target_code_size : 0);
1.1.1.6   root     3659:     cpu_fprintf(f, "cross page TB count %d (%d%%)\n",
                   3660:             cross_page,
1.1       root     3661:             nb_tbs ? (cross_page * 100) / nb_tbs : 0);
                   3662:     cpu_fprintf(f, "direct jump count   %d (%d%%) (2 jumps=%d %d%%)\n",
1.1.1.6   root     3663:                 direct_jmp_count,
1.1       root     3664:                 nb_tbs ? (direct_jmp_count * 100) / nb_tbs : 0,
                   3665:                 direct_jmp2_count,
                   3666:                 nb_tbs ? (direct_jmp2_count * 100) / nb_tbs : 0);
1.1.1.7   root     3667:     cpu_fprintf(f, "\nStatistics:\n");
1.1       root     3668:     cpu_fprintf(f, "TB flush count      %d\n", tb_flush_count);
                   3669:     cpu_fprintf(f, "TB invalidate count %d\n", tb_phys_invalidate_count);
                   3670:     cpu_fprintf(f, "TLB flush count     %d\n", tlb_flush_count);
1.1.1.7   root     3671:     tcg_dump_info(f, cpu_fprintf);
1.1       root     3672: }
                   3673: 
1.1.1.6   root     3674: #if !defined(CONFIG_USER_ONLY)
1.1       root     3675: 
                   3676: #define MMUSUFFIX _cmmu
                   3677: #define GETPC() NULL
                   3678: #define env cpu_single_env
                   3679: #define SOFTMMU_CODE_ACCESS
                   3680: 
                   3681: #define SHIFT 0
                   3682: #include "softmmu_template.h"
                   3683: 
                   3684: #define SHIFT 1
                   3685: #include "softmmu_template.h"
                   3686: 
                   3687: #define SHIFT 2
                   3688: #include "softmmu_template.h"
                   3689: 
                   3690: #define SHIFT 3
                   3691: #include "softmmu_template.h"
                   3692: 
                   3693: #undef env
                   3694: 
                   3695: #endif

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