![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to acpi_piix4.c CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [Qemu by Fabrice Bellard] / qemu / hw|
Return to acpi_piix4.c CVS log | Up to [Qemu by Fabrice Bellard] / qemu / hw |
1.1 root 1: /*
2: * ACPI implementation
3: *
4: * Copyright (c) 2006 Fabrice Bellard
5: *
6: * This library is free software; you can redistribute it and/or
7: * modify it under the terms of the GNU Lesser General Public
8: * License version 2 as published by the Free Software Foundation.
9: *
10: * This library is distributed in the hope that it will be useful,
11: * but WITHOUT ANY WARRANTY; without even the implied warranty of
12: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13: * Lesser General Public License for more details.
14: *
15: * You should have received a copy of the GNU Lesser General Public
16: * License along with this library; if not, see <http://www.gnu.org/licenses/>
17: */
18: #include "hw.h"
19: #include "pc.h"
20: #include "apm.h"
21: #include "pm_smbus.h"
22: #include "pci.h"
23: #include "acpi.h"
24: #include "sysemu.h"
1.1.1.2 root 25: #include "range.h"
1.1.1.3 root 26: #include "ioport.h"
1.1 root 27:
28: //#define DEBUG
29:
30: #ifdef DEBUG
31: # define PIIX4_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
32: #else
33: # define PIIX4_DPRINTF(format, ...) do { } while (0)
34: #endif
35:
36: #define ACPI_DBG_IO_ADDR 0xb044
37:
38: #define GPE_BASE 0xafe0
1.1.1.3 root 39: #define GPE_LEN 4
1.1 root 40: #define PCI_BASE 0xae00
41: #define PCI_EJ_BASE 0xae08
1.1.1.2 root 42: #define PCI_RMV_BASE 0xae0c
43:
44: #define PIIX4_PCI_HOTPLUG_STATUS 2
1.1 root 45:
46: struct pci_status {
47: uint32_t up;
48: uint32_t down;
49: };
50:
51: typedef struct PIIX4PMState {
52: PCIDevice dev;
1.1.1.2 root 53: IORange ioport;
1.1.1.3 root 54: ACPIPM1EVT pm1a;
55: ACPIPM1CNT pm1_cnt;
1.1 root 56:
57: APMState apm;
58:
1.1.1.3 root 59: ACPIPMTimer tmr;
1.1 root 60:
61: PMSMBus smb;
62: uint32_t smb_io_base;
63:
64: qemu_irq irq;
65: qemu_irq smi_irq;
66: int kvm_enabled;
1.1.1.3 root 67: Notifier machine_ready;
1.1 root 68:
69: /* for pci hotplug */
1.1.1.3 root 70: ACPIGPE gpe;
1.1 root 71: struct pci_status pci0_status;
1.1.1.2 root 72: uint32_t pci0_hotplug_enable;
1.1 root 73: } PIIX4PMState;
74:
75: static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s);
76:
77: #define ACPI_ENABLE 0xf1
78: #define ACPI_DISABLE 0xf0
79:
80: static void pm_update_sci(PIIX4PMState *s)
81: {
82: int sci_level, pmsts;
83:
1.1.1.3 root 84: pmsts = acpi_pm1_evt_get_sts(&s->pm1a, s->tmr.overflow_time);
85: sci_level = (((pmsts & s->pm1a.en) &
1.1 root 86: (ACPI_BITMASK_RT_CLOCK_ENABLE |
87: ACPI_BITMASK_POWER_BUTTON_ENABLE |
88: ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
1.1.1.2 root 89: ACPI_BITMASK_TIMER_ENABLE)) != 0) ||
1.1.1.3 root 90: (((s->gpe.sts[0] & s->gpe.en[0]) & PIIX4_PCI_HOTPLUG_STATUS) != 0);
1.1.1.2 root 91:
1.1 root 92: qemu_set_irq(s->irq, sci_level);
93: /* schedule a timer interruption if needed */
1.1.1.3 root 94: acpi_pm_tmr_update(&s->tmr, (s->pm1a.en & ACPI_BITMASK_TIMER_ENABLE) &&
95: !(pmsts & ACPI_BITMASK_TIMER_STATUS));
1.1 root 96: }
97:
1.1.1.3 root 98: static void pm_tmr_timer(ACPIPMTimer *tmr)
1.1 root 99: {
1.1.1.3 root 100: PIIX4PMState *s = container_of(tmr, PIIX4PMState, tmr);
1.1 root 101: pm_update_sci(s);
102: }
103:
1.1.1.2 root 104: static void pm_ioport_write(IORange *ioport, uint64_t addr, unsigned width,
105: uint64_t val)
1.1 root 106: {
1.1.1.2 root 107: PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport);
108:
109: if (width != 2) {
110: PIIX4_DPRINTF("PM write port=0x%04x width=%d val=0x%08x\n",
111: (unsigned)addr, width, (unsigned)val);
112: }
113:
1.1 root 114: switch(addr) {
115: case 0x00:
1.1.1.3 root 116: acpi_pm1_evt_write_sts(&s->pm1a, &s->tmr, val);
117: pm_update_sci(s);
1.1 root 118: break;
119: case 0x02:
1.1.1.3 root 120: s->pm1a.en = val;
1.1 root 121: pm_update_sci(s);
122: break;
123: case 0x04:
1.1.1.3 root 124: acpi_pm1_cnt_write(&s->pm1a, &s->pm1_cnt, val);
1.1 root 125: break;
126: default:
127: break;
128: }
1.1.1.3 root 129: PIIX4_DPRINTF("PM writew port=0x%04x val=0x%04x\n", (unsigned int)addr,
130: (unsigned int)val);
1.1 root 131: }
132:
1.1.1.2 root 133: static void pm_ioport_read(IORange *ioport, uint64_t addr, unsigned width,
134: uint64_t *data)
1.1 root 135: {
1.1.1.2 root 136: PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport);
1.1 root 137: uint32_t val;
138:
139: switch(addr) {
140: case 0x00:
1.1.1.3 root 141: val = acpi_pm1_evt_get_sts(&s->pm1a, s->tmr.overflow_time);
1.1 root 142: break;
143: case 0x02:
1.1.1.3 root 144: val = s->pm1a.en;
1.1 root 145: break;
146: case 0x04:
1.1.1.3 root 147: val = s->pm1_cnt.cnt;
1.1 root 148: break;
149: case 0x08:
1.1.1.3 root 150: val = acpi_pm_tmr_get(&s->tmr);
1.1 root 151: break;
152: default:
153: val = 0;
154: break;
155: }
1.1.1.3 root 156: PIIX4_DPRINTF("PM readw port=0x%04x val=0x%04x\n", (unsigned int)addr, val);
1.1.1.2 root 157: *data = val;
1.1 root 158: }
159:
1.1.1.2 root 160: static const IORangeOps pm_iorange_ops = {
161: .read = pm_ioport_read,
162: .write = pm_ioport_write,
163: };
164:
1.1 root 165: static void apm_ctrl_changed(uint32_t val, void *arg)
166: {
167: PIIX4PMState *s = arg;
168:
169: /* ACPI specs 3.0, 4.7.2.5 */
1.1.1.3 root 170: acpi_pm1_cnt_update(&s->pm1_cnt, val == ACPI_ENABLE, val == ACPI_DISABLE);
1.1 root 171:
172: if (s->dev.config[0x5b] & (1 << 1)) {
173: if (s->smi_irq) {
174: qemu_irq_raise(s->smi_irq);
175: }
176: }
177: }
178:
179: static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
180: {
181: PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val);
182: }
183:
184: static void pm_io_space_update(PIIX4PMState *s)
185: {
186: uint32_t pm_io_base;
187:
188: if (s->dev.config[0x80] & 1) {
189: pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
190: pm_io_base &= 0xffc0;
191:
192: /* XXX: need to improve memory and ioport allocation */
193: PIIX4_DPRINTF("PM: mapping to 0x%x\n", pm_io_base);
1.1.1.2 root 194: iorange_init(&s->ioport, &pm_iorange_ops, pm_io_base, 64);
195: ioport_register(&s->ioport);
1.1 root 196: }
197: }
198:
199: static void pm_write_config(PCIDevice *d,
200: uint32_t address, uint32_t val, int len)
201: {
202: pci_default_write_config(d, address, val, len);
203: if (range_covers_byte(address, len, 0x80))
204: pm_io_space_update((PIIX4PMState *)d);
205: }
206:
207: static int vmstate_acpi_post_load(void *opaque, int version_id)
208: {
209: PIIX4PMState *s = opaque;
210:
211: pm_io_space_update(s);
212: return 0;
213: }
214:
1.1.1.3 root 215: #define VMSTATE_GPE_ARRAY(_field, _state) \
216: { \
217: .name = (stringify(_field)), \
218: .version_id = 0, \
219: .num = GPE_LEN, \
220: .info = &vmstate_info_uint16, \
221: .size = sizeof(uint16_t), \
222: .flags = VMS_ARRAY | VMS_POINTER, \
223: .offset = vmstate_offset_pointer(_state, _field, uint8_t), \
224: }
225:
1.1 root 226: static const VMStateDescription vmstate_gpe = {
227: .name = "gpe",
228: .version_id = 1,
229: .minimum_version_id = 1,
230: .minimum_version_id_old = 1,
231: .fields = (VMStateField []) {
1.1.1.3 root 232: VMSTATE_GPE_ARRAY(sts, ACPIGPE),
233: VMSTATE_GPE_ARRAY(en, ACPIGPE),
1.1 root 234: VMSTATE_END_OF_LIST()
235: }
236: };
237:
238: static const VMStateDescription vmstate_pci_status = {
239: .name = "pci_status",
240: .version_id = 1,
241: .minimum_version_id = 1,
242: .minimum_version_id_old = 1,
243: .fields = (VMStateField []) {
244: VMSTATE_UINT32(up, struct pci_status),
245: VMSTATE_UINT32(down, struct pci_status),
246: VMSTATE_END_OF_LIST()
247: }
248: };
249:
250: static const VMStateDescription vmstate_acpi = {
251: .name = "piix4_pm",
252: .version_id = 2,
253: .minimum_version_id = 1,
254: .minimum_version_id_old = 1,
255: .post_load = vmstate_acpi_post_load,
256: .fields = (VMStateField []) {
257: VMSTATE_PCI_DEVICE(dev, PIIX4PMState),
1.1.1.3 root 258: VMSTATE_UINT16(pm1a.sts, PIIX4PMState),
259: VMSTATE_UINT16(pm1a.en, PIIX4PMState),
260: VMSTATE_UINT16(pm1_cnt.cnt, PIIX4PMState),
1.1 root 261: VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
1.1.1.3 root 262: VMSTATE_TIMER(tmr.timer, PIIX4PMState),
263: VMSTATE_INT64(tmr.overflow_time, PIIX4PMState),
264: VMSTATE_STRUCT(gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE),
1.1 root 265: VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status,
266: struct pci_status),
267: VMSTATE_END_OF_LIST()
268: }
269: };
270:
1.1.1.2 root 271: static void piix4_update_hotplug(PIIX4PMState *s)
272: {
273: PCIDevice *dev = &s->dev;
274: BusState *bus = qdev_get_parent_bus(&dev->qdev);
275: DeviceState *qdev, *next;
276:
277: s->pci0_hotplug_enable = ~0;
278:
1.1.1.4 ! root 279: QTAILQ_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
1.1.1.2 root 280: PCIDeviceInfo *info = container_of(qdev->info, PCIDeviceInfo, qdev);
281: PCIDevice *pdev = DO_UPCAST(PCIDevice, qdev, qdev);
282: int slot = PCI_SLOT(pdev->devfn);
283:
284: if (info->no_hotplug) {
285: s->pci0_hotplug_enable &= ~(1 << slot);
286: }
287: }
288: }
289:
1.1 root 290: static void piix4_reset(void *opaque)
291: {
292: PIIX4PMState *s = opaque;
293: uint8_t *pci_conf = s->dev.config;
294:
295: pci_conf[0x58] = 0;
296: pci_conf[0x59] = 0;
297: pci_conf[0x5a] = 0;
298: pci_conf[0x5b] = 0;
299:
300: if (s->kvm_enabled) {
301: /* Mark SMM as already inited (until KVM supports SMM). */
302: pci_conf[0x5B] = 0x02;
303: }
1.1.1.2 root 304: piix4_update_hotplug(s);
1.1 root 305: }
306:
307: static void piix4_powerdown(void *opaque, int irq, int power_failing)
308: {
309: PIIX4PMState *s = opaque;
1.1.1.3 root 310: ACPIPM1EVT *pm1a = s? &s->pm1a: NULL;
311: ACPIPMTimer *tmr = s? &s->tmr: NULL;
312:
313: acpi_pm1_evt_power_down(pm1a, tmr);
314: }
315:
316: static void piix4_pm_machine_ready(Notifier *n, void *opaque)
317: {
318: PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready);
319: uint8_t *pci_conf;
320:
321: pci_conf = s->dev.config;
322: pci_conf[0x5f] = (isa_is_ioport_assigned(0x378) ? 0x80 : 0) | 0x10;
323: pci_conf[0x63] = 0x60;
324: pci_conf[0x67] = (isa_is_ioport_assigned(0x3f8) ? 0x08 : 0) |
325: (isa_is_ioport_assigned(0x2f8) ? 0x90 : 0);
1.1 root 326:
327: }
328:
329: static int piix4_pm_initfn(PCIDevice *dev)
330: {
331: PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev);
332: uint8_t *pci_conf;
333:
334: pci_conf = s->dev.config;
335: pci_conf[0x06] = 0x80;
336: pci_conf[0x07] = 0x02;
337: pci_conf[0x09] = 0x00;
338: pci_conf[0x3d] = 0x01; // interrupt pin 1
339:
340: pci_conf[0x40] = 0x01; /* PM io base read only bit */
341:
342: /* APM */
343: apm_init(&s->apm, apm_ctrl_changed, s);
344:
345: register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
346:
347: if (s->kvm_enabled) {
348: /* Mark SMM as already inited to prevent SMM from running. KVM does not
349: * support SMM mode. */
350: pci_conf[0x5B] = 0x02;
351: }
352:
353: /* XXX: which specification is used ? The i82731AB has different
354: mappings */
355: pci_conf[0x90] = s->smb_io_base | 1;
356: pci_conf[0x91] = s->smb_io_base >> 8;
357: pci_conf[0xd2] = 0x09;
358: register_ioport_write(s->smb_io_base, 64, 1, smb_ioport_writeb, &s->smb);
359: register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s->smb);
360:
1.1.1.3 root 361: acpi_pm_tmr_init(&s->tmr, pm_tmr_timer);
362: acpi_gpe_init(&s->gpe, GPE_LEN);
1.1 root 363:
364: qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1);
365:
366: pm_smbus_init(&s->dev.qdev, &s->smb);
1.1.1.3 root 367: s->machine_ready.notify = piix4_pm_machine_ready;
368: qemu_add_machine_init_done_notifier(&s->machine_ready);
1.1 root 369: qemu_register_reset(piix4_reset, s);
370: piix4_acpi_system_hot_add_init(dev->bus, s);
371:
372: return 0;
373: }
374:
375: i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
376: qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq,
377: int kvm_enabled)
378: {
379: PCIDevice *dev;
380: PIIX4PMState *s;
381:
382: dev = pci_create(bus, devfn, "PIIX4_PM");
383: qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
384:
385: s = DO_UPCAST(PIIX4PMState, dev, dev);
386: s->irq = sci_irq;
1.1.1.3 root 387: acpi_pm1_cnt_init(&s->pm1_cnt, cmos_s3);
1.1 root 388: s->smi_irq = smi_irq;
389: s->kvm_enabled = kvm_enabled;
390:
391: qdev_init_nofail(&dev->qdev);
392:
393: return s->smb.smbus;
394: }
395:
396: static PCIDeviceInfo piix4_pm_info = {
397: .qdev.name = "PIIX4_PM",
398: .qdev.desc = "PM",
399: .qdev.size = sizeof(PIIX4PMState),
400: .qdev.vmsd = &vmstate_acpi,
1.1.1.2 root 401: .qdev.no_user = 1,
402: .no_hotplug = 1,
1.1 root 403: .init = piix4_pm_initfn,
404: .config_write = pm_write_config,
1.1.1.3 root 405: .vendor_id = PCI_VENDOR_ID_INTEL,
406: .device_id = PCI_DEVICE_ID_INTEL_82371AB_3,
407: .revision = 0x03,
408: .class_id = PCI_CLASS_BRIDGE_OTHER,
1.1 root 409: .qdev.props = (Property[]) {
410: DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
411: DEFINE_PROP_END_OF_LIST(),
412: }
413: };
414:
415: static void piix4_pm_register(void)
416: {
417: pci_qdev_register(&piix4_pm_info);
418: }
419:
420: device_init(piix4_pm_register);
421:
422: static uint32_t gpe_readb(void *opaque, uint32_t addr)
423: {
1.1.1.2 root 424: PIIX4PMState *s = opaque;
1.1.1.3 root 425: uint32_t val = acpi_gpe_ioport_readb(&s->gpe, addr);
1.1 root 426:
427: PIIX4_DPRINTF("gpe read %x == %x\n", addr, val);
428: return val;
429: }
430:
431: static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
432: {
1.1.1.2 root 433: PIIX4PMState *s = opaque;
434:
1.1.1.3 root 435: acpi_gpe_ioport_writeb(&s->gpe, addr, val);
1.1.1.2 root 436: pm_update_sci(s);
1.1 root 437:
438: PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val);
439: }
440:
441: static uint32_t pcihotplug_read(void *opaque, uint32_t addr)
442: {
443: uint32_t val = 0;
444: struct pci_status *g = opaque;
445: switch (addr) {
446: case PCI_BASE:
447: val = g->up;
448: break;
449: case PCI_BASE + 4:
450: val = g->down;
451: break;
452: default:
453: break;
454: }
455:
456: PIIX4_DPRINTF("pcihotplug read %x == %x\n", addr, val);
457: return val;
458: }
459:
460: static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val)
461: {
462: struct pci_status *g = opaque;
463: switch (addr) {
464: case PCI_BASE:
465: g->up = val;
466: break;
467: case PCI_BASE + 4:
468: g->down = val;
469: break;
470: }
471:
472: PIIX4_DPRINTF("pcihotplug write %x <== %d\n", addr, val);
473: }
474:
475: static uint32_t pciej_read(void *opaque, uint32_t addr)
476: {
477: PIIX4_DPRINTF("pciej read %x\n", addr);
478: return 0;
479: }
480:
481: static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
482: {
483: BusState *bus = opaque;
484: DeviceState *qdev, *next;
485: PCIDevice *dev;
1.1.1.3 root 486: PCIDeviceInfo *info;
1.1 root 487: int slot = ffs(val) - 1;
488:
1.1.1.4 ! root 489: QTAILQ_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
1.1 root 490: dev = DO_UPCAST(PCIDevice, qdev, qdev);
1.1.1.3 root 491: info = container_of(qdev->info, PCIDeviceInfo, qdev);
492: if (PCI_SLOT(dev->devfn) == slot && !info->no_hotplug) {
1.1 root 493: qdev_free(qdev);
494: }
495: }
496:
497:
498: PIIX4_DPRINTF("pciej write %x <== %d\n", addr, val);
499: }
500:
1.1.1.2 root 501: static uint32_t pcirmv_read(void *opaque, uint32_t addr)
502: {
503: PIIX4PMState *s = opaque;
504:
505: return s->pci0_hotplug_enable;
506: }
507:
508: static void pcirmv_write(void *opaque, uint32_t addr, uint32_t val)
509: {
510: return;
511: }
512:
513: static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
514: PCIHotplugState state);
1.1 root 515:
516: static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s)
517: {
518: struct pci_status *pci0_status = &s->pci0_status;
519:
1.1.1.3 root 520: register_ioport_write(GPE_BASE, GPE_LEN, 1, gpe_writeb, s);
521: register_ioport_read(GPE_BASE, GPE_LEN, 1, gpe_readb, s);
522: acpi_gpe_blk(&s->gpe, GPE_BASE);
1.1 root 523:
524: register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, pci0_status);
525: register_ioport_read(PCI_BASE, 8, 4, pcihotplug_read, pci0_status);
526:
527: register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, bus);
528: register_ioport_read(PCI_EJ_BASE, 4, 4, pciej_read, bus);
529:
1.1.1.2 root 530: register_ioport_write(PCI_RMV_BASE, 4, 4, pcirmv_write, s);
531: register_ioport_read(PCI_RMV_BASE, 4, 4, pcirmv_read, s);
532:
1.1 root 533: pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev);
534: }
535:
536: static void enable_device(PIIX4PMState *s, int slot)
537: {
1.1.1.3 root 538: s->gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS;
1.1 root 539: s->pci0_status.up |= (1 << slot);
540: }
541:
542: static void disable_device(PIIX4PMState *s, int slot)
543: {
1.1.1.3 root 544: s->gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS;
1.1 root 545: s->pci0_status.down |= (1 << slot);
546: }
547:
1.1.1.2 root 548: static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
549: PCIHotplugState state)
1.1 root 550: {
551: int slot = PCI_SLOT(dev->devfn);
552: PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev,
553: DO_UPCAST(PCIDevice, qdev, qdev));
554:
1.1.1.2 root 555: /* Don't send event when device is enabled during qemu machine creation:
556: * it is present on boot, no hotplug event is necessary. We do send an
557: * event when the device is disabled later. */
558: if (state == PCI_COLDPLUG_ENABLED) {
559: return 0;
560: }
561:
1.1 root 562: s->pci0_status.up = 0;
563: s->pci0_status.down = 0;
1.1.1.2 root 564: if (state == PCI_HOTPLUG_ENABLED) {
1.1 root 565: enable_device(s, slot);
566: } else {
567: disable_device(s, slot);
568: }
1.1.1.2 root 569:
570: pm_update_sci(s);
571:
1.1 root 572: return 0;
573: }
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.