Diff for /qemu/hw/arm_timer.c between versions 1.1.1.10 and 1.1.1.11

version 1.1.1.10, 2018/04/24 19:00:17 version 1.1.1.11, 2018/04/24 19:27:58
Line 159  static arm_timer_state *arm_timer_init(u Line 159  static arm_timer_state *arm_timer_init(u
     arm_timer_state *s;      arm_timer_state *s;
     QEMUBH *bh;      QEMUBH *bh;
   
     s = (arm_timer_state *)qemu_mallocz(sizeof(arm_timer_state));      s = (arm_timer_state *)g_malloc0(sizeof(arm_timer_state));
     s->freq = freq;      s->freq = freq;
     s->control = TIMER_CTRL_IE;      s->control = TIMER_CTRL_IE;
   
Line 176  static arm_timer_state *arm_timer_init(u Line 176  static arm_timer_state *arm_timer_init(u
   
 typedef struct {  typedef struct {
     SysBusDevice busdev;      SysBusDevice busdev;
       MemoryRegion iomem;
     arm_timer_state *timer[2];      arm_timer_state *timer[2];
     int level[2];      int level[2];
     qemu_irq irq;      qemu_irq irq;
Line 190  static void sp804_set_irq(void *opaque,  Line 191  static void sp804_set_irq(void *opaque, 
     qemu_set_irq(s->irq, s->level[0] || s->level[1]);      qemu_set_irq(s->irq, s->level[0] || s->level[1]);
 }  }
   
 static uint32_t sp804_read(void *opaque, target_phys_addr_t offset)  static uint64_t sp804_read(void *opaque, target_phys_addr_t offset,
                              unsigned size)
 {  {
     sp804_state *s = (sp804_state *)opaque;      sp804_state *s = (sp804_state *)opaque;
   
Line 203  static uint32_t sp804_read(void *opaque, Line 205  static uint32_t sp804_read(void *opaque,
 }  }
   
 static void sp804_write(void *opaque, target_phys_addr_t offset,  static void sp804_write(void *opaque, target_phys_addr_t offset,
                         uint32_t value)                          uint64_t value, unsigned size)
 {  {
     sp804_state *s = (sp804_state *)opaque;      sp804_state *s = (sp804_state *)opaque;
   
Line 214  static void sp804_write(void *opaque, ta Line 216  static void sp804_write(void *opaque, ta
     }      }
 }  }
   
 static CPUReadMemoryFunc * const sp804_readfn[] = {  static const MemoryRegionOps sp804_ops = {
    sp804_read,      .read = sp804_read,
    sp804_read,      .write = sp804_write,
    sp804_read      .endianness = DEVICE_NATIVE_ENDIAN,
 };  };
   
 static CPUWriteMemoryFunc * const sp804_writefn[] = {  
    sp804_write,  
    sp804_write,  
    sp804_write  
 };  
   
   
 static const VMStateDescription vmstate_sp804 = {  static const VMStateDescription vmstate_sp804 = {
     .name = "sp804",      .name = "sp804",
     .version_id = 1,      .version_id = 1,
Line 240  static const VMStateDescription vmstate_ Line 235  static const VMStateDescription vmstate_
   
 static int sp804_init(SysBusDevice *dev)  static int sp804_init(SysBusDevice *dev)
 {  {
     int iomemtype;  
     sp804_state *s = FROM_SYSBUS(sp804_state, dev);      sp804_state *s = FROM_SYSBUS(sp804_state, dev);
     qemu_irq *qi;      qemu_irq *qi;
   
Line 252  static int sp804_init(SysBusDevice *dev) Line 246  static int sp804_init(SysBusDevice *dev)
     s->timer[1] = arm_timer_init(1000000);      s->timer[1] = arm_timer_init(1000000);
     s->timer[0]->irq = qi[0];      s->timer[0]->irq = qi[0];
     s->timer[1]->irq = qi[1];      s->timer[1]->irq = qi[1];
     iomemtype = cpu_register_io_memory(sp804_readfn,      memory_region_init_io(&s->iomem, &sp804_ops, s, "sp804", 0x1000);
                                        sp804_writefn, s, DEVICE_NATIVE_ENDIAN);      sysbus_init_mmio_region(dev, &s->iomem);
     sysbus_init_mmio(dev, 0x1000, iomemtype);  
     vmstate_register(&dev->qdev, -1, &vmstate_sp804, s);      vmstate_register(&dev->qdev, -1, &vmstate_sp804, s);
     return 0;      return 0;
 }  }
Line 264  static int sp804_init(SysBusDevice *dev) Line 257  static int sp804_init(SysBusDevice *dev)
   
 typedef struct {  typedef struct {
     SysBusDevice busdev;      SysBusDevice busdev;
       MemoryRegion iomem;
     arm_timer_state *timer[3];      arm_timer_state *timer[3];
 } icp_pit_state;  } icp_pit_state;
   
 static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset)  static uint64_t icp_pit_read(void *opaque, target_phys_addr_t offset,
                                unsigned size)
 {  {
     icp_pit_state *s = (icp_pit_state *)opaque;      icp_pit_state *s = (icp_pit_state *)opaque;
     int n;      int n;
   
     /* ??? Don't know the PrimeCell ID for this device.  */      /* ??? Don't know the PrimeCell ID for this device.  */
     n = offset >> 8;      n = offset >> 8;
     if (n > 3) {      if (n > 2) {
         hw_error("sp804_read: Bad timer %d\n", n);          hw_error("sp804_read: Bad timer %d\n", n);
     }      }
   
Line 282  static uint32_t icp_pit_read(void *opaqu Line 277  static uint32_t icp_pit_read(void *opaqu
 }  }
   
 static void icp_pit_write(void *opaque, target_phys_addr_t offset,  static void icp_pit_write(void *opaque, target_phys_addr_t offset,
                           uint32_t value)                            uint64_t value, unsigned size)
 {  {
     icp_pit_state *s = (icp_pit_state *)opaque;      icp_pit_state *s = (icp_pit_state *)opaque;
     int n;      int n;
   
     n = offset >> 8;      n = offset >> 8;
     if (n > 3) {      if (n > 2) {
         hw_error("sp804_write: Bad timer %d\n", n);          hw_error("sp804_write: Bad timer %d\n", n);
     }      }
   
     arm_timer_write(s->timer[n], offset & 0xff, value);      arm_timer_write(s->timer[n], offset & 0xff, value);
 }  }
   
   static const MemoryRegionOps icp_pit_ops = {
 static CPUReadMemoryFunc * const icp_pit_readfn[] = {      .read = icp_pit_read,
    icp_pit_read,      .write = icp_pit_write,
    icp_pit_read,      .endianness = DEVICE_NATIVE_ENDIAN,
    icp_pit_read  
 };  
   
 static CPUWriteMemoryFunc * const icp_pit_writefn[] = {  
    icp_pit_write,  
    icp_pit_write,  
    icp_pit_write  
 };  };
   
 static int icp_pit_init(SysBusDevice *dev)  static int icp_pit_init(SysBusDevice *dev)
 {  {
     int iomemtype;  
     icp_pit_state *s = FROM_SYSBUS(icp_pit_state, dev);      icp_pit_state *s = FROM_SYSBUS(icp_pit_state, dev);
   
     /* Timer 0 runs at the system clock speed (40MHz).  */      /* Timer 0 runs at the system clock speed (40MHz).  */
Line 323  static int icp_pit_init(SysBusDevice *de Line 310  static int icp_pit_init(SysBusDevice *de
     sysbus_init_irq(dev, &s->timer[1]->irq);      sysbus_init_irq(dev, &s->timer[1]->irq);
     sysbus_init_irq(dev, &s->timer[2]->irq);      sysbus_init_irq(dev, &s->timer[2]->irq);
   
     iomemtype = cpu_register_io_memory(icp_pit_readfn,      memory_region_init_io(&s->iomem, &icp_pit_ops, s, "icp_pit", 0x1000);
                                        icp_pit_writefn, s,      sysbus_init_mmio_region(dev, &s->iomem);
                                        DEVICE_NATIVE_ENDIAN);  
     sysbus_init_mmio(dev, 0x1000, iomemtype);  
     /* This device has no state to save/restore.  The component timers will      /* This device has no state to save/restore.  The component timers will
        save themselves.  */         save themselves.  */
     return 0;      return 0;

Removed from v.1.1.1.10  
changed lines
  Added in v.1.1.1.11


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