Diff for /qemu/hw/arm_timer.c between versions 1.1.1.3 and 1.1.1.4

version 1.1.1.3, 2018/04/24 16:48:35 version 1.1.1.4, 2018/04/24 16:52:59
Line 143  static void arm_timer_tick(void *opaque) Line 143  static void arm_timer_tick(void *opaque)
     arm_timer_update(s);      arm_timer_update(s);
 }  }
   
   static void arm_timer_save(QEMUFile *f, void *opaque)
   {
       arm_timer_state *s = (arm_timer_state *)opaque;
       qemu_put_be32(f, s->control);
       qemu_put_be32(f, s->limit);
       qemu_put_be32(f, s->int_level);
       qemu_put_ptimer(f, s->timer);
   }
   
   static int arm_timer_load(QEMUFile *f, void *opaque, int version_id)
   {
       arm_timer_state *s = (arm_timer_state *)opaque;
   
       if (version_id != 1)
           return -EINVAL;
   
       s->control = qemu_get_be32(f);
       s->limit = qemu_get_be32(f);
       s->int_level = qemu_get_be32(f);
       qemu_get_ptimer(f, s->timer);
       return 0;
   }
   
 static void *arm_timer_init(uint32_t freq, qemu_irq irq)  static void *arm_timer_init(uint32_t freq, qemu_irq irq)
 {  {
     arm_timer_state *s;      arm_timer_state *s;
Line 155  static void *arm_timer_init(uint32_t fre Line 178  static void *arm_timer_init(uint32_t fre
   
     bh = qemu_bh_new(arm_timer_tick, s);      bh = qemu_bh_new(arm_timer_tick, s);
     s->timer = ptimer_init(bh);      s->timer = ptimer_init(bh);
     /* ??? Save/restore.  */      register_savevm("arm_timer", -1, 1, arm_timer_save, arm_timer_load, s);
     return s;      return s;
 }  }
   
Line 167  static void *arm_timer_init(uint32_t fre Line 190  static void *arm_timer_init(uint32_t fre
 typedef struct {  typedef struct {
     void *timer[2];      void *timer[2];
     int level[2];      int level[2];
     uint32_t base;  
     qemu_irq irq;      qemu_irq irq;
 } sp804_state;  } sp804_state;
   
Line 185  static uint32_t sp804_read(void *opaque, Line 207  static uint32_t sp804_read(void *opaque,
     sp804_state *s = (sp804_state *)opaque;      sp804_state *s = (sp804_state *)opaque;
   
     /* ??? Don't know the PrimeCell ID for this device.  */      /* ??? Don't know the PrimeCell ID for this device.  */
     offset -= s->base;  
     if (offset < 0x20) {      if (offset < 0x20) {
         return arm_timer_read(s->timer[0], offset);          return arm_timer_read(s->timer[0], offset);
     } else {      } else {
Line 198  static void sp804_write(void *opaque, ta Line 219  static void sp804_write(void *opaque, ta
 {  {
     sp804_state *s = (sp804_state *)opaque;      sp804_state *s = (sp804_state *)opaque;
   
     offset -= s->base;  
     if (offset < 0x20) {      if (offset < 0x20) {
         arm_timer_write(s->timer[0], offset, value);          arm_timer_write(s->timer[0], offset, value);
     } else {      } else {
Line 218  static CPUWriteMemoryFunc *sp804_writefn Line 238  static CPUWriteMemoryFunc *sp804_writefn
    sp804_write     sp804_write
 };  };
   
   static void sp804_save(QEMUFile *f, void *opaque)
   {
       sp804_state *s = (sp804_state *)opaque;
       qemu_put_be32(f, s->level[0]);
       qemu_put_be32(f, s->level[1]);
   }
   
   static int sp804_load(QEMUFile *f, void *opaque, int version_id)
   {
       sp804_state *s = (sp804_state *)opaque;
   
       if (version_id != 1)
           return -EINVAL;
   
       s->level[0] = qemu_get_be32(f);
       s->level[1] = qemu_get_be32(f);
       return 0;
   }
   
 void sp804_init(uint32_t base, qemu_irq irq)  void sp804_init(uint32_t base, qemu_irq irq)
 {  {
     int iomemtype;      int iomemtype;
Line 226  void sp804_init(uint32_t base, qemu_irq  Line 265  void sp804_init(uint32_t base, qemu_irq 
   
     s = (sp804_state *)qemu_mallocz(sizeof(sp804_state));      s = (sp804_state *)qemu_mallocz(sizeof(sp804_state));
     qi = qemu_allocate_irqs(sp804_set_irq, s, 2);      qi = qemu_allocate_irqs(sp804_set_irq, s, 2);
     s->base = base;  
     s->irq = irq;      s->irq = irq;
     /* ??? The timers are actually configurable between 32kHz and 1MHz, but      /* ??? The timers are actually configurable between 32kHz and 1MHz, but
        we don't implement that.  */         we don't implement that.  */
Line 235  void sp804_init(uint32_t base, qemu_irq  Line 273  void sp804_init(uint32_t base, qemu_irq 
     iomemtype = cpu_register_io_memory(0, sp804_readfn,      iomemtype = cpu_register_io_memory(0, sp804_readfn,
                                        sp804_writefn, s);                                         sp804_writefn, s);
     cpu_register_physical_memory(base, 0x00001000, iomemtype);      cpu_register_physical_memory(base, 0x00001000, iomemtype);
     /* ??? Save/restore.  */      register_savevm("sp804", -1, 1, sp804_save, sp804_load, s);
 }  }
   
   
Line 243  void sp804_init(uint32_t base, qemu_irq  Line 281  void sp804_init(uint32_t base, qemu_irq 
   
 typedef struct {  typedef struct {
     void *timer[3];      void *timer[3];
     uint32_t base;  
 } icp_pit_state;  } icp_pit_state;
   
 static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset)  static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset)
Line 252  static uint32_t icp_pit_read(void *opaqu Line 289  static uint32_t icp_pit_read(void *opaqu
     int n;      int n;
   
     /* ??? Don't know the PrimeCell ID for this device.  */      /* ??? Don't know the PrimeCell ID for this device.  */
     offset -= s->base;  
     n = offset >> 8;      n = offset >> 8;
     if (n > 3)      if (n > 3)
         cpu_abort(cpu_single_env, "sp804_read: Bad timer %d\n", n);          cpu_abort(cpu_single_env, "sp804_read: Bad timer %d\n", n);
Line 266  static void icp_pit_write(void *opaque,  Line 302  static void icp_pit_write(void *opaque, 
     icp_pit_state *s = (icp_pit_state *)opaque;      icp_pit_state *s = (icp_pit_state *)opaque;
     int n;      int n;
   
     offset -= s->base;  
     n = offset >> 8;      n = offset >> 8;
     if (n > 3)      if (n > 3)
         cpu_abort(cpu_single_env, "sp804_write: Bad timer %d\n", n);          cpu_abort(cpu_single_env, "sp804_write: Bad timer %d\n", n);
Line 293  void icp_pit_init(uint32_t base, qemu_ir Line 328  void icp_pit_init(uint32_t base, qemu_ir
     icp_pit_state *s;      icp_pit_state *s;
   
     s = (icp_pit_state *)qemu_mallocz(sizeof(icp_pit_state));      s = (icp_pit_state *)qemu_mallocz(sizeof(icp_pit_state));
     s->base = base;  
     /* Timer 0 runs at the system clock speed (40MHz).  */      /* Timer 0 runs at the system clock speed (40MHz).  */
     s->timer[0] = arm_timer_init(40000000, pic[irq]);      s->timer[0] = arm_timer_init(40000000, pic[irq]);
     /* The other two timers run at 1MHz.  */      /* The other two timers run at 1MHz.  */
Line 303  void icp_pit_init(uint32_t base, qemu_ir Line 337  void icp_pit_init(uint32_t base, qemu_ir
     iomemtype = cpu_register_io_memory(0, icp_pit_readfn,      iomemtype = cpu_register_io_memory(0, icp_pit_readfn,
                                        icp_pit_writefn, s);                                         icp_pit_writefn, s);
     cpu_register_physical_memory(base, 0x00001000, iomemtype);      cpu_register_physical_memory(base, 0x00001000, iomemtype);
     /* ??? Save/restore.  */      /* This device has no state to save/restore.  The component timers will
          save themselves.  */
 }  }
   

Removed from v.1.1.1.3  
changed lines
  Added in v.1.1.1.4


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