Diff for /qemu/hw/arm_timer.c between versions 1.1.1.4 and 1.1.1.5

version 1.1.1.4, 2018/04/24 16:52:59 version 1.1.1.5, 2018/04/24 17:24:03
Line 7 Line 7
  * This code is licenced under the GPL.   * This code is licenced under the GPL.
  */   */
   
 #include "hw.h"  #include "sysbus.h"
 #include "qemu-timer.h"  #include "qemu-timer.h"
 #include "primecell.h"  
   
 /* Common timer implementation.  */  /* Common timer implementation.  */
   
Line 62  static uint32_t arm_timer_read(void *opa Line 61  static uint32_t arm_timer_read(void *opa
             return 0;              return 0;
         return s->int_level;          return s->int_level;
     default:      default:
         cpu_abort (cpu_single_env, "arm_timer_read: Bad offset %x\n",          hw_error("arm_timer_read: Bad offset %x\n", (int)offset);
                    (int)offset);  
         return 0;          return 0;
     }      }
 }  }
Line 130  static void arm_timer_write(void *opaque Line 128  static void arm_timer_write(void *opaque
         arm_timer_recalibrate(s, 0);          arm_timer_recalibrate(s, 0);
         break;          break;
     default:      default:
         cpu_abort (cpu_single_env, "arm_timer_write: Bad offset %x\n",          hw_error("arm_timer_write: Bad offset %x\n", (int)offset);
                    (int)offset);  
     }      }
     arm_timer_update(s);      arm_timer_update(s);
 }  }
Line 166  static int arm_timer_load(QEMUFile *f, v Line 163  static int arm_timer_load(QEMUFile *f, v
     return 0;      return 0;
 }  }
   
 static void *arm_timer_init(uint32_t freq, qemu_irq irq)  static arm_timer_state *arm_timer_init(uint32_t freq)
 {  {
     arm_timer_state *s;      arm_timer_state *s;
     QEMUBH *bh;      QEMUBH *bh;
   
     s = (arm_timer_state *)qemu_mallocz(sizeof(arm_timer_state));      s = (arm_timer_state *)qemu_mallocz(sizeof(arm_timer_state));
     s->irq = irq;  
     s->freq = freq;      s->freq = freq;
     s->control = TIMER_CTRL_IE;      s->control = TIMER_CTRL_IE;
   
Line 188  static void *arm_timer_init(uint32_t fre Line 184  static void *arm_timer_init(uint32_t fre
    Integrator/CP timer modules.  */     Integrator/CP timer modules.  */
   
 typedef struct {  typedef struct {
     void *timer[2];      SysBusDevice busdev;
       arm_timer_state *timer[2];
     int level[2];      int level[2];
     qemu_irq irq;      qemu_irq irq;
 } sp804_state;  } sp804_state;
Line 257  static int sp804_load(QEMUFile *f, void  Line 254  static int sp804_load(QEMUFile *f, void 
     return 0;      return 0;
 }  }
   
 void sp804_init(uint32_t base, qemu_irq irq)  static void sp804_init(SysBusDevice *dev)
 {  {
     int iomemtype;      int iomemtype;
     sp804_state *s;      sp804_state *s = FROM_SYSBUS(sp804_state, dev);
     qemu_irq *qi;      qemu_irq *qi;
   
     s = (sp804_state *)qemu_mallocz(sizeof(sp804_state));  
     qi = qemu_allocate_irqs(sp804_set_irq, s, 2);      qi = qemu_allocate_irqs(sp804_set_irq, s, 2);
     s->irq = irq;      sysbus_init_irq(dev, &s->irq);
     /* ??? The timers are actually configurable between 32kHz and 1MHz, but      /* ??? The timers are actually configurable between 32kHz and 1MHz, but
        we don't implement that.  */         we don't implement that.  */
     s->timer[0] = arm_timer_init(1000000, qi[0]);      s->timer[0] = arm_timer_init(1000000);
     s->timer[1] = arm_timer_init(1000000, qi[1]);      s->timer[1] = arm_timer_init(1000000);
     iomemtype = cpu_register_io_memory(0, sp804_readfn,      s->timer[0]->irq = qi[0];
       s->timer[1]->irq = qi[1];
       iomemtype = cpu_register_io_memory(sp804_readfn,
                                        sp804_writefn, s);                                         sp804_writefn, s);
     cpu_register_physical_memory(base, 0x00001000, iomemtype);      sysbus_init_mmio(dev, 0x1000, iomemtype);
     register_savevm("sp804", -1, 1, sp804_save, sp804_load, s);      register_savevm("sp804", -1, 1, sp804_save, sp804_load, s);
 }  }
   
Line 280  void sp804_init(uint32_t base, qemu_irq  Line 278  void sp804_init(uint32_t base, qemu_irq 
 /* Integrator/CP timer module.  */  /* Integrator/CP timer module.  */
   
 typedef struct {  typedef struct {
     void *timer[3];      SysBusDevice busdev;
       arm_timer_state *timer[3];
 } icp_pit_state;  } icp_pit_state;
   
 static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset)  static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset)
Line 290  static uint32_t icp_pit_read(void *opaqu Line 289  static uint32_t icp_pit_read(void *opaqu
   
     /* ??? Don't know the PrimeCell ID for this device.  */      /* ??? Don't know the PrimeCell ID for this device.  */
     n = offset >> 8;      n = offset >> 8;
     if (n > 3)      if (n > 3) {
         cpu_abort(cpu_single_env, "sp804_read: Bad timer %d\n", n);          hw_error("sp804_read: Bad timer %d\n", n);
       }
   
     return arm_timer_read(s->timer[n], offset & 0xff);      return arm_timer_read(s->timer[n], offset & 0xff);
 }  }
Line 303  static void icp_pit_write(void *opaque,  Line 303  static void icp_pit_write(void *opaque, 
     int n;      int n;
   
     n = offset >> 8;      n = offset >> 8;
     if (n > 3)      if (n > 3) {
         cpu_abort(cpu_single_env, "sp804_write: Bad timer %d\n", n);          hw_error("sp804_write: Bad timer %d\n", n);
       }
   
     arm_timer_write(s->timer[n], offset & 0xff, value);      arm_timer_write(s->timer[n], offset & 0xff, value);
 }  }
Line 322  static CPUWriteMemoryFunc *icp_pit_write Line 323  static CPUWriteMemoryFunc *icp_pit_write
    icp_pit_write     icp_pit_write
 };  };
   
 void icp_pit_init(uint32_t base, qemu_irq *pic, int irq)  static void icp_pit_init(SysBusDevice *dev)
 {  {
     int iomemtype;      int iomemtype;
     icp_pit_state *s;      icp_pit_state *s = FROM_SYSBUS(icp_pit_state, dev);
   
     s = (icp_pit_state *)qemu_mallocz(sizeof(icp_pit_state));  
     /* Timer 0 runs at the system clock speed (40MHz).  */      /* Timer 0 runs at the system clock speed (40MHz).  */
     s->timer[0] = arm_timer_init(40000000, pic[irq]);      s->timer[0] = arm_timer_init(40000000);
     /* The other two timers run at 1MHz.  */      /* The other two timers run at 1MHz.  */
     s->timer[1] = arm_timer_init(1000000, pic[irq + 1]);      s->timer[1] = arm_timer_init(1000000);
     s->timer[2] = arm_timer_init(1000000, pic[irq + 2]);      s->timer[2] = arm_timer_init(1000000);
   
     iomemtype = cpu_register_io_memory(0, icp_pit_readfn,      sysbus_init_irq(dev, &s->timer[0]->irq);
       sysbus_init_irq(dev, &s->timer[1]->irq);
       sysbus_init_irq(dev, &s->timer[2]->irq);
   
       iomemtype = cpu_register_io_memory(icp_pit_readfn,
                                        icp_pit_writefn, s);                                         icp_pit_writefn, s);
     cpu_register_physical_memory(base, 0x00001000, iomemtype);      sysbus_init_mmio(dev, 0x1000, iomemtype);
     /* This device has no state to save/restore.  The component timers will      /* This device has no state to save/restore.  The component timers will
        save themselves.  */         save themselves.  */
 }  }
   
   static void arm_timer_register_devices(void)
   {
       sysbus_register_dev("integrator_pit", sizeof(icp_pit_state), icp_pit_init);
       sysbus_register_dev("sp804", sizeof(sp804_state), sp804_init);
   }
   
   device_init(arm_timer_register_devices)

Removed from v.1.1.1.4  
changed lines
  Added in v.1.1.1.5


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