Annotation of qemu/hw/arm_timer.c, revision 1.1.1.11

1.1.1.3   root        1: /*
1.1       root        2:  * ARM PrimeCell Timer modules.
                      3:  *
                      4:  * Copyright (c) 2005-2006 CodeSourcery.
                      5:  * Written by Paul Brook
                      6:  *
1.1.1.10  root        7:  * This code is licensed under the GPL.
1.1       root        8:  */
                      9: 
1.1.1.5   root       10: #include "sysbus.h"
1.1.1.3   root       11: #include "qemu-timer.h"
1.1       root       12: 
                     13: /* Common timer implementation.  */
                     14: 
                     15: #define TIMER_CTRL_ONESHOT      (1 << 0)
                     16: #define TIMER_CTRL_32BIT        (1 << 1)
                     17: #define TIMER_CTRL_DIV1         (0 << 2)
                     18: #define TIMER_CTRL_DIV16        (1 << 2)
                     19: #define TIMER_CTRL_DIV256       (2 << 2)
                     20: #define TIMER_CTRL_IE           (1 << 5)
                     21: #define TIMER_CTRL_PERIODIC     (1 << 6)
                     22: #define TIMER_CTRL_ENABLE       (1 << 7)
                     23: 
                     24: typedef struct {
1.1.1.3   root       25:     ptimer_state *timer;
1.1       root       26:     uint32_t control;
                     27:     uint32_t limit;
                     28:     int freq;
                     29:     int int_level;
1.1.1.3   root       30:     qemu_irq irq;
1.1       root       31: } arm_timer_state;
                     32: 
                     33: /* Check all active timers, and schedule the next timer interrupt.  */
                     34: 
1.1.1.3   root       35: static void arm_timer_update(arm_timer_state *s)
1.1       root       36: {
                     37:     /* Update interrupts.  */
                     38:     if (s->int_level && (s->control & TIMER_CTRL_IE)) {
1.1.1.3   root       39:         qemu_irq_raise(s->irq);
1.1       root       40:     } else {
1.1.1.3   root       41:         qemu_irq_lower(s->irq);
1.1       root       42:     }
                     43: }
                     44: 
1.1.1.3   root       45: static uint32_t arm_timer_read(void *opaque, target_phys_addr_t offset)
1.1       root       46: {
                     47:     arm_timer_state *s = (arm_timer_state *)opaque;
                     48: 
                     49:     switch (offset >> 2) {
                     50:     case 0: /* TimerLoad */
                     51:     case 6: /* TimerBGLoad */
                     52:         return s->limit;
                     53:     case 1: /* TimerValue */
1.1.1.3   root       54:         return ptimer_get_count(s->timer);
1.1       root       55:     case 2: /* TimerControl */
                     56:         return s->control;
                     57:     case 4: /* TimerRIS */
                     58:         return s->int_level;
                     59:     case 5: /* TimerMIS */
                     60:         if ((s->control & TIMER_CTRL_IE) == 0)
                     61:             return 0;
                     62:         return s->int_level;
                     63:     default:
1.1.1.5   root       64:         hw_error("arm_timer_read: Bad offset %x\n", (int)offset);
1.1       root       65:         return 0;
                     66:     }
                     67: }
                     68: 
1.1.1.3   root       69: /* Reset the timer limit after settings have changed.  */
                     70: static void arm_timer_recalibrate(arm_timer_state *s, int reload)
                     71: {
                     72:     uint32_t limit;
                     73: 
1.1.1.7   root       74:     if ((s->control & (TIMER_CTRL_PERIODIC | TIMER_CTRL_ONESHOT)) == 0) {
1.1.1.3   root       75:         /* Free running.  */
                     76:         if (s->control & TIMER_CTRL_32BIT)
                     77:             limit = 0xffffffff;
                     78:         else
                     79:             limit = 0xffff;
                     80:     } else {
                     81:           /* Periodic.  */
                     82:           limit = s->limit;
                     83:     }
                     84:     ptimer_set_limit(s->timer, limit, reload);
                     85: }
                     86: 
1.1       root       87: static void arm_timer_write(void *opaque, target_phys_addr_t offset,
                     88:                             uint32_t value)
                     89: {
                     90:     arm_timer_state *s = (arm_timer_state *)opaque;
1.1.1.3   root       91:     int freq;
1.1       root       92: 
                     93:     switch (offset >> 2) {
                     94:     case 0: /* TimerLoad */
                     95:         s->limit = value;
1.1.1.3   root       96:         arm_timer_recalibrate(s, 1);
1.1       root       97:         break;
                     98:     case 1: /* TimerValue */
                     99:         /* ??? Linux seems to want to write to this readonly register.
                    100:            Ignore it.  */
                    101:         break;
                    102:     case 2: /* TimerControl */
                    103:         if (s->control & TIMER_CTRL_ENABLE) {
                    104:             /* Pause the timer if it is running.  This may cause some
                    105:                inaccuracy dure to rounding, but avoids a whole lot of other
                    106:                messyness.  */
1.1.1.3   root      107:             ptimer_stop(s->timer);
1.1       root      108:         }
                    109:         s->control = value;
1.1.1.3   root      110:         freq = s->freq;
1.1       root      111:         /* ??? Need to recalculate expiry time after changing divisor.  */
                    112:         switch ((value >> 2) & 3) {
1.1.1.3   root      113:         case 1: freq >>= 4; break;
                    114:         case 2: freq >>= 8; break;
1.1       root      115:         }
1.1.1.7   root      116:         arm_timer_recalibrate(s, s->control & TIMER_CTRL_ENABLE);
1.1.1.3   root      117:         ptimer_set_freq(s->timer, freq);
1.1       root      118:         if (s->control & TIMER_CTRL_ENABLE) {
                    119:             /* Restart the timer if still enabled.  */
1.1.1.3   root      120:             ptimer_run(s->timer, (s->control & TIMER_CTRL_ONESHOT) != 0);
1.1       root      121:         }
                    122:         break;
                    123:     case 3: /* TimerIntClr */
                    124:         s->int_level = 0;
                    125:         break;
                    126:     case 6: /* TimerBGLoad */
                    127:         s->limit = value;
1.1.1.3   root      128:         arm_timer_recalibrate(s, 0);
1.1       root      129:         break;
                    130:     default:
1.1.1.5   root      131:         hw_error("arm_timer_write: Bad offset %x\n", (int)offset);
1.1       root      132:     }
1.1.1.3   root      133:     arm_timer_update(s);
1.1       root      134: }
                    135: 
                    136: static void arm_timer_tick(void *opaque)
                    137: {
1.1.1.3   root      138:     arm_timer_state *s = (arm_timer_state *)opaque;
                    139:     s->int_level = 1;
                    140:     arm_timer_update(s);
1.1       root      141: }
                    142: 
1.1.1.10  root      143: static const VMStateDescription vmstate_arm_timer = {
                    144:     .name = "arm_timer",
                    145:     .version_id = 1,
                    146:     .minimum_version_id = 1,
                    147:     .minimum_version_id_old = 1,
                    148:     .fields      = (VMStateField[]) {
                    149:         VMSTATE_UINT32(control, arm_timer_state),
                    150:         VMSTATE_UINT32(limit, arm_timer_state),
                    151:         VMSTATE_INT32(int_level, arm_timer_state),
                    152:         VMSTATE_PTIMER(timer, arm_timer_state),
                    153:         VMSTATE_END_OF_LIST()
                    154:     }
                    155: };
1.1.1.4   root      156: 
1.1.1.5   root      157: static arm_timer_state *arm_timer_init(uint32_t freq)
1.1       root      158: {
                    159:     arm_timer_state *s;
1.1.1.3   root      160:     QEMUBH *bh;
1.1       root      161: 
1.1.1.11! root      162:     s = (arm_timer_state *)g_malloc0(sizeof(arm_timer_state));
1.1.1.3   root      163:     s->freq = freq;
1.1       root      164:     s->control = TIMER_CTRL_IE;
                    165: 
1.1.1.3   root      166:     bh = qemu_bh_new(arm_timer_tick, s);
                    167:     s->timer = ptimer_init(bh);
1.1.1.10  root      168:     vmstate_register(NULL, -1, &vmstate_arm_timer, s);
1.1       root      169:     return s;
                    170: }
                    171: 
                    172: /* ARM PrimeCell SP804 dual timer module.
                    173:    Docs for this device don't seem to be publicly available.  This
1.1.1.3   root      174:    implementation is based on guesswork, the linux kernel sources and the
1.1       root      175:    Integrator/CP timer modules.  */
                    176: 
                    177: typedef struct {
1.1.1.5   root      178:     SysBusDevice busdev;
1.1.1.11! root      179:     MemoryRegion iomem;
1.1.1.5   root      180:     arm_timer_state *timer[2];
1.1       root      181:     int level[2];
1.1.1.3   root      182:     qemu_irq irq;
1.1       root      183: } sp804_state;
                    184: 
1.1.1.3   root      185: /* Merge the IRQs from the two component devices.  */
1.1       root      186: static void sp804_set_irq(void *opaque, int irq, int level)
                    187: {
                    188:     sp804_state *s = (sp804_state *)opaque;
                    189: 
                    190:     s->level[irq] = level;
1.1.1.3   root      191:     qemu_set_irq(s->irq, s->level[0] || s->level[1]);
1.1       root      192: }
                    193: 
1.1.1.11! root      194: static uint64_t sp804_read(void *opaque, target_phys_addr_t offset,
        !           195:                            unsigned size)
1.1       root      196: {
                    197:     sp804_state *s = (sp804_state *)opaque;
                    198: 
                    199:     /* ??? Don't know the PrimeCell ID for this device.  */
                    200:     if (offset < 0x20) {
                    201:         return arm_timer_read(s->timer[0], offset);
                    202:     } else {
                    203:         return arm_timer_read(s->timer[1], offset - 0x20);
                    204:     }
                    205: }
                    206: 
                    207: static void sp804_write(void *opaque, target_phys_addr_t offset,
1.1.1.11! root      208:                         uint64_t value, unsigned size)
1.1       root      209: {
                    210:     sp804_state *s = (sp804_state *)opaque;
                    211: 
                    212:     if (offset < 0x20) {
                    213:         arm_timer_write(s->timer[0], offset, value);
                    214:     } else {
                    215:         arm_timer_write(s->timer[1], offset - 0x20, value);
                    216:     }
                    217: }
                    218: 
1.1.1.11! root      219: static const MemoryRegionOps sp804_ops = {
        !           220:     .read = sp804_read,
        !           221:     .write = sp804_write,
        !           222:     .endianness = DEVICE_NATIVE_ENDIAN,
1.1       root      223: };
                    224: 
1.1.1.10  root      225: static const VMStateDescription vmstate_sp804 = {
                    226:     .name = "sp804",
                    227:     .version_id = 1,
                    228:     .minimum_version_id = 1,
                    229:     .minimum_version_id_old = 1,
                    230:     .fields      = (VMStateField[]) {
                    231:         VMSTATE_INT32_ARRAY(level, sp804_state, 2),
                    232:         VMSTATE_END_OF_LIST()
                    233:     }
                    234: };
1.1.1.4   root      235: 
1.1.1.6   root      236: static int sp804_init(SysBusDevice *dev)
1.1       root      237: {
1.1.1.5   root      238:     sp804_state *s = FROM_SYSBUS(sp804_state, dev);
1.1.1.3   root      239:     qemu_irq *qi;
1.1       root      240: 
1.1.1.3   root      241:     qi = qemu_allocate_irqs(sp804_set_irq, s, 2);
1.1.1.5   root      242:     sysbus_init_irq(dev, &s->irq);
1.1       root      243:     /* ??? The timers are actually configurable between 32kHz and 1MHz, but
                    244:        we don't implement that.  */
1.1.1.5   root      245:     s->timer[0] = arm_timer_init(1000000);
                    246:     s->timer[1] = arm_timer_init(1000000);
                    247:     s->timer[0]->irq = qi[0];
                    248:     s->timer[1]->irq = qi[1];
1.1.1.11! root      249:     memory_region_init_io(&s->iomem, &sp804_ops, s, "sp804", 0x1000);
        !           250:     sysbus_init_mmio_region(dev, &s->iomem);
1.1.1.10  root      251:     vmstate_register(&dev->qdev, -1, &vmstate_sp804, s);
1.1.1.6   root      252:     return 0;
1.1       root      253: }
                    254: 
                    255: 
                    256: /* Integrator/CP timer module.  */
                    257: 
                    258: typedef struct {
1.1.1.5   root      259:     SysBusDevice busdev;
1.1.1.11! root      260:     MemoryRegion iomem;
1.1.1.5   root      261:     arm_timer_state *timer[3];
1.1       root      262: } icp_pit_state;
                    263: 
1.1.1.11! root      264: static uint64_t icp_pit_read(void *opaque, target_phys_addr_t offset,
        !           265:                              unsigned size)
1.1       root      266: {
                    267:     icp_pit_state *s = (icp_pit_state *)opaque;
                    268:     int n;
                    269: 
                    270:     /* ??? Don't know the PrimeCell ID for this device.  */
                    271:     n = offset >> 8;
1.1.1.11! root      272:     if (n > 2) {
1.1.1.5   root      273:         hw_error("sp804_read: Bad timer %d\n", n);
                    274:     }
1.1       root      275: 
                    276:     return arm_timer_read(s->timer[n], offset & 0xff);
                    277: }
                    278: 
                    279: static void icp_pit_write(void *opaque, target_phys_addr_t offset,
1.1.1.11! root      280:                           uint64_t value, unsigned size)
1.1       root      281: {
                    282:     icp_pit_state *s = (icp_pit_state *)opaque;
                    283:     int n;
                    284: 
                    285:     n = offset >> 8;
1.1.1.11! root      286:     if (n > 2) {
1.1.1.5   root      287:         hw_error("sp804_write: Bad timer %d\n", n);
                    288:     }
1.1       root      289: 
                    290:     arm_timer_write(s->timer[n], offset & 0xff, value);
                    291: }
                    292: 
1.1.1.11! root      293: static const MemoryRegionOps icp_pit_ops = {
        !           294:     .read = icp_pit_read,
        !           295:     .write = icp_pit_write,
        !           296:     .endianness = DEVICE_NATIVE_ENDIAN,
1.1       root      297: };
                    298: 
1.1.1.6   root      299: static int icp_pit_init(SysBusDevice *dev)
1.1       root      300: {
1.1.1.5   root      301:     icp_pit_state *s = FROM_SYSBUS(icp_pit_state, dev);
1.1       root      302: 
                    303:     /* Timer 0 runs at the system clock speed (40MHz).  */
1.1.1.5   root      304:     s->timer[0] = arm_timer_init(40000000);
1.1       root      305:     /* The other two timers run at 1MHz.  */
1.1.1.5   root      306:     s->timer[1] = arm_timer_init(1000000);
                    307:     s->timer[2] = arm_timer_init(1000000);
1.1       root      308: 
1.1.1.5   root      309:     sysbus_init_irq(dev, &s->timer[0]->irq);
                    310:     sysbus_init_irq(dev, &s->timer[1]->irq);
                    311:     sysbus_init_irq(dev, &s->timer[2]->irq);
                    312: 
1.1.1.11! root      313:     memory_region_init_io(&s->iomem, &icp_pit_ops, s, "icp_pit", 0x1000);
        !           314:     sysbus_init_mmio_region(dev, &s->iomem);
1.1.1.4   root      315:     /* This device has no state to save/restore.  The component timers will
                    316:        save themselves.  */
1.1.1.6   root      317:     return 0;
1.1       root      318: }
1.1.1.5   root      319: 
                    320: static void arm_timer_register_devices(void)
                    321: {
                    322:     sysbus_register_dev("integrator_pit", sizeof(icp_pit_state), icp_pit_init);
                    323:     sysbus_register_dev("sp804", sizeof(sp804_state), sp804_init);
                    324: }
                    325: 
                    326: device_init(arm_timer_register_devices)

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