Annotation of qemu/hw/arm_timer.c, revision 1.1.1.9

1.1.1.3   root        1: /*
1.1       root        2:  * ARM PrimeCell Timer modules.
                      3:  *
                      4:  * Copyright (c) 2005-2006 CodeSourcery.
                      5:  * Written by Paul Brook
                      6:  *
                      7:  * This code is licenced under the GPL.
                      8:  */
                      9: 
1.1.1.5   root       10: #include "sysbus.h"
1.1.1.3   root       11: #include "qemu-timer.h"
1.1       root       12: 
                     13: /* Common timer implementation.  */
                     14: 
                     15: #define TIMER_CTRL_ONESHOT      (1 << 0)
                     16: #define TIMER_CTRL_32BIT        (1 << 1)
                     17: #define TIMER_CTRL_DIV1         (0 << 2)
                     18: #define TIMER_CTRL_DIV16        (1 << 2)
                     19: #define TIMER_CTRL_DIV256       (2 << 2)
                     20: #define TIMER_CTRL_IE           (1 << 5)
                     21: #define TIMER_CTRL_PERIODIC     (1 << 6)
                     22: #define TIMER_CTRL_ENABLE       (1 << 7)
                     23: 
                     24: typedef struct {
1.1.1.3   root       25:     ptimer_state *timer;
1.1       root       26:     uint32_t control;
                     27:     uint32_t limit;
                     28:     int freq;
                     29:     int int_level;
1.1.1.3   root       30:     qemu_irq irq;
1.1       root       31: } arm_timer_state;
                     32: 
                     33: /* Check all active timers, and schedule the next timer interrupt.  */
                     34: 
1.1.1.3   root       35: static void arm_timer_update(arm_timer_state *s)
1.1       root       36: {
                     37:     /* Update interrupts.  */
                     38:     if (s->int_level && (s->control & TIMER_CTRL_IE)) {
1.1.1.3   root       39:         qemu_irq_raise(s->irq);
1.1       root       40:     } else {
1.1.1.3   root       41:         qemu_irq_lower(s->irq);
1.1       root       42:     }
                     43: }
                     44: 
1.1.1.3   root       45: static uint32_t arm_timer_read(void *opaque, target_phys_addr_t offset)
1.1       root       46: {
                     47:     arm_timer_state *s = (arm_timer_state *)opaque;
                     48: 
                     49:     switch (offset >> 2) {
                     50:     case 0: /* TimerLoad */
                     51:     case 6: /* TimerBGLoad */
                     52:         return s->limit;
                     53:     case 1: /* TimerValue */
1.1.1.3   root       54:         return ptimer_get_count(s->timer);
1.1       root       55:     case 2: /* TimerControl */
                     56:         return s->control;
                     57:     case 4: /* TimerRIS */
                     58:         return s->int_level;
                     59:     case 5: /* TimerMIS */
                     60:         if ((s->control & TIMER_CTRL_IE) == 0)
                     61:             return 0;
                     62:         return s->int_level;
                     63:     default:
1.1.1.5   root       64:         hw_error("arm_timer_read: Bad offset %x\n", (int)offset);
1.1       root       65:         return 0;
                     66:     }
                     67: }
                     68: 
1.1.1.3   root       69: /* Reset the timer limit after settings have changed.  */
                     70: static void arm_timer_recalibrate(arm_timer_state *s, int reload)
                     71: {
                     72:     uint32_t limit;
                     73: 
1.1.1.7   root       74:     if ((s->control & (TIMER_CTRL_PERIODIC | TIMER_CTRL_ONESHOT)) == 0) {
1.1.1.3   root       75:         /* Free running.  */
                     76:         if (s->control & TIMER_CTRL_32BIT)
                     77:             limit = 0xffffffff;
                     78:         else
                     79:             limit = 0xffff;
                     80:     } else {
                     81:           /* Periodic.  */
                     82:           limit = s->limit;
                     83:     }
                     84:     ptimer_set_limit(s->timer, limit, reload);
                     85: }
                     86: 
1.1       root       87: static void arm_timer_write(void *opaque, target_phys_addr_t offset,
                     88:                             uint32_t value)
                     89: {
                     90:     arm_timer_state *s = (arm_timer_state *)opaque;
1.1.1.3   root       91:     int freq;
1.1       root       92: 
                     93:     switch (offset >> 2) {
                     94:     case 0: /* TimerLoad */
                     95:         s->limit = value;
1.1.1.3   root       96:         arm_timer_recalibrate(s, 1);
1.1       root       97:         break;
                     98:     case 1: /* TimerValue */
                     99:         /* ??? Linux seems to want to write to this readonly register.
                    100:            Ignore it.  */
                    101:         break;
                    102:     case 2: /* TimerControl */
                    103:         if (s->control & TIMER_CTRL_ENABLE) {
                    104:             /* Pause the timer if it is running.  This may cause some
                    105:                inaccuracy dure to rounding, but avoids a whole lot of other
                    106:                messyness.  */
1.1.1.3   root      107:             ptimer_stop(s->timer);
1.1       root      108:         }
                    109:         s->control = value;
1.1.1.3   root      110:         freq = s->freq;
1.1       root      111:         /* ??? Need to recalculate expiry time after changing divisor.  */
                    112:         switch ((value >> 2) & 3) {
1.1.1.3   root      113:         case 1: freq >>= 4; break;
                    114:         case 2: freq >>= 8; break;
1.1       root      115:         }
1.1.1.7   root      116:         arm_timer_recalibrate(s, s->control & TIMER_CTRL_ENABLE);
1.1.1.3   root      117:         ptimer_set_freq(s->timer, freq);
1.1       root      118:         if (s->control & TIMER_CTRL_ENABLE) {
                    119:             /* Restart the timer if still enabled.  */
1.1.1.3   root      120:             ptimer_run(s->timer, (s->control & TIMER_CTRL_ONESHOT) != 0);
1.1       root      121:         }
                    122:         break;
                    123:     case 3: /* TimerIntClr */
                    124:         s->int_level = 0;
                    125:         break;
                    126:     case 6: /* TimerBGLoad */
                    127:         s->limit = value;
1.1.1.3   root      128:         arm_timer_recalibrate(s, 0);
1.1       root      129:         break;
                    130:     default:
1.1.1.5   root      131:         hw_error("arm_timer_write: Bad offset %x\n", (int)offset);
1.1       root      132:     }
1.1.1.3   root      133:     arm_timer_update(s);
1.1       root      134: }
                    135: 
                    136: static void arm_timer_tick(void *opaque)
                    137: {
1.1.1.3   root      138:     arm_timer_state *s = (arm_timer_state *)opaque;
                    139:     s->int_level = 1;
                    140:     arm_timer_update(s);
1.1       root      141: }
                    142: 
1.1.1.4   root      143: static void arm_timer_save(QEMUFile *f, void *opaque)
                    144: {
                    145:     arm_timer_state *s = (arm_timer_state *)opaque;
                    146:     qemu_put_be32(f, s->control);
                    147:     qemu_put_be32(f, s->limit);
                    148:     qemu_put_be32(f, s->int_level);
                    149:     qemu_put_ptimer(f, s->timer);
                    150: }
                    151: 
                    152: static int arm_timer_load(QEMUFile *f, void *opaque, int version_id)
                    153: {
                    154:     arm_timer_state *s = (arm_timer_state *)opaque;
                    155: 
                    156:     if (version_id != 1)
                    157:         return -EINVAL;
                    158: 
                    159:     s->control = qemu_get_be32(f);
                    160:     s->limit = qemu_get_be32(f);
                    161:     s->int_level = qemu_get_be32(f);
                    162:     qemu_get_ptimer(f, s->timer);
                    163:     return 0;
                    164: }
                    165: 
1.1.1.5   root      166: static arm_timer_state *arm_timer_init(uint32_t freq)
1.1       root      167: {
                    168:     arm_timer_state *s;
1.1.1.3   root      169:     QEMUBH *bh;
1.1       root      170: 
                    171:     s = (arm_timer_state *)qemu_mallocz(sizeof(arm_timer_state));
1.1.1.3   root      172:     s->freq = freq;
1.1       root      173:     s->control = TIMER_CTRL_IE;
                    174: 
1.1.1.3   root      175:     bh = qemu_bh_new(arm_timer_tick, s);
                    176:     s->timer = ptimer_init(bh);
1.1.1.8   root      177:     register_savevm(NULL, "arm_timer", -1, 1, arm_timer_save, arm_timer_load, s);
1.1       root      178:     return s;
                    179: }
                    180: 
                    181: /* ARM PrimeCell SP804 dual timer module.
                    182:    Docs for this device don't seem to be publicly available.  This
1.1.1.3   root      183:    implementation is based on guesswork, the linux kernel sources and the
1.1       root      184:    Integrator/CP timer modules.  */
                    185: 
                    186: typedef struct {
1.1.1.5   root      187:     SysBusDevice busdev;
                    188:     arm_timer_state *timer[2];
1.1       root      189:     int level[2];
1.1.1.3   root      190:     qemu_irq irq;
1.1       root      191: } sp804_state;
                    192: 
1.1.1.3   root      193: /* Merge the IRQs from the two component devices.  */
1.1       root      194: static void sp804_set_irq(void *opaque, int irq, int level)
                    195: {
                    196:     sp804_state *s = (sp804_state *)opaque;
                    197: 
                    198:     s->level[irq] = level;
1.1.1.3   root      199:     qemu_set_irq(s->irq, s->level[0] || s->level[1]);
1.1       root      200: }
                    201: 
                    202: static uint32_t sp804_read(void *opaque, target_phys_addr_t offset)
                    203: {
                    204:     sp804_state *s = (sp804_state *)opaque;
                    205: 
                    206:     /* ??? Don't know the PrimeCell ID for this device.  */
                    207:     if (offset < 0x20) {
                    208:         return arm_timer_read(s->timer[0], offset);
                    209:     } else {
                    210:         return arm_timer_read(s->timer[1], offset - 0x20);
                    211:     }
                    212: }
                    213: 
                    214: static void sp804_write(void *opaque, target_phys_addr_t offset,
                    215:                         uint32_t value)
                    216: {
                    217:     sp804_state *s = (sp804_state *)opaque;
                    218: 
                    219:     if (offset < 0x20) {
                    220:         arm_timer_write(s->timer[0], offset, value);
                    221:     } else {
                    222:         arm_timer_write(s->timer[1], offset - 0x20, value);
                    223:     }
                    224: }
                    225: 
1.1.1.6   root      226: static CPUReadMemoryFunc * const sp804_readfn[] = {
1.1       root      227:    sp804_read,
                    228:    sp804_read,
                    229:    sp804_read
                    230: };
                    231: 
1.1.1.6   root      232: static CPUWriteMemoryFunc * const sp804_writefn[] = {
1.1       root      233:    sp804_write,
                    234:    sp804_write,
                    235:    sp804_write
                    236: };
                    237: 
1.1.1.4   root      238: static void sp804_save(QEMUFile *f, void *opaque)
                    239: {
                    240:     sp804_state *s = (sp804_state *)opaque;
                    241:     qemu_put_be32(f, s->level[0]);
                    242:     qemu_put_be32(f, s->level[1]);
                    243: }
                    244: 
                    245: static int sp804_load(QEMUFile *f, void *opaque, int version_id)
                    246: {
                    247:     sp804_state *s = (sp804_state *)opaque;
                    248: 
                    249:     if (version_id != 1)
                    250:         return -EINVAL;
                    251: 
                    252:     s->level[0] = qemu_get_be32(f);
                    253:     s->level[1] = qemu_get_be32(f);
                    254:     return 0;
                    255: }
                    256: 
1.1.1.6   root      257: static int sp804_init(SysBusDevice *dev)
1.1       root      258: {
                    259:     int iomemtype;
1.1.1.5   root      260:     sp804_state *s = FROM_SYSBUS(sp804_state, dev);
1.1.1.3   root      261:     qemu_irq *qi;
1.1       root      262: 
1.1.1.3   root      263:     qi = qemu_allocate_irqs(sp804_set_irq, s, 2);
1.1.1.5   root      264:     sysbus_init_irq(dev, &s->irq);
1.1       root      265:     /* ??? The timers are actually configurable between 32kHz and 1MHz, but
                    266:        we don't implement that.  */
1.1.1.5   root      267:     s->timer[0] = arm_timer_init(1000000);
                    268:     s->timer[1] = arm_timer_init(1000000);
                    269:     s->timer[0]->irq = qi[0];
                    270:     s->timer[1]->irq = qi[1];
                    271:     iomemtype = cpu_register_io_memory(sp804_readfn,
1.1.1.9 ! root      272:                                        sp804_writefn, s, DEVICE_NATIVE_ENDIAN);
1.1.1.5   root      273:     sysbus_init_mmio(dev, 0x1000, iomemtype);
1.1.1.8   root      274:     register_savevm(&dev->qdev, "sp804", -1, 1, sp804_save, sp804_load, s);
1.1.1.6   root      275:     return 0;
1.1       root      276: }
                    277: 
                    278: 
                    279: /* Integrator/CP timer module.  */
                    280: 
                    281: typedef struct {
1.1.1.5   root      282:     SysBusDevice busdev;
                    283:     arm_timer_state *timer[3];
1.1       root      284: } icp_pit_state;
                    285: 
                    286: static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset)
                    287: {
                    288:     icp_pit_state *s = (icp_pit_state *)opaque;
                    289:     int n;
                    290: 
                    291:     /* ??? Don't know the PrimeCell ID for this device.  */
                    292:     n = offset >> 8;
1.1.1.5   root      293:     if (n > 3) {
                    294:         hw_error("sp804_read: Bad timer %d\n", n);
                    295:     }
1.1       root      296: 
                    297:     return arm_timer_read(s->timer[n], offset & 0xff);
                    298: }
                    299: 
                    300: static void icp_pit_write(void *opaque, target_phys_addr_t offset,
                    301:                           uint32_t value)
                    302: {
                    303:     icp_pit_state *s = (icp_pit_state *)opaque;
                    304:     int n;
                    305: 
                    306:     n = offset >> 8;
1.1.1.5   root      307:     if (n > 3) {
                    308:         hw_error("sp804_write: Bad timer %d\n", n);
                    309:     }
1.1       root      310: 
                    311:     arm_timer_write(s->timer[n], offset & 0xff, value);
                    312: }
                    313: 
                    314: 
1.1.1.6   root      315: static CPUReadMemoryFunc * const icp_pit_readfn[] = {
1.1       root      316:    icp_pit_read,
                    317:    icp_pit_read,
                    318:    icp_pit_read
                    319: };
                    320: 
1.1.1.6   root      321: static CPUWriteMemoryFunc * const icp_pit_writefn[] = {
1.1       root      322:    icp_pit_write,
                    323:    icp_pit_write,
                    324:    icp_pit_write
                    325: };
                    326: 
1.1.1.6   root      327: static int icp_pit_init(SysBusDevice *dev)
1.1       root      328: {
                    329:     int iomemtype;
1.1.1.5   root      330:     icp_pit_state *s = FROM_SYSBUS(icp_pit_state, dev);
1.1       root      331: 
                    332:     /* Timer 0 runs at the system clock speed (40MHz).  */
1.1.1.5   root      333:     s->timer[0] = arm_timer_init(40000000);
1.1       root      334:     /* The other two timers run at 1MHz.  */
1.1.1.5   root      335:     s->timer[1] = arm_timer_init(1000000);
                    336:     s->timer[2] = arm_timer_init(1000000);
1.1       root      337: 
1.1.1.5   root      338:     sysbus_init_irq(dev, &s->timer[0]->irq);
                    339:     sysbus_init_irq(dev, &s->timer[1]->irq);
                    340:     sysbus_init_irq(dev, &s->timer[2]->irq);
                    341: 
                    342:     iomemtype = cpu_register_io_memory(icp_pit_readfn,
1.1.1.9 ! root      343:                                        icp_pit_writefn, s,
        !           344:                                        DEVICE_NATIVE_ENDIAN);
1.1.1.5   root      345:     sysbus_init_mmio(dev, 0x1000, iomemtype);
1.1.1.4   root      346:     /* This device has no state to save/restore.  The component timers will
                    347:        save themselves.  */
1.1.1.6   root      348:     return 0;
1.1       root      349: }
1.1.1.5   root      350: 
                    351: static void arm_timer_register_devices(void)
                    352: {
                    353:     sysbus_register_dev("integrator_pit", sizeof(icp_pit_state), icp_pit_init);
                    354:     sysbus_register_dev("sp804", sizeof(sp804_state), sp804_init);
                    355: }
                    356: 
                    357: device_init(arm_timer_register_devices)

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