Diff for /qemu/hw/armv7m.c between versions 1.1.1.7 and 1.1.1.8

version 1.1.1.7, 2018/04/24 19:00:09 version 1.1.1.8, 2018/04/24 19:27:49
Line 106  static void bitband_writel(void *opaque, Line 106  static void bitband_writel(void *opaque,
     cpu_physical_memory_write(addr, (uint8_t *)&v, 4);      cpu_physical_memory_write(addr, (uint8_t *)&v, 4);
 }  }
   
 static CPUReadMemoryFunc * const bitband_readfn[] = {  static const MemoryRegionOps bitband_ops = {
    bitband_readb,      .old_mmio = {
    bitband_readw,          .read = { bitband_readb, bitband_readw, bitband_readl, },
    bitband_readl          .write = { bitband_writeb, bitband_writew, bitband_writel, },
 };      },
       .endianness = DEVICE_NATIVE_ENDIAN,
 static CPUWriteMemoryFunc * const bitband_writefn[] = {  
    bitband_writeb,  
    bitband_writew,  
    bitband_writel  
 };  };
   
 typedef struct {  typedef struct {
     SysBusDevice busdev;      SysBusDevice busdev;
       MemoryRegion iomem;
     uint32_t base;      uint32_t base;
 } BitBandState;  } BitBandState;
   
 static int bitband_init(SysBusDevice *dev)  static int bitband_init(SysBusDevice *dev)
 {  {
     BitBandState *s = FROM_SYSBUS(BitBandState, dev);      BitBandState *s = FROM_SYSBUS(BitBandState, dev);
     int iomemtype;  
   
     iomemtype = cpu_register_io_memory(bitband_readfn, bitband_writefn,      memory_region_init_io(&s->iomem, &bitband_ops, &s->base, "bitband",
                                        &s->base, DEVICE_NATIVE_ENDIAN);                            0x02000000);
     sysbus_init_mmio(dev, 0x02000000, iomemtype);      sysbus_init_mmio_region(dev, &s->iomem);
     return 0;      return 0;
 }  }
   
Line 160  static void armv7m_reset(void *opaque) Line 156  static void armv7m_reset(void *opaque)
    flash_size and sram_size are in kb.     flash_size and sram_size are in kb.
    Returns the NVIC array.  */     Returns the NVIC array.  */
   
 qemu_irq *armv7m_init(int flash_size, int sram_size,  qemu_irq *armv7m_init(MemoryRegion *address_space_mem,
                         int flash_size, int sram_size,
                       const char *kernel_filename, const char *cpu_model)                        const char *kernel_filename, const char *cpu_model)
 {  {
     CPUState *env;      CPUState *env;
Line 173  qemu_irq *armv7m_init(int flash_size, in Line 170  qemu_irq *armv7m_init(int flash_size, in
     uint64_t lowaddr;      uint64_t lowaddr;
     int i;      int i;
     int big_endian;      int big_endian;
       MemoryRegion *sram = g_new(MemoryRegion, 1);
       MemoryRegion *flash = g_new(MemoryRegion, 1);
       MemoryRegion *hack = g_new(MemoryRegion, 1);
   
     flash_size *= 1024;      flash_size *= 1024;
     sram_size *= 1024;      sram_size *= 1024;
Line 198  qemu_irq *armv7m_init(int flash_size, in Line 198  qemu_irq *armv7m_init(int flash_size, in
 #endif  #endif
   
     /* Flash programming is done via the SCU, so pretend it is ROM.  */      /* Flash programming is done via the SCU, so pretend it is ROM.  */
     cpu_register_physical_memory(0, flash_size,      memory_region_init_ram(flash, NULL, "armv7m.flash", flash_size);
                                  qemu_ram_alloc(NULL, "armv7m.flash",      memory_region_set_readonly(flash, true);
                                                 flash_size) | IO_MEM_ROM);      memory_region_add_subregion(address_space_mem, 0, flash);
     cpu_register_physical_memory(0x20000000, sram_size,      memory_region_init_ram(sram, NULL, "armv7m.sram", sram_size);
                                  qemu_ram_alloc(NULL, "armv7m.sram",      memory_region_add_subregion(address_space_mem, 0x20000000, sram);
                                                 sram_size) | IO_MEM_RAM);  
     armv7m_bitband_init();      armv7m_bitband_init();
   
     nvic = qdev_create(NULL, "armv7m_nvic");      nvic = qdev_create(NULL, "armv7m_nvic");
Line 236  qemu_irq *armv7m_init(int flash_size, in Line 235  qemu_irq *armv7m_init(int flash_size, in
     /* Hack to map an additional page of ram at the top of the address      /* Hack to map an additional page of ram at the top of the address
        space.  This stops qemu complaining about executing code outside RAM         space.  This stops qemu complaining about executing code outside RAM
        when returning from an exception.  */         when returning from an exception.  */
     cpu_register_physical_memory(0xfffff000, 0x1000,      memory_region_init_ram(hack, NULL, "armv7m.hack", 0x1000);
                                  qemu_ram_alloc(NULL, "armv7m.hack",       memory_region_add_subregion(address_space_mem, 0xfffff000, hack);
                                                 0x1000) | IO_MEM_RAM);  
   
     qemu_register_reset(armv7m_reset, env);      qemu_register_reset(armv7m_reset, env);
     return pic;      return pic;

Removed from v.1.1.1.7  
changed lines
  Added in v.1.1.1.8


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