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Diff for /qemu/hw/armv7m.c between versions 1.1.1.4 and 1.1.1.8

version 1.1.1.4, 2018/04/24 17:38:00 version 1.1.1.8, 2018/04/24 19:27:49
Line 4 Line 4
  * Copyright (c) 2006-2007 CodeSourcery.   * Copyright (c) 2006-2007 CodeSourcery.
  * Written by Paul Brook   * Written by Paul Brook
  *   *
  * This code is licenced under the GPL.   * This code is licensed under the GPL.
  */   */
   
 #include "sysbus.h"  #include "sysbus.h"
 #include "arm-misc.h"  #include "arm-misc.h"
 #include "sysemu.h"  
 #include "loader.h"  #include "loader.h"
 #include "elf.h"  #include "elf.h"
   
 /* Bitbanded IO.  Each word corresponds to a single bit.  */  /* Bitbanded IO.  Each word corresponds to a single bit.  */
   
 /* Get the byte address of the real memory for a bitband acess.  */  /* Get the byte address of the real memory for a bitband access.  */
 static inline uint32_t bitband_addr(void * opaque, uint32_t addr)  static inline uint32_t bitband_addr(void * opaque, uint32_t addr)
 {  {
     uint32_t res;      uint32_t res;
Line 107  static void bitband_writel(void *opaque, Line 106  static void bitband_writel(void *opaque,
     cpu_physical_memory_write(addr, (uint8_t *)&v, 4);      cpu_physical_memory_write(addr, (uint8_t *)&v, 4);
 }  }
   
 static CPUReadMemoryFunc * const bitband_readfn[] = {  static const MemoryRegionOps bitband_ops = {
    bitband_readb,      .old_mmio = {
    bitband_readw,          .read = { bitband_readb, bitband_readw, bitband_readl, },
    bitband_readl          .write = { bitband_writeb, bitband_writew, bitband_writel, },
 };      },
       .endianness = DEVICE_NATIVE_ENDIAN,
 static CPUWriteMemoryFunc * const bitband_writefn[] = {  
    bitband_writeb,  
    bitband_writew,  
    bitband_writel  
 };  };
   
 typedef struct {  typedef struct {
     SysBusDevice busdev;      SysBusDevice busdev;
       MemoryRegion iomem;
     uint32_t base;      uint32_t base;
 } BitBandState;  } BitBandState;
   
 static int bitband_init(SysBusDevice *dev)  static int bitband_init(SysBusDevice *dev)
 {  {
     BitBandState *s = FROM_SYSBUS(BitBandState, dev);      BitBandState *s = FROM_SYSBUS(BitBandState, dev);
     int iomemtype;  
   
     iomemtype = cpu_register_io_memory(bitband_readfn, bitband_writefn,      memory_region_init_io(&s->iomem, &bitband_ops, &s->base, "bitband",
                                        &s->base);                            0x02000000);
     sysbus_init_mmio(dev, 0x02000000, iomemtype);      sysbus_init_mmio_region(dev, &s->iomem);
     return 0;      return 0;
 }  }
   
Line 151  static void armv7m_bitband_init(void) Line 146  static void armv7m_bitband_init(void)
 }  }
   
 /* Board init.  */  /* Board init.  */
   
   static void armv7m_reset(void *opaque)
   {
       cpu_reset((CPUState *)opaque);
   }
   
 /* Init CPU and memory for a v7-M based board.  /* Init CPU and memory for a v7-M based board.
    flash_size and sram_size are in kb.     flash_size and sram_size are in kb.
    Returns the NVIC array.  */     Returns the NVIC array.  */
   
 qemu_irq *armv7m_init(int flash_size, int sram_size,  qemu_irq *armv7m_init(MemoryRegion *address_space_mem,
                         int flash_size, int sram_size,
                       const char *kernel_filename, const char *cpu_model)                        const char *kernel_filename, const char *cpu_model)
 {  {
     CPUState *env;      CPUState *env;
Line 163  qemu_irq *armv7m_init(int flash_size, in Line 165  qemu_irq *armv7m_init(int flash_size, in
     /* FIXME: make this local state.  */      /* FIXME: make this local state.  */
     static qemu_irq pic[64];      static qemu_irq pic[64];
     qemu_irq *cpu_pic;      qemu_irq *cpu_pic;
     uint32_t pc;  
     int image_size;      int image_size;
     uint64_t entry;      uint64_t entry;
     uint64_t lowaddr;      uint64_t lowaddr;
     int i;      int i;
     int big_endian;      int big_endian;
       MemoryRegion *sram = g_new(MemoryRegion, 1);
       MemoryRegion *flash = g_new(MemoryRegion, 1);
       MemoryRegion *hack = g_new(MemoryRegion, 1);
   
     flash_size *= 1024;      flash_size *= 1024;
     sram_size *= 1024;      sram_size *= 1024;
Line 194  qemu_irq *armv7m_init(int flash_size, in Line 198  qemu_irq *armv7m_init(int flash_size, in
 #endif  #endif
   
     /* Flash programming is done via the SCU, so pretend it is ROM.  */      /* Flash programming is done via the SCU, so pretend it is ROM.  */
     cpu_register_physical_memory(0, flash_size,      memory_region_init_ram(flash, NULL, "armv7m.flash", flash_size);
                                  qemu_ram_alloc(flash_size) | IO_MEM_ROM);      memory_region_set_readonly(flash, true);
     cpu_register_physical_memory(0x20000000, sram_size,      memory_region_add_subregion(address_space_mem, 0, flash);
                                  qemu_ram_alloc(sram_size) | IO_MEM_RAM);      memory_region_init_ram(sram, NULL, "armv7m.sram", sram_size);
       memory_region_add_subregion(address_space_mem, 0x20000000, sram);
     armv7m_bitband_init();      armv7m_bitband_init();
   
     nvic = qdev_create(NULL, "armv7m_nvic");      nvic = qdev_create(NULL, "armv7m_nvic");
     env->v7m.nvic = nvic;      env->nvic = nvic;
     qdev_init_nofail(nvic);      qdev_init_nofail(nvic);
     cpu_pic = arm_pic_init_cpu(env);      cpu_pic = arm_pic_init_cpu(env);
     sysbus_connect_irq(sysbus_from_qdev(nvic), 0, cpu_pic[ARM_PIC_CPU_IRQ]);      sysbus_connect_irq(sysbus_from_qdev(nvic), 0, cpu_pic[ARM_PIC_CPU_IRQ]);
Line 215  qemu_irq *armv7m_init(int flash_size, in Line 220  qemu_irq *armv7m_init(int flash_size, in
     big_endian = 0;      big_endian = 0;
 #endif  #endif
   
     image_size = load_elf(kernel_filename, 0, &entry, &lowaddr, NULL,      image_size = load_elf(kernel_filename, NULL, NULL, &entry, &lowaddr,
                           big_endian, ELF_MACHINE, 1);                            NULL, big_endian, ELF_MACHINE, 1);
     if (image_size < 0) {      if (image_size < 0) {
         image_size = load_image_targphys(kernel_filename, 0, flash_size);          image_size = load_image_targphys(kernel_filename, 0, flash_size);
         lowaddr = 0;          lowaddr = 0;
Line 227  qemu_irq *armv7m_init(int flash_size, in Line 232  qemu_irq *armv7m_init(int flash_size, in
         exit(1);          exit(1);
     }      }
   
     /* If the image was loaded at address zero then assume it is a  
        regular ROM image and perform the normal CPU reset sequence.  
        Otherwise jump directly to the entry point.  */  
     if (lowaddr == 0) {  
         env->regs[13] = ldl_phys(0);  
         pc = ldl_phys(4);  
     } else {  
         pc = entry;  
     }  
     env->thumb = pc & 1;  
     env->regs[15] = pc & ~1;  
   
     /* Hack to map an additional page of ram at the top of the address      /* Hack to map an additional page of ram at the top of the address
        space.  This stops qemu complaining about executing code outside RAM         space.  This stops qemu complaining about executing code outside RAM
        when returning from an exception.  */         when returning from an exception.  */
     cpu_register_physical_memory(0xfffff000, 0x1000,      memory_region_init_ram(hack, NULL, "armv7m.hack", 0x1000);
                                  qemu_ram_alloc(0x1000) | IO_MEM_RAM);      memory_region_add_subregion(address_space_mem, 0xfffff000, hack);
   
       qemu_register_reset(armv7m_reset, env);
     return pic;      return pic;
 }  }
   
Removed from v.1.1.1.4  
changed lines
  Added in v.1.1.1.8

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