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1.1 root 1: /*
2: * QEMU model for the AXIS devboard 88.
3: *
4: * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
5: *
6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
1.1.1.3 root 24:
25: #include "sysbus.h"
1.1 root 26: #include "net.h"
27: #include "flash.h"
28: #include "boards.h"
1.1.1.3 root 29: #include "sysemu.h"
1.1 root 30: #include "etraxfs.h"
1.1.1.4 ! root 31: #include "loader.h"
! 32: #include "elf.h"
1.1 root 33:
34: #define D(x)
35: #define DNAND(x)
36:
37: struct nand_state_t
38: {
1.1.1.3 root 39: NANDFlashState *nand;
1.1 root 40: unsigned int rdy:1;
41: unsigned int ale:1;
42: unsigned int cle:1;
43: unsigned int ce:1;
44: };
45:
46: static struct nand_state_t nand_state;
47: static uint32_t nand_readl (void *opaque, target_phys_addr_t addr)
48: {
49: struct nand_state_t *s = opaque;
50: uint32_t r;
51: int rdy;
52:
53: r = nand_getio(s->nand);
54: nand_getpins(s->nand, &rdy);
55: s->rdy = rdy;
56:
57: DNAND(printf("%s addr=%x r=%x\n", __func__, addr, r));
58: return r;
59: }
60:
61: static void
62: nand_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
63: {
64: struct nand_state_t *s = opaque;
65: int rdy;
66:
67: DNAND(printf("%s addr=%x v=%x\n", __func__, addr, value));
68: nand_setpins(s->nand, s->cle, s->ale, s->ce, 1, 0);
69: nand_setio(s->nand, value);
70: nand_getpins(s->nand, &rdy);
71: s->rdy = rdy;
72: }
73:
1.1.1.4 ! root 74: static CPUReadMemoryFunc * const nand_read[] = {
1.1 root 75: &nand_readl,
76: &nand_readl,
77: &nand_readl,
78: };
79:
1.1.1.4 ! root 80: static CPUWriteMemoryFunc * const nand_write[] = {
1.1 root 81: &nand_writel,
82: &nand_writel,
83: &nand_writel,
84: };
85:
86:
87: struct tempsensor_t
88: {
89: unsigned int shiftreg;
90: unsigned int count;
91: enum {
92: ST_OUT, ST_IN, ST_Z
93: } state;
94:
95: uint16_t regs[3];
96: };
97:
98: static void tempsensor_clkedge(struct tempsensor_t *s,
99: unsigned int clk, unsigned int data_in)
100: {
101: D(printf("%s clk=%d state=%d sr=%x\n", __func__,
102: clk, s->state, s->shiftreg));
103: if (s->count == 0) {
104: s->count = 16;
105: s->state = ST_OUT;
106: }
107: switch (s->state) {
108: case ST_OUT:
109: /* Output reg is clocked at negedge. */
110: if (!clk) {
111: s->count--;
112: s->shiftreg <<= 1;
113: if (s->count == 0) {
114: s->shiftreg = 0;
115: s->state = ST_IN;
116: s->count = 16;
117: }
118: }
119: break;
120: case ST_Z:
121: if (clk) {
122: s->count--;
123: if (s->count == 0) {
124: s->shiftreg = 0;
125: s->state = ST_OUT;
126: s->count = 16;
127: }
128: }
129: break;
130: case ST_IN:
131: /* Indata is sampled at posedge. */
132: if (clk) {
133: s->count--;
134: s->shiftreg <<= 1;
135: s->shiftreg |= data_in & 1;
136: if (s->count == 0) {
137: D(printf("%s cfgreg=%x\n", __func__, s->shiftreg));
138: s->regs[0] = s->shiftreg;
139: s->state = ST_OUT;
140: s->count = 16;
141:
142: if ((s->regs[0] & 0xff) == 0) {
143: /* 25 degrees celcius. */
144: s->shiftreg = 0x0b9f;
145: } else if ((s->regs[0] & 0xff) == 0xff) {
146: /* Sensor ID, 0x8100 LM70. */
147: s->shiftreg = 0x8100;
148: } else
149: printf("Invalid tempsens state %x\n", s->regs[0]);
150: }
151: }
152: break;
153: }
154: }
155:
156:
157: #define RW_PA_DOUT 0x00
158: #define R_PA_DIN 0x01
159: #define RW_PA_OE 0x02
160: #define RW_PD_DOUT 0x10
161: #define R_PD_DIN 0x11
162: #define RW_PD_OE 0x12
163:
164: static struct gpio_state_t
165: {
166: struct nand_state_t *nand;
167: struct tempsensor_t tempsensor;
168: uint32_t regs[0x5c / 4];
169: } gpio_state;
170:
171: static uint32_t gpio_readl (void *opaque, target_phys_addr_t addr)
172: {
173: struct gpio_state_t *s = opaque;
174: uint32_t r = 0;
175:
176: addr >>= 2;
177: switch (addr)
178: {
179: case R_PA_DIN:
180: r = s->regs[RW_PA_DOUT] & s->regs[RW_PA_OE];
181:
182: /* Encode pins from the nand. */
183: r |= s->nand->rdy << 7;
184: break;
185: case R_PD_DIN:
186: r = s->regs[RW_PD_DOUT] & s->regs[RW_PD_OE];
187:
188: /* Encode temp sensor pins. */
189: r |= (!!(s->tempsensor.shiftreg & 0x10000)) << 4;
190: break;
191:
192: default:
193: r = s->regs[addr];
194: break;
195: }
196: return r;
197: D(printf("%s %x=%x\n", __func__, addr, r));
198: }
199:
200: static void gpio_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
201: {
202: struct gpio_state_t *s = opaque;
203: D(printf("%s %x=%x\n", __func__, addr, value));
204:
205: addr >>= 2;
206: switch (addr)
207: {
208: case RW_PA_DOUT:
209: /* Decode nand pins. */
210: s->nand->ale = !!(value & (1 << 6));
211: s->nand->cle = !!(value & (1 << 5));
212: s->nand->ce = !!(value & (1 << 4));
213:
214: s->regs[addr] = value;
215: break;
216:
217: case RW_PD_DOUT:
218: /* Temp sensor clk. */
219: if ((s->regs[addr] ^ value) & 2)
220: tempsensor_clkedge(&s->tempsensor, !!(value & 2),
221: !!(value & 16));
222: s->regs[addr] = value;
223: break;
224:
225: default:
226: s->regs[addr] = value;
227: break;
228: }
229: }
230:
1.1.1.4 ! root 231: static CPUReadMemoryFunc * const gpio_read[] = {
1.1 root 232: NULL, NULL,
233: &gpio_readl,
234: };
235:
1.1.1.4 ! root 236: static CPUWriteMemoryFunc * const gpio_write[] = {
1.1 root 237: NULL, NULL,
238: &gpio_writel,
239: };
240:
241: #define INTMEM_SIZE (128 * 1024)
242:
243: static uint32_t bootstrap_pc;
244: static void main_cpu_reset(void *opaque)
245: {
246: CPUState *env = opaque;
247: cpu_reset(env);
248:
249: env->pc = bootstrap_pc;
250: }
251:
252: static
1.1.1.3 root 253: void axisdev88_init (ram_addr_t ram_size,
1.1 root 254: const char *boot_device,
255: const char *kernel_filename, const char *kernel_cmdline,
256: const char *initrd_filename, const char *cpu_model)
257: {
258: CPUState *env;
1.1.1.3 root 259: DeviceState *dev;
260: SysBusDevice *s;
261: qemu_irq irq[30], nmi[2], *cpu_irq;
1.1 root 262: void *etraxfs_dmac;
263: struct etraxfs_dma_client *eth[2] = {NULL, NULL};
264: int kernel_size;
265: int i;
266: int nand_regs;
267: int gpio_regs;
268: ram_addr_t phys_ram;
269: ram_addr_t phys_intmem;
270:
271: /* init CPUs */
272: if (cpu_model == NULL) {
273: cpu_model = "crisv32";
274: }
275: env = cpu_init(cpu_model);
276: qemu_register_reset(main_cpu_reset, env);
277:
278: /* allocate RAM */
279: phys_ram = qemu_ram_alloc(ram_size);
280: cpu_register_physical_memory(0x40000000, ram_size, phys_ram | IO_MEM_RAM);
281:
282: /* The ETRAX-FS has 128Kb on chip ram, the docs refer to it as the
283: internal memory. */
284: phys_intmem = qemu_ram_alloc(INTMEM_SIZE);
285: cpu_register_physical_memory(0x38000000, INTMEM_SIZE,
286: phys_intmem | IO_MEM_RAM);
287:
288:
289: /* Attach a NAND flash to CS1. */
290: nand_state.nand = nand_init(NAND_MFR_STMICRO, 0x39);
1.1.1.3 root 291: nand_regs = cpu_register_io_memory(nand_read, nand_write, &nand_state);
1.1 root 292: cpu_register_physical_memory(0x10000000, 0x05000000, nand_regs);
293:
294: gpio_state.nand = &nand_state;
1.1.1.3 root 295: gpio_regs = cpu_register_io_memory(gpio_read, gpio_write, &gpio_state);
1.1 root 296: cpu_register_physical_memory(0x3001a000, 0x5c, gpio_regs);
297:
298:
1.1.1.3 root 299: cpu_irq = cris_pic_init_cpu(env);
300: dev = qdev_create(NULL, "etraxfs,pic");
301: /* FIXME: Is there a proper way to signal vectors to the CPU core? */
302: qdev_prop_set_ptr(dev, "interrupt_vector", &env->interrupt_vector);
1.1.1.4 ! root 303: qdev_init_nofail(dev);
1.1.1.3 root 304: s = sysbus_from_qdev(dev);
305: sysbus_mmio_map(s, 0, 0x3001c000);
306: sysbus_connect_irq(s, 0, cpu_irq[0]);
307: sysbus_connect_irq(s, 1, cpu_irq[1]);
308: for (i = 0; i < 30; i++) {
309: irq[i] = qdev_get_gpio_in(dev, i);
310: }
311: nmi[0] = qdev_get_gpio_in(dev, 30);
312: nmi[1] = qdev_get_gpio_in(dev, 31);
313:
314: etraxfs_dmac = etraxfs_dmac_init(0x30000000, 10);
1.1 root 315: for (i = 0; i < 10; i++) {
316: /* On ETRAX, odd numbered channels are inputs. */
1.1.1.3 root 317: etraxfs_dmac_connect(etraxfs_dmac, i, irq + 7 + i, i & 1);
1.1 root 318: }
319:
320: /* Add the two ethernet blocks. */
1.1.1.3 root 321: eth[0] = etraxfs_eth_init(&nd_table[0], 0x30034000, 1);
1.1 root 322: if (nb_nics > 1)
1.1.1.3 root 323: eth[1] = etraxfs_eth_init(&nd_table[1], 0x30036000, 2);
1.1 root 324:
325: /* The DMA Connector block is missing, hardwire things for now. */
326: etraxfs_dmac_connect_client(etraxfs_dmac, 0, eth[0]);
327: etraxfs_dmac_connect_client(etraxfs_dmac, 1, eth[0] + 1);
328: if (eth[1]) {
329: etraxfs_dmac_connect_client(etraxfs_dmac, 6, eth[1]);
330: etraxfs_dmac_connect_client(etraxfs_dmac, 7, eth[1] + 1);
331: }
332:
333: /* 2 timers. */
1.1.1.3 root 334: sysbus_create_varargs("etraxfs,timer", 0x3001e000, irq[0x1b], nmi[1], NULL);
335: sysbus_create_varargs("etraxfs,timer", 0x3005e000, irq[0x1b], nmi[1], NULL);
1.1 root 336:
337: for (i = 0; i < 4; i++) {
1.1.1.3 root 338: sysbus_create_simple("etraxfs,serial", 0x30026000 + i * 0x2000,
339: irq[0x14 + i]);
1.1 root 340: }
341:
342: if (kernel_filename) {
343: uint64_t entry, high;
344: int kcmdline_len;
345:
346: /* Boots a kernel elf binary, os/linux-2.6/vmlinux from the axis
347: devboard SDK. */
348: kernel_size = load_elf(kernel_filename, -0x80000000LL,
1.1.1.4 ! root 349: &entry, NULL, &high, 0, ELF_MACHINE, 0);
1.1 root 350: bootstrap_pc = entry;
351: if (kernel_size < 0) {
352: /* Takes a kimage from the axis devboard SDK. */
1.1.1.3 root 353: kernel_size = load_image_targphys(kernel_filename, 0x40004000,
354: ram_size);
1.1 root 355: bootstrap_pc = 0x40004000;
356: env->regs[9] = 0x40004000 + kernel_size;
357: }
358: env->regs[8] = 0x56902387; /* RAM init magic. */
359:
360: if (kernel_cmdline && (kcmdline_len = strlen(kernel_cmdline))) {
361: if (kcmdline_len > 256) {
362: fprintf(stderr, "Too long CRIS kernel cmdline (max 256)\n");
363: exit(1);
364: }
365: /* Let the kernel know we are modifying the cmdline. */
366: env->regs[10] = 0x87109563;
1.1.1.2 root 367: env->regs[11] = 0x40000000;
1.1.1.4 ! root 368: pstrcpy_targphys("cmdline", env->regs[11], 256, kernel_cmdline);
1.1 root 369: }
370: }
371: env->pc = bootstrap_pc;
372:
373: printf ("pc =%x\n", env->pc);
374: printf ("ram size =%ld\n", ram_size);
375: }
376:
1.1.1.3 root 377: static QEMUMachine axisdev88_machine = {
1.1 root 378: .name = "axis-dev88",
379: .desc = "AXIS devboard 88",
380: .init = axisdev88_init,
381: };
1.1.1.3 root 382:
383: static void axisdev88_machine_init(void)
384: {
385: qemu_register_machine(&axisdev88_machine);
386: }
387:
388: machine_init(axisdev88_machine_init);
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