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1.1 root 1: /*
2: * QEMU DMA emulation
3: *
4: * Copyright (c) 2003-2004 Vassili Karpov (malc)
5: *
6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
1.1.1.3 ! root 24: #include "hw.h"
! 25: #include "isa.h"
1.1 root 26:
27: /* #define DEBUG_DMA */
28:
29: #define dolog(...) fprintf (stderr, "dma: " __VA_ARGS__)
30: #ifdef DEBUG_DMA
31: #define lwarn(...) fprintf (stderr, "dma: " __VA_ARGS__)
32: #define linfo(...) fprintf (stderr, "dma: " __VA_ARGS__)
33: #define ldebug(...) fprintf (stderr, "dma: " __VA_ARGS__)
34: #else
35: #define lwarn(...)
36: #define linfo(...)
37: #define ldebug(...)
38: #endif
39:
40: #define LENOFA(a) ((int) (sizeof(a)/sizeof(a[0])))
41:
42: struct dma_regs {
43: int now[2];
44: uint16_t base[2];
45: uint8_t mode;
46: uint8_t page;
47: uint8_t pageh;
48: uint8_t dack;
49: uint8_t eop;
50: DMA_transfer_handler transfer_handler;
51: void *opaque;
52: };
53:
54: #define ADDR 0
55: #define COUNT 1
56:
57: static struct dma_cont {
58: uint8_t status;
59: uint8_t command;
60: uint8_t mask;
61: uint8_t flip_flop;
62: int dshift;
63: struct dma_regs regs[4];
64: } dma_controllers[2];
65:
66: enum {
67: CMD_MEMORY_TO_MEMORY = 0x01,
68: CMD_FIXED_ADDRESS = 0x02,
69: CMD_BLOCK_CONTROLLER = 0x04,
70: CMD_COMPRESSED_TIME = 0x08,
71: CMD_CYCLIC_PRIORITY = 0x10,
72: CMD_EXTENDED_WRITE = 0x20,
73: CMD_LOW_DREQ = 0x40,
74: CMD_LOW_DACK = 0x80,
75: CMD_NOT_SUPPORTED = CMD_MEMORY_TO_MEMORY | CMD_FIXED_ADDRESS
76: | CMD_COMPRESSED_TIME | CMD_CYCLIC_PRIORITY | CMD_EXTENDED_WRITE
77: | CMD_LOW_DREQ | CMD_LOW_DACK
78:
79: };
80:
81: static int channels[8] = {-1, 2, 3, 1, -1, -1, -1, 0};
82:
83: static void write_page (void *opaque, uint32_t nport, uint32_t data)
84: {
85: struct dma_cont *d = opaque;
86: int ichan;
87:
88: ichan = channels[nport & 7];
89: if (-1 == ichan) {
90: dolog ("invalid channel %#x %#x\n", nport, data);
91: return;
92: }
93: d->regs[ichan].page = data;
94: }
95:
96: static void write_pageh (void *opaque, uint32_t nport, uint32_t data)
97: {
98: struct dma_cont *d = opaque;
99: int ichan;
100:
101: ichan = channels[nport & 7];
102: if (-1 == ichan) {
103: dolog ("invalid channel %#x %#x\n", nport, data);
104: return;
105: }
106: d->regs[ichan].pageh = data;
107: }
108:
109: static uint32_t read_page (void *opaque, uint32_t nport)
110: {
111: struct dma_cont *d = opaque;
112: int ichan;
113:
114: ichan = channels[nport & 7];
115: if (-1 == ichan) {
116: dolog ("invalid channel read %#x\n", nport);
117: return 0;
118: }
119: return d->regs[ichan].page;
120: }
121:
122: static uint32_t read_pageh (void *opaque, uint32_t nport)
123: {
124: struct dma_cont *d = opaque;
125: int ichan;
126:
127: ichan = channels[nport & 7];
128: if (-1 == ichan) {
129: dolog ("invalid channel read %#x\n", nport);
130: return 0;
131: }
132: return d->regs[ichan].pageh;
133: }
134:
135: static inline void init_chan (struct dma_cont *d, int ichan)
136: {
137: struct dma_regs *r;
138:
139: r = d->regs + ichan;
140: r->now[ADDR] = r->base[ADDR] << d->dshift;
141: r->now[COUNT] = 0;
142: }
143:
144: static inline int getff (struct dma_cont *d)
145: {
146: int ff;
147:
148: ff = d->flip_flop;
149: d->flip_flop = !ff;
150: return ff;
151: }
152:
153: static uint32_t read_chan (void *opaque, uint32_t nport)
154: {
155: struct dma_cont *d = opaque;
156: int ichan, nreg, iport, ff, val, dir;
157: struct dma_regs *r;
158:
159: iport = (nport >> d->dshift) & 0x0f;
160: ichan = iport >> 1;
161: nreg = iport & 1;
162: r = d->regs + ichan;
163:
164: dir = ((r->mode >> 5) & 1) ? -1 : 1;
165: ff = getff (d);
166: if (nreg)
167: val = (r->base[COUNT] << d->dshift) - r->now[COUNT];
168: else
169: val = r->now[ADDR] + r->now[COUNT] * dir;
170:
171: ldebug ("read_chan %#x -> %d\n", iport, val);
172: return (val >> (d->dshift + (ff << 3))) & 0xff;
173: }
174:
175: static void write_chan (void *opaque, uint32_t nport, uint32_t data)
176: {
177: struct dma_cont *d = opaque;
178: int iport, ichan, nreg;
179: struct dma_regs *r;
180:
181: iport = (nport >> d->dshift) & 0x0f;
182: ichan = iport >> 1;
183: nreg = iport & 1;
184: r = d->regs + ichan;
185: if (getff (d)) {
186: r->base[nreg] = (r->base[nreg] & 0xff) | ((data << 8) & 0xff00);
187: init_chan (d, ichan);
188: } else {
189: r->base[nreg] = (r->base[nreg] & 0xff00) | (data & 0xff);
190: }
191: }
192:
193: static void write_cont (void *opaque, uint32_t nport, uint32_t data)
194: {
195: struct dma_cont *d = opaque;
196: int iport, ichan = 0;
197:
198: iport = (nport >> d->dshift) & 0x0f;
199: switch (iport) {
200: case 0x08: /* command */
201: if ((data != 0) && (data & CMD_NOT_SUPPORTED)) {
202: dolog ("command %#x not supported\n", data);
203: return;
204: }
205: d->command = data;
206: break;
207:
208: case 0x09:
209: ichan = data & 3;
210: if (data & 4) {
211: d->status |= 1 << (ichan + 4);
212: }
213: else {
214: d->status &= ~(1 << (ichan + 4));
215: }
216: d->status &= ~(1 << ichan);
217: break;
218:
219: case 0x0a: /* single mask */
220: if (data & 4)
221: d->mask |= 1 << (data & 3);
222: else
223: d->mask &= ~(1 << (data & 3));
224: break;
225:
226: case 0x0b: /* mode */
227: {
228: ichan = data & 3;
229: #ifdef DEBUG_DMA
230: {
231: int op, ai, dir, opmode;
232: op = (data >> 2) & 3;
233: ai = (data >> 4) & 1;
234: dir = (data >> 5) & 1;
235: opmode = (data >> 6) & 3;
236:
237: linfo ("ichan %d, op %d, ai %d, dir %d, opmode %d\n",
238: ichan, op, ai, dir, opmode);
239: }
240: #endif
241: d->regs[ichan].mode = data;
242: break;
243: }
244:
245: case 0x0c: /* clear flip flop */
246: d->flip_flop = 0;
247: break;
248:
249: case 0x0d: /* reset */
250: d->flip_flop = 0;
251: d->mask = ~0;
252: d->status = 0;
253: d->command = 0;
254: break;
255:
256: case 0x0e: /* clear mask for all channels */
257: d->mask = 0;
258: break;
259:
260: case 0x0f: /* write mask for all channels */
261: d->mask = data;
262: break;
263:
264: default:
265: dolog ("unknown iport %#x\n", iport);
266: break;
267: }
268:
269: #ifdef DEBUG_DMA
270: if (0xc != iport) {
271: linfo ("write_cont: nport %#06x, ichan % 2d, val %#06x\n",
272: nport, ichan, data);
273: }
274: #endif
275: }
276:
277: static uint32_t read_cont (void *opaque, uint32_t nport)
278: {
279: struct dma_cont *d = opaque;
280: int iport, val;
281:
282: iport = (nport >> d->dshift) & 0x0f;
283: switch (iport) {
284: case 0x08: /* status */
285: val = d->status;
286: d->status &= 0xf0;
287: break;
288: case 0x0f: /* mask */
289: val = d->mask;
290: break;
291: default:
292: val = 0;
293: break;
294: }
295:
296: ldebug ("read_cont: nport %#06x, iport %#04x val %#x\n", nport, iport, val);
297: return val;
298: }
299:
300: int DMA_get_channel_mode (int nchan)
301: {
302: return dma_controllers[nchan > 3].regs[nchan & 3].mode;
303: }
304:
305: void DMA_hold_DREQ (int nchan)
306: {
307: int ncont, ichan;
308:
309: ncont = nchan > 3;
310: ichan = nchan & 3;
311: linfo ("held cont=%d chan=%d\n", ncont, ichan);
312: dma_controllers[ncont].status |= 1 << (ichan + 4);
313: }
314:
315: void DMA_release_DREQ (int nchan)
316: {
317: int ncont, ichan;
318:
319: ncont = nchan > 3;
320: ichan = nchan & 3;
321: linfo ("released cont=%d chan=%d\n", ncont, ichan);
322: dma_controllers[ncont].status &= ~(1 << (ichan + 4));
323: }
324:
325: static void channel_run (int ncont, int ichan)
326: {
327: int n;
328: struct dma_regs *r = &dma_controllers[ncont].regs[ichan];
329: #ifdef DEBUG_DMA
330: int dir, opmode;
331:
332: dir = (r->mode >> 5) & 1;
333: opmode = (r->mode >> 6) & 3;
334:
335: if (dir) {
336: dolog ("DMA in address decrement mode\n");
337: }
338: if (opmode != 1) {
339: dolog ("DMA not in single mode select %#x\n", opmode);
340: }
341: #endif
342:
343: r = dma_controllers[ncont].regs + ichan;
344: n = r->transfer_handler (r->opaque, ichan + (ncont << 2),
345: r->now[COUNT], (r->base[COUNT] + 1) << ncont);
346: r->now[COUNT] = n;
347: ldebug ("dma_pos %d size %d\n", n, (r->base[COUNT] + 1) << ncont);
348: }
349:
350: void DMA_run (void)
351: {
352: struct dma_cont *d;
353: int icont, ichan;
354:
355: d = dma_controllers;
356:
357: for (icont = 0; icont < 2; icont++, d++) {
358: for (ichan = 0; ichan < 4; ichan++) {
359: int mask;
360:
361: mask = 1 << ichan;
362:
363: if ((0 == (d->mask & mask)) && (0 != (d->status & (mask << 4))))
364: channel_run (icont, ichan);
365: }
366: }
367: }
368:
369: void DMA_register_channel (int nchan,
370: DMA_transfer_handler transfer_handler,
371: void *opaque)
372: {
373: struct dma_regs *r;
374: int ichan, ncont;
375:
376: ncont = nchan > 3;
377: ichan = nchan & 3;
378:
379: r = dma_controllers[ncont].regs + ichan;
380: r->transfer_handler = transfer_handler;
381: r->opaque = opaque;
382: }
383:
384: int DMA_read_memory (int nchan, void *buf, int pos, int len)
385: {
386: struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3];
1.1.1.3 ! root 387: target_phys_addr_t addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
1.1 root 388:
389: if (r->mode & 0x20) {
390: int i;
391: uint8_t *p = buf;
392:
393: cpu_physical_memory_read (addr - pos - len, buf, len);
394: /* What about 16bit transfers? */
395: for (i = 0; i < len >> 1; i++) {
396: uint8_t b = p[len - i - 1];
397: p[i] = b;
398: }
399: }
400: else
401: cpu_physical_memory_read (addr + pos, buf, len);
402:
403: return len;
404: }
405:
406: int DMA_write_memory (int nchan, void *buf, int pos, int len)
407: {
408: struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3];
1.1.1.3 ! root 409: target_phys_addr_t addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
1.1 root 410:
411: if (r->mode & 0x20) {
412: int i;
413: uint8_t *p = buf;
414:
415: cpu_physical_memory_write (addr - pos - len, buf, len);
416: /* What about 16bit transfers? */
417: for (i = 0; i < len; i++) {
418: uint8_t b = p[len - i - 1];
419: p[i] = b;
420: }
421: }
422: else
423: cpu_physical_memory_write (addr + pos, buf, len);
424:
425: return len;
426: }
427:
428: /* request the emulator to transfer a new DMA memory block ASAP */
429: void DMA_schedule(int nchan)
430: {
1.1.1.2 root 431: CPUState *env = cpu_single_env;
432: if (env)
433: cpu_interrupt(env, CPU_INTERRUPT_EXIT);
1.1 root 434: }
435:
436: static void dma_reset(void *opaque)
437: {
438: struct dma_cont *d = opaque;
439: write_cont (d, (0x0d << d->dshift), 0);
440: }
441:
442: /* dshift = 0: 8 bit DMA, 1 = 16 bit DMA */
443: static void dma_init2(struct dma_cont *d, int base, int dshift,
444: int page_base, int pageh_base)
445: {
446: const static int page_port_list[] = { 0x1, 0x2, 0x3, 0x7 };
447: int i;
448:
449: d->dshift = dshift;
450: for (i = 0; i < 8; i++) {
451: register_ioport_write (base + (i << dshift), 1, 1, write_chan, d);
452: register_ioport_read (base + (i << dshift), 1, 1, read_chan, d);
453: }
454: for (i = 0; i < LENOFA (page_port_list); i++) {
455: register_ioport_write (page_base + page_port_list[i], 1, 1,
456: write_page, d);
457: register_ioport_read (page_base + page_port_list[i], 1, 1,
458: read_page, d);
459: if (pageh_base >= 0) {
460: register_ioport_write (pageh_base + page_port_list[i], 1, 1,
461: write_pageh, d);
462: register_ioport_read (pageh_base + page_port_list[i], 1, 1,
463: read_pageh, d);
464: }
465: }
466: for (i = 0; i < 8; i++) {
467: register_ioport_write (base + ((i + 8) << dshift), 1, 1,
468: write_cont, d);
469: register_ioport_read (base + ((i + 8) << dshift), 1, 1,
470: read_cont, d);
471: }
472: qemu_register_reset(dma_reset, d);
473: dma_reset(d);
474: }
475:
476: static void dma_save (QEMUFile *f, void *opaque)
477: {
478: struct dma_cont *d = opaque;
479: int i;
480:
481: /* qemu_put_8s (f, &d->status); */
482: qemu_put_8s (f, &d->command);
483: qemu_put_8s (f, &d->mask);
484: qemu_put_8s (f, &d->flip_flop);
1.1.1.3 ! root 485: qemu_put_be32 (f, d->dshift);
1.1 root 486:
487: for (i = 0; i < 4; ++i) {
488: struct dma_regs *r = &d->regs[i];
1.1.1.3 ! root 489: qemu_put_be32 (f, r->now[0]);
! 490: qemu_put_be32 (f, r->now[1]);
1.1 root 491: qemu_put_be16s (f, &r->base[0]);
492: qemu_put_be16s (f, &r->base[1]);
493: qemu_put_8s (f, &r->mode);
494: qemu_put_8s (f, &r->page);
495: qemu_put_8s (f, &r->pageh);
496: qemu_put_8s (f, &r->dack);
497: qemu_put_8s (f, &r->eop);
498: }
499: }
500:
501: static int dma_load (QEMUFile *f, void *opaque, int version_id)
502: {
503: struct dma_cont *d = opaque;
504: int i;
505:
506: if (version_id != 1)
507: return -EINVAL;
508:
509: /* qemu_get_8s (f, &d->status); */
510: qemu_get_8s (f, &d->command);
511: qemu_get_8s (f, &d->mask);
512: qemu_get_8s (f, &d->flip_flop);
1.1.1.3 ! root 513: d->dshift=qemu_get_be32 (f);
1.1 root 514:
515: for (i = 0; i < 4; ++i) {
516: struct dma_regs *r = &d->regs[i];
1.1.1.3 ! root 517: r->now[0]=qemu_get_be32 (f);
! 518: r->now[1]=qemu_get_be32 (f);
1.1 root 519: qemu_get_be16s (f, &r->base[0]);
520: qemu_get_be16s (f, &r->base[1]);
521: qemu_get_8s (f, &r->mode);
522: qemu_get_8s (f, &r->page);
523: qemu_get_8s (f, &r->pageh);
524: qemu_get_8s (f, &r->dack);
525: qemu_get_8s (f, &r->eop);
526: }
527: return 0;
528: }
529:
530: void DMA_init (int high_page_enable)
531: {
532: dma_init2(&dma_controllers[0], 0x00, 0, 0x80,
533: high_page_enable ? 0x480 : -1);
534: dma_init2(&dma_controllers[1], 0xc0, 1, 0x88,
535: high_page_enable ? 0x488 : -1);
536: register_savevm ("dma", 0, 1, dma_save, dma_load, &dma_controllers[0]);
537: register_savevm ("dma", 1, 1, dma_save, dma_load, &dma_controllers[1]);
538: }
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