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1.1.1.2 root 1: /*
2: * QEMU NVRAM emulation for DS1225Y chip
3: *
4: * Copyright (c) 2007-2008 Herv� Poussineau
5: *
6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
24:
1.1.1.6 root 25: #include "sysbus.h"
26: #include "trace.h"
1.1.1.2 root 27:
1.1.1.6 root 28: typedef struct {
29: DeviceState qdev;
1.1.1.2 root 30: uint32_t chip_size;
1.1.1.6 root 31: char *filename;
1.1.1.7 ! root 32: FILE *file;
1.1.1.2 root 33: uint8_t *contents;
1.1.1.6 root 34: } NvRamState;
1.1.1.2 root 35:
36: static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
37: {
1.1.1.6 root 38: NvRamState *s = opaque;
1.1.1.2 root 39: uint32_t val;
40:
41: val = s->contents[addr];
1.1.1.6 root 42: trace_nvram_read(addr, val);
1.1.1.2 root 43: return val;
44: }
45:
46: static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
47: {
48: uint32_t v;
49: v = nvram_readb(opaque, addr);
50: v |= nvram_readb(opaque, addr + 1) << 8;
51: return v;
52: }
53:
54: static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
55: {
56: uint32_t v;
57: v = nvram_readb(opaque, addr);
58: v |= nvram_readb(opaque, addr + 1) << 8;
59: v |= nvram_readb(opaque, addr + 2) << 16;
60: v |= nvram_readb(opaque, addr + 3) << 24;
61: return v;
62: }
63:
64: static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
65: {
1.1.1.6 root 66: NvRamState *s = opaque;
1.1.1.2 root 67:
1.1.1.6 root 68: val &= 0xff;
69: trace_nvram_write(addr, s->contents[addr], val);
1.1.1.2 root 70:
1.1.1.6 root 71: s->contents[addr] = val;
1.1.1.2 root 72: if (s->file) {
1.1.1.7 ! root 73: fseek(s->file, addr, SEEK_SET);
! 74: fputc(val, s->file);
! 75: fflush(s->file);
1.1.1.2 root 76: }
77: }
78:
79: static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t val)
80: {
81: nvram_writeb(opaque, addr, val & 0xff);
82: nvram_writeb(opaque, addr + 1, (val >> 8) & 0xff);
83: }
84:
85: static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
86: {
87: nvram_writeb(opaque, addr, val & 0xff);
88: nvram_writeb(opaque, addr + 1, (val >> 8) & 0xff);
89: nvram_writeb(opaque, addr + 2, (val >> 16) & 0xff);
90: nvram_writeb(opaque, addr + 3, (val >> 24) & 0xff);
91: }
92:
1.1.1.4 root 93: static CPUReadMemoryFunc * const nvram_read[] = {
1.1.1.2 root 94: &nvram_readb,
95: &nvram_readw,
96: &nvram_readl,
97: };
98:
1.1.1.4 root 99: static CPUWriteMemoryFunc * const nvram_write[] = {
1.1.1.2 root 100: &nvram_writeb,
101: &nvram_writew,
102: &nvram_writel,
103: };
104:
1.1.1.6 root 105: static int nvram_post_load(void *opaque, int version_id)
106: {
107: NvRamState *s = opaque;
108:
109: /* Close file, as filename may has changed in load/store process */
110: if (s->file) {
1.1.1.7 ! root 111: fclose(s->file);
1.1.1.6 root 112: }
113:
114: /* Write back nvram contents */
1.1.1.7 ! root 115: s->file = fopen(s->filename, "wb");
1.1.1.6 root 116: if (s->file) {
117: /* Write back contents, as 'wb' mode cleaned the file */
1.1.1.7 ! root 118: if (fwrite(s->contents, s->chip_size, 1, s->file) != 1) {
! 119: printf("nvram_post_load: short write\n");
! 120: }
! 121: fflush(s->file);
1.1.1.6 root 122: }
123:
124: return 0;
125: }
126:
127: static const VMStateDescription vmstate_nvram = {
128: .name = "nvram",
129: .version_id = 0,
130: .minimum_version_id = 0,
131: .minimum_version_id_old = 0,
132: .post_load = nvram_post_load,
133: .fields = (VMStateField[]) {
134: VMSTATE_VARRAY_UINT32(contents, NvRamState, chip_size, 0,
135: vmstate_info_uint8, uint8_t),
136: VMSTATE_END_OF_LIST()
137: }
1.1.1.2 root 138: };
139:
1.1.1.6 root 140: typedef struct {
141: SysBusDevice busdev;
142: NvRamState nvram;
143: } SysBusNvRamState;
144:
145: static int nvram_sysbus_initfn(SysBusDevice *dev)
1.1.1.2 root 146: {
1.1.1.6 root 147: NvRamState *s = &FROM_SYSBUS(SysBusNvRamState, dev)->nvram;
1.1.1.7 ! root 148: FILE *file;
1.1.1.6 root 149: int s_io;
1.1.1.2 root 150:
1.1.1.7 ! root 151: s->contents = g_malloc0(s->chip_size);
1.1.1.6 root 152:
153: s_io = cpu_register_io_memory(nvram_read, nvram_write, s,
154: DEVICE_NATIVE_ENDIAN);
155: sysbus_init_mmio(dev, s->chip_size, s_io);
1.1.1.2 root 156:
157: /* Read current file */
1.1.1.7 ! root 158: file = fopen(s->filename, "rb");
1.1.1.2 root 159: if (file) {
160: /* Read nvram contents */
1.1.1.7 ! root 161: if (fread(s->contents, s->chip_size, 1, file) != 1) {
! 162: printf("nvram_sysbus_initfn: short read\n");
! 163: }
! 164: fclose(file);
1.1.1.2 root 165: }
1.1.1.6 root 166: nvram_post_load(s, 0);
167:
168: return 0;
169: }
170:
171: static SysBusDeviceInfo nvram_sysbus_info = {
172: .qdev.name = "ds1225y",
173: .qdev.size = sizeof(SysBusNvRamState),
174: .qdev.vmsd = &vmstate_nvram,
175: .init = nvram_sysbus_initfn,
176: .qdev.props = (Property[]) {
177: DEFINE_PROP_UINT32("size", SysBusNvRamState, nvram.chip_size, 0x2000),
178: DEFINE_PROP_STRING("filename", SysBusNvRamState, nvram.filename),
179: DEFINE_PROP_END_OF_LIST(),
180: },
181: };
1.1.1.2 root 182:
1.1.1.6 root 183: static void nvram_register(void)
184: {
185: sysbus_register_withprop(&nvram_sysbus_info);
1.1.1.2 root 186: }
1.1.1.6 root 187:
188: device_init(nvram_register)
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