Annotation of qemu/hw/e1000_hw.h, revision 1.1.1.1

1.1       root        1: /*******************************************************************************
                      2: 
                      3:   Intel PRO/1000 Linux driver
                      4:   Copyright(c) 1999 - 2006 Intel Corporation.
                      5: 
                      6:   This program is free software; you can redistribute it and/or modify it
                      7:   under the terms and conditions of the GNU General Public License,
                      8:   version 2, as published by the Free Software Foundation.
                      9: 
                     10:   This program is distributed in the hope it will be useful, but WITHOUT
                     11:   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
                     12:   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
                     13:   more details.
                     14: 
                     15:   You should have received a copy of the GNU General Public License along with
                     16:   this program; if not, write to the Free Software Foundation, Inc.,
                     17:   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
                     18: 
                     19:   The full GNU General Public License is included in this distribution in
                     20:   the file called "COPYING".
                     21: 
                     22:   Contact Information:
                     23:   Linux NICS <linux.nics@intel.com>
                     24:   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
                     25:   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
                     26: 
                     27: *******************************************************************************/
                     28: 
                     29: /* e1000_hw.h
                     30:  * Structures, enums, and macros for the MAC
                     31:  */
                     32: 
                     33: #ifndef _E1000_HW_H_
                     34: #define _E1000_HW_H_
                     35: 
                     36: 
                     37: /* PCI Device IDs */
                     38: #define E1000_DEV_ID_82542               0x1000
                     39: #define E1000_DEV_ID_82543GC_FIBER       0x1001
                     40: #define E1000_DEV_ID_82543GC_COPPER      0x1004
                     41: #define E1000_DEV_ID_82544EI_COPPER      0x1008
                     42: #define E1000_DEV_ID_82544EI_FIBER       0x1009
                     43: #define E1000_DEV_ID_82544GC_COPPER      0x100C
                     44: #define E1000_DEV_ID_82544GC_LOM         0x100D
                     45: #define E1000_DEV_ID_82540EM             0x100E
                     46: #define E1000_DEV_ID_82540EM_LOM         0x1015
                     47: #define E1000_DEV_ID_82540EP_LOM         0x1016
                     48: #define E1000_DEV_ID_82540EP             0x1017
                     49: #define E1000_DEV_ID_82540EP_LP          0x101E
                     50: #define E1000_DEV_ID_82545EM_COPPER      0x100F
                     51: #define E1000_DEV_ID_82545EM_FIBER       0x1011
                     52: #define E1000_DEV_ID_82545GM_COPPER      0x1026
                     53: #define E1000_DEV_ID_82545GM_FIBER       0x1027
                     54: #define E1000_DEV_ID_82545GM_SERDES      0x1028
                     55: #define E1000_DEV_ID_82546EB_COPPER      0x1010
                     56: #define E1000_DEV_ID_82546EB_FIBER       0x1012
                     57: #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
                     58: #define E1000_DEV_ID_82541EI             0x1013
                     59: #define E1000_DEV_ID_82541EI_MOBILE      0x1018
                     60: #define E1000_DEV_ID_82541ER_LOM         0x1014
                     61: #define E1000_DEV_ID_82541ER             0x1078
                     62: #define E1000_DEV_ID_82547GI             0x1075
                     63: #define E1000_DEV_ID_82541GI             0x1076
                     64: #define E1000_DEV_ID_82541GI_MOBILE      0x1077
                     65: #define E1000_DEV_ID_82541GI_LF          0x107C
                     66: #define E1000_DEV_ID_82546GB_COPPER      0x1079
                     67: #define E1000_DEV_ID_82546GB_FIBER       0x107A
                     68: #define E1000_DEV_ID_82546GB_SERDES      0x107B
                     69: #define E1000_DEV_ID_82546GB_PCIE        0x108A
                     70: #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
                     71: #define E1000_DEV_ID_82547EI             0x1019
                     72: #define E1000_DEV_ID_82547EI_MOBILE      0x101A
                     73: #define E1000_DEV_ID_82571EB_COPPER      0x105E
                     74: #define E1000_DEV_ID_82571EB_FIBER       0x105F
                     75: #define E1000_DEV_ID_82571EB_SERDES      0x1060
                     76: #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
                     77: #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
                     78: #define E1000_DEV_ID_82571EB_QUAD_FIBER  0x10A5
                     79: #define E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE  0x10BC
                     80: #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
                     81: #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
                     82: #define E1000_DEV_ID_82572EI_COPPER      0x107D
                     83: #define E1000_DEV_ID_82572EI_FIBER       0x107E
                     84: #define E1000_DEV_ID_82572EI_SERDES      0x107F
                     85: #define E1000_DEV_ID_82572EI             0x10B9
                     86: #define E1000_DEV_ID_82573E              0x108B
                     87: #define E1000_DEV_ID_82573E_IAMT         0x108C
                     88: #define E1000_DEV_ID_82573L              0x109A
                     89: #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
                     90: #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT     0x1096
                     91: #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT     0x1098
                     92: #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT     0x10BA
                     93: #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT     0x10BB
                     94: 
                     95: #define E1000_DEV_ID_ICH8_IGP_M_AMT      0x1049
                     96: #define E1000_DEV_ID_ICH8_IGP_AMT        0x104A
                     97: #define E1000_DEV_ID_ICH8_IGP_C          0x104B
                     98: #define E1000_DEV_ID_ICH8_IFE            0x104C
                     99: #define E1000_DEV_ID_ICH8_IFE_GT         0x10C4
                    100: #define E1000_DEV_ID_ICH8_IFE_G          0x10C5
                    101: #define E1000_DEV_ID_ICH8_IGP_M          0x104D
                    102: 
                    103: /* Register Set. (82543, 82544)
                    104:  *
                    105:  * Registers are defined to be 32 bits and  should be accessed as 32 bit values.
                    106:  * These registers are physically located on the NIC, but are mapped into the
                    107:  * host memory address space.
                    108:  *
                    109:  * RW - register is both readable and writable
                    110:  * RO - register is read only
                    111:  * WO - register is write only
                    112:  * R/clr - register is read only and is cleared when read
                    113:  * A - register array
                    114:  */
                    115: #define E1000_CTRL     0x00000  /* Device Control - RW */
                    116: #define E1000_CTRL_DUP 0x00004  /* Device Control Duplicate (Shadow) - RW */
                    117: #define E1000_STATUS   0x00008  /* Device Status - RO */
                    118: #define E1000_EECD     0x00010  /* EEPROM/Flash Control - RW */
                    119: #define E1000_EERD     0x00014  /* EEPROM Read - RW */
                    120: #define E1000_CTRL_EXT 0x00018  /* Extended Device Control - RW */
                    121: #define E1000_FLA      0x0001C  /* Flash Access - RW */
                    122: #define E1000_MDIC     0x00020  /* MDI Control - RW */
                    123: #define E1000_SCTL     0x00024  /* SerDes Control - RW */
                    124: #define E1000_FEXTNVM  0x00028  /* Future Extended NVM register */
                    125: #define E1000_FCAL     0x00028  /* Flow Control Address Low - RW */
                    126: #define E1000_FCAH     0x0002C  /* Flow Control Address High -RW */
                    127: #define E1000_FCT      0x00030  /* Flow Control Type - RW */
                    128: #define E1000_VET      0x00038  /* VLAN Ether Type - RW */
                    129: #define E1000_ICR      0x000C0  /* Interrupt Cause Read - R/clr */
                    130: #define E1000_ITR      0x000C4  /* Interrupt Throttling Rate - RW */
                    131: #define E1000_ICS      0x000C8  /* Interrupt Cause Set - WO */
                    132: #define E1000_IMS      0x000D0  /* Interrupt Mask Set - RW */
                    133: #define E1000_IMC      0x000D8  /* Interrupt Mask Clear - WO */
                    134: #define E1000_IAM      0x000E0  /* Interrupt Acknowledge Auto Mask */
                    135: #define E1000_RCTL     0x00100  /* RX Control - RW */
                    136: #define E1000_RDTR1    0x02820  /* RX Delay Timer (1) - RW */
                    137: #define E1000_RDBAL1   0x02900  /* RX Descriptor Base Address Low (1) - RW */
                    138: #define E1000_RDBAH1   0x02904  /* RX Descriptor Base Address High (1) - RW */
                    139: #define E1000_RDLEN1   0x02908  /* RX Descriptor Length (1) - RW */
                    140: #define E1000_RDH1     0x02910  /* RX Descriptor Head (1) - RW */
                    141: #define E1000_RDT1     0x02918  /* RX Descriptor Tail (1) - RW */
                    142: #define E1000_FCTTV    0x00170  /* Flow Control Transmit Timer Value - RW */
                    143: #define E1000_TXCW     0x00178  /* TX Configuration Word - RW */
                    144: #define E1000_RXCW     0x00180  /* RX Configuration Word - RO */
                    145: #define E1000_TCTL     0x00400  /* TX Control - RW */
                    146: #define E1000_TCTL_EXT 0x00404  /* Extended TX Control - RW */
                    147: #define E1000_TIPG     0x00410  /* TX Inter-packet gap -RW */
                    148: #define E1000_TBT      0x00448  /* TX Burst Timer - RW */
                    149: #define E1000_AIT      0x00458  /* Adaptive Interframe Spacing Throttle - RW */
                    150: #define E1000_LEDCTL   0x00E00  /* LED Control - RW */
                    151: #define E1000_EXTCNF_CTRL  0x00F00  /* Extended Configuration Control */
                    152: #define E1000_EXTCNF_SIZE  0x00F08  /* Extended Configuration Size */
                    153: #define E1000_PHY_CTRL     0x00F10  /* PHY Control Register in CSR */
                    154: #define FEXTNVM_SW_CONFIG  0x0001
                    155: #define E1000_PBA      0x01000  /* Packet Buffer Allocation - RW */
                    156: #define E1000_PBS      0x01008  /* Packet Buffer Size */
                    157: #define E1000_EEMNGCTL 0x01010  /* MNG EEprom Control */
                    158: #define E1000_FLASH_UPDATES 1000
                    159: #define E1000_EEARBC   0x01024  /* EEPROM Auto Read Bus Control */
                    160: #define E1000_FLASHT   0x01028  /* FLASH Timer Register */
                    161: #define E1000_EEWR     0x0102C  /* EEPROM Write Register - RW */
                    162: #define E1000_FLSWCTL  0x01030  /* FLASH control register */
                    163: #define E1000_FLSWDATA 0x01034  /* FLASH data register */
                    164: #define E1000_FLSWCNT  0x01038  /* FLASH Access Counter */
                    165: #define E1000_FLOP     0x0103C  /* FLASH Opcode Register */
                    166: #define E1000_ERT      0x02008  /* Early Rx Threshold - RW */
                    167: #define E1000_FCRTL    0x02160  /* Flow Control Receive Threshold Low - RW */
                    168: #define E1000_FCRTH    0x02168  /* Flow Control Receive Threshold High - RW */
                    169: #define E1000_PSRCTL   0x02170  /* Packet Split Receive Control - RW */
                    170: #define E1000_RDBAL    0x02800  /* RX Descriptor Base Address Low - RW */
                    171: #define E1000_RDBAH    0x02804  /* RX Descriptor Base Address High - RW */
                    172: #define E1000_RDLEN    0x02808  /* RX Descriptor Length - RW */
                    173: #define E1000_RDH      0x02810  /* RX Descriptor Head - RW */
                    174: #define E1000_RDT      0x02818  /* RX Descriptor Tail - RW */
                    175: #define E1000_RDTR     0x02820  /* RX Delay Timer - RW */
                    176: #define E1000_RDBAL0   E1000_RDBAL /* RX Desc Base Address Low (0) - RW */
                    177: #define E1000_RDBAH0   E1000_RDBAH /* RX Desc Base Address High (0) - RW */
                    178: #define E1000_RDLEN0   E1000_RDLEN /* RX Desc Length (0) - RW */
                    179: #define E1000_RDH0     E1000_RDH   /* RX Desc Head (0) - RW */
                    180: #define E1000_RDT0     E1000_RDT   /* RX Desc Tail (0) - RW */
                    181: #define E1000_RDTR0    E1000_RDTR  /* RX Delay Timer (0) - RW */
                    182: #define E1000_RXDCTL   0x02828  /* RX Descriptor Control queue 0 - RW */
                    183: #define E1000_RXDCTL1  0x02928  /* RX Descriptor Control queue 1 - RW */
                    184: #define E1000_RADV     0x0282C  /* RX Interrupt Absolute Delay Timer - RW */
                    185: #define E1000_RSRPD    0x02C00  /* RX Small Packet Detect - RW */
                    186: #define E1000_RAID     0x02C08  /* Receive Ack Interrupt Delay - RW */
                    187: #define E1000_TXDMAC   0x03000  /* TX DMA Control - RW */
                    188: #define E1000_KABGTXD  0x03004  /* AFE Band Gap Transmit Ref Data */
                    189: #define E1000_TDFH     0x03410  /* TX Data FIFO Head - RW */
                    190: #define E1000_TDFT     0x03418  /* TX Data FIFO Tail - RW */
                    191: #define E1000_TDFHS    0x03420  /* TX Data FIFO Head Saved - RW */
                    192: #define E1000_TDFTS    0x03428  /* TX Data FIFO Tail Saved - RW */
                    193: #define E1000_TDFPC    0x03430  /* TX Data FIFO Packet Count - RW */
                    194: #define E1000_TDBAL    0x03800  /* TX Descriptor Base Address Low - RW */
                    195: #define E1000_TDBAH    0x03804  /* TX Descriptor Base Address High - RW */
                    196: #define E1000_TDLEN    0x03808  /* TX Descriptor Length - RW */
                    197: #define E1000_TDH      0x03810  /* TX Descriptor Head - RW */
                    198: #define E1000_TDT      0x03818  /* TX Descripotr Tail - RW */
                    199: #define E1000_TIDV     0x03820  /* TX Interrupt Delay Value - RW */
                    200: #define E1000_TXDCTL   0x03828  /* TX Descriptor Control - RW */
                    201: #define E1000_TADV     0x0382C  /* TX Interrupt Absolute Delay Val - RW */
                    202: #define E1000_TSPMT    0x03830  /* TCP Segmentation PAD & Min Threshold - RW */
                    203: #define E1000_TARC0    0x03840  /* TX Arbitration Count (0) */
                    204: #define E1000_TDBAL1   0x03900  /* TX Desc Base Address Low (1) - RW */
                    205: #define E1000_TDBAH1   0x03904  /* TX Desc Base Address High (1) - RW */
                    206: #define E1000_TDLEN1   0x03908  /* TX Desc Length (1) - RW */
                    207: #define E1000_TDH1     0x03910  /* TX Desc Head (1) - RW */
                    208: #define E1000_TDT1     0x03918  /* TX Desc Tail (1) - RW */
                    209: #define E1000_TXDCTL1  0x03928  /* TX Descriptor Control (1) - RW */
                    210: #define E1000_TARC1    0x03940  /* TX Arbitration Count (1) */
                    211: #define E1000_CRCERRS  0x04000  /* CRC Error Count - R/clr */
                    212: #define E1000_ALGNERRC 0x04004  /* Alignment Error Count - R/clr */
                    213: #define E1000_SYMERRS  0x04008  /* Symbol Error Count - R/clr */
                    214: #define E1000_RXERRC   0x0400C  /* Receive Error Count - R/clr */
                    215: #define E1000_MPC      0x04010  /* Missed Packet Count - R/clr */
                    216: #define E1000_SCC      0x04014  /* Single Collision Count - R/clr */
                    217: #define E1000_ECOL     0x04018  /* Excessive Collision Count - R/clr */
                    218: #define E1000_MCC      0x0401C  /* Multiple Collision Count - R/clr */
                    219: #define E1000_LATECOL  0x04020  /* Late Collision Count - R/clr */
                    220: #define E1000_COLC     0x04028  /* Collision Count - R/clr */
                    221: #define E1000_DC       0x04030  /* Defer Count - R/clr */
                    222: #define E1000_TNCRS    0x04034  /* TX-No CRS - R/clr */
                    223: #define E1000_SEC      0x04038  /* Sequence Error Count - R/clr */
                    224: #define E1000_CEXTERR  0x0403C  /* Carrier Extension Error Count - R/clr */
                    225: #define E1000_RLEC     0x04040  /* Receive Length Error Count - R/clr */
                    226: #define E1000_XONRXC   0x04048  /* XON RX Count - R/clr */
                    227: #define E1000_XONTXC   0x0404C  /* XON TX Count - R/clr */
                    228: #define E1000_XOFFRXC  0x04050  /* XOFF RX Count - R/clr */
                    229: #define E1000_XOFFTXC  0x04054  /* XOFF TX Count - R/clr */
                    230: #define E1000_FCRUC    0x04058  /* Flow Control RX Unsupported Count- R/clr */
                    231: #define E1000_PRC64    0x0405C  /* Packets RX (64 bytes) - R/clr */
                    232: #define E1000_PRC127   0x04060  /* Packets RX (65-127 bytes) - R/clr */
                    233: #define E1000_PRC255   0x04064  /* Packets RX (128-255 bytes) - R/clr */
                    234: #define E1000_PRC511   0x04068  /* Packets RX (255-511 bytes) - R/clr */
                    235: #define E1000_PRC1023  0x0406C  /* Packets RX (512-1023 bytes) - R/clr */
                    236: #define E1000_PRC1522  0x04070  /* Packets RX (1024-1522 bytes) - R/clr */
                    237: #define E1000_GPRC     0x04074  /* Good Packets RX Count - R/clr */
                    238: #define E1000_BPRC     0x04078  /* Broadcast Packets RX Count - R/clr */
                    239: #define E1000_MPRC     0x0407C  /* Multicast Packets RX Count - R/clr */
                    240: #define E1000_GPTC     0x04080  /* Good Packets TX Count - R/clr */
                    241: #define E1000_GORCL    0x04088  /* Good Octets RX Count Low - R/clr */
                    242: #define E1000_GORCH    0x0408C  /* Good Octets RX Count High - R/clr */
                    243: #define E1000_GOTCL    0x04090  /* Good Octets TX Count Low - R/clr */
                    244: #define E1000_GOTCH    0x04094  /* Good Octets TX Count High - R/clr */
                    245: #define E1000_RNBC     0x040A0  /* RX No Buffers Count - R/clr */
                    246: #define E1000_RUC      0x040A4  /* RX Undersize Count - R/clr */
                    247: #define E1000_RFC      0x040A8  /* RX Fragment Count - R/clr */
                    248: #define E1000_ROC      0x040AC  /* RX Oversize Count - R/clr */
                    249: #define E1000_RJC      0x040B0  /* RX Jabber Count - R/clr */
                    250: #define E1000_MGTPRC   0x040B4  /* Management Packets RX Count - R/clr */
                    251: #define E1000_MGTPDC   0x040B8  /* Management Packets Dropped Count - R/clr */
                    252: #define E1000_MGTPTC   0x040BC  /* Management Packets TX Count - R/clr */
                    253: #define E1000_TORL     0x040C0  /* Total Octets RX Low - R/clr */
                    254: #define E1000_TORH     0x040C4  /* Total Octets RX High - R/clr */
                    255: #define E1000_TOTL     0x040C8  /* Total Octets TX Low - R/clr */
                    256: #define E1000_TOTH     0x040CC  /* Total Octets TX High - R/clr */
                    257: #define E1000_TPR      0x040D0  /* Total Packets RX - R/clr */
                    258: #define E1000_TPT      0x040D4  /* Total Packets TX - R/clr */
                    259: #define E1000_PTC64    0x040D8  /* Packets TX (64 bytes) - R/clr */
                    260: #define E1000_PTC127   0x040DC  /* Packets TX (65-127 bytes) - R/clr */
                    261: #define E1000_PTC255   0x040E0  /* Packets TX (128-255 bytes) - R/clr */
                    262: #define E1000_PTC511   0x040E4  /* Packets TX (256-511 bytes) - R/clr */
                    263: #define E1000_PTC1023  0x040E8  /* Packets TX (512-1023 bytes) - R/clr */
                    264: #define E1000_PTC1522  0x040EC  /* Packets TX (1024-1522 Bytes) - R/clr */
                    265: #define E1000_MPTC     0x040F0  /* Multicast Packets TX Count - R/clr */
                    266: #define E1000_BPTC     0x040F4  /* Broadcast Packets TX Count - R/clr */
                    267: #define E1000_TSCTC    0x040F8  /* TCP Segmentation Context TX - R/clr */
                    268: #define E1000_TSCTFC   0x040FC  /* TCP Segmentation Context TX Fail - R/clr */
                    269: #define E1000_IAC      0x04100  /* Interrupt Assertion Count */
                    270: #define E1000_ICRXPTC  0x04104  /* Interrupt Cause Rx Packet Timer Expire Count */
                    271: #define E1000_ICRXATC  0x04108  /* Interrupt Cause Rx Absolute Timer Expire Count */
                    272: #define E1000_ICTXPTC  0x0410C  /* Interrupt Cause Tx Packet Timer Expire Count */
                    273: #define E1000_ICTXATC  0x04110  /* Interrupt Cause Tx Absolute Timer Expire Count */
                    274: #define E1000_ICTXQEC  0x04118  /* Interrupt Cause Tx Queue Empty Count */
                    275: #define E1000_ICTXQMTC 0x0411C  /* Interrupt Cause Tx Queue Minimum Threshold Count */
                    276: #define E1000_ICRXDMTC 0x04120  /* Interrupt Cause Rx Descriptor Minimum Threshold Count */
                    277: #define E1000_ICRXOC   0x04124  /* Interrupt Cause Receiver Overrun Count */
                    278: #define E1000_RXCSUM   0x05000  /* RX Checksum Control - RW */
                    279: #define E1000_RFCTL    0x05008  /* Receive Filter Control*/
                    280: #define E1000_MTA      0x05200  /* Multicast Table Array - RW Array */
                    281: #define E1000_RA       0x05400  /* Receive Address - RW Array */
                    282: #define E1000_VFTA     0x05600  /* VLAN Filter Table Array - RW Array */
                    283: #define E1000_WUC      0x05800  /* Wakeup Control - RW */
                    284: #define E1000_WUFC     0x05808  /* Wakeup Filter Control - RW */
                    285: #define E1000_WUS      0x05810  /* Wakeup Status - RO */
                    286: #define E1000_MANC     0x05820  /* Management Control - RW */
                    287: #define E1000_IPAV     0x05838  /* IP Address Valid - RW */
                    288: #define E1000_IP4AT    0x05840  /* IPv4 Address Table - RW Array */
                    289: #define E1000_IP6AT    0x05880  /* IPv6 Address Table - RW Array */
                    290: #define E1000_WUPL     0x05900  /* Wakeup Packet Length - RW */
                    291: #define E1000_WUPM     0x05A00  /* Wakeup Packet Memory - RO A */
                    292: #define E1000_FFLT     0x05F00  /* Flexible Filter Length Table - RW Array */
                    293: #define E1000_HOST_IF  0x08800  /* Host Interface */
                    294: #define E1000_FFMT     0x09000  /* Flexible Filter Mask Table - RW Array */
                    295: #define E1000_FFVT     0x09800  /* Flexible Filter Value Table - RW Array */
                    296: 
                    297: #define E1000_KUMCTRLSTA 0x00034 /* MAC-PHY interface - RW */
                    298: #define E1000_MDPHYA     0x0003C  /* PHY address - RW */
                    299: #define E1000_MANC2H     0x05860  /* Managment Control To Host - RW */
                    300: #define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */
                    301: 
                    302: #define E1000_GCR       0x05B00 /* PCI-Ex Control */
                    303: #define E1000_GSCL_1    0x05B10 /* PCI-Ex Statistic Control #1 */
                    304: #define E1000_GSCL_2    0x05B14 /* PCI-Ex Statistic Control #2 */
                    305: #define E1000_GSCL_3    0x05B18 /* PCI-Ex Statistic Control #3 */
                    306: #define E1000_GSCL_4    0x05B1C /* PCI-Ex Statistic Control #4 */
                    307: #define E1000_FACTPS    0x05B30 /* Function Active and Power State to MNG */
                    308: #define E1000_SWSM      0x05B50 /* SW Semaphore */
                    309: #define E1000_FWSM      0x05B54 /* FW Semaphore */
                    310: #define E1000_FFLT_DBG  0x05F04 /* Debug Register */
                    311: #define E1000_HICR      0x08F00 /* Host Inteface Control */
                    312: 
                    313: /* RSS registers */
                    314: #define E1000_CPUVEC    0x02C10 /* CPU Vector Register - RW */
                    315: #define E1000_MRQC      0x05818 /* Multiple Receive Control - RW */
                    316: #define E1000_RETA      0x05C00 /* Redirection Table - RW Array */
                    317: #define E1000_RSSRK     0x05C80 /* RSS Random Key - RW Array */
                    318: #define E1000_RSSIM     0x05864 /* RSS Interrupt Mask */
                    319: #define E1000_RSSIR     0x05868 /* RSS Interrupt Request */
                    320: 
                    321: /* PHY 1000 MII Register/Bit Definitions */
                    322: /* PHY Registers defined by IEEE */
                    323: #define PHY_CTRL         0x00 /* Control Register */
                    324: #define PHY_STATUS       0x01 /* Status Regiser */
                    325: #define PHY_ID1          0x02 /* Phy Id Reg (word 1) */
                    326: #define PHY_ID2          0x03 /* Phy Id Reg (word 2) */
                    327: #define PHY_AUTONEG_ADV  0x04 /* Autoneg Advertisement */
                    328: #define PHY_LP_ABILITY   0x05 /* Link Partner Ability (Base Page) */
                    329: #define PHY_AUTONEG_EXP  0x06 /* Autoneg Expansion Reg */
                    330: #define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */
                    331: #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
                    332: #define PHY_1000T_CTRL   0x09 /* 1000Base-T Control Reg */
                    333: #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
                    334: #define PHY_EXT_STATUS   0x0F /* Extended Status Reg */
                    335: 
                    336: #define MAX_PHY_REG_ADDRESS        0x1F  /* 5 bit address bus (0-0x1F) */
                    337: #define MAX_PHY_MULTI_PAGE_REG     0xF   /* Registers equal on all pages */
                    338: 
                    339: /* M88E1000 Specific Registers */
                    340: #define M88E1000_PHY_SPEC_CTRL     0x10  /* PHY Specific Control Register */
                    341: #define M88E1000_PHY_SPEC_STATUS   0x11  /* PHY Specific Status Register */
                    342: #define M88E1000_INT_ENABLE        0x12  /* Interrupt Enable Register */
                    343: #define M88E1000_INT_STATUS        0x13  /* Interrupt Status Register */
                    344: #define M88E1000_EXT_PHY_SPEC_CTRL 0x14  /* Extended PHY Specific Control */
                    345: #define M88E1000_RX_ERR_CNTR       0x15  /* Receive Error Counter */
                    346: 
                    347: #define M88E1000_PHY_EXT_CTRL      0x1A  /* PHY extend control register */
                    348: #define M88E1000_PHY_PAGE_SELECT   0x1D  /* Reg 29 for page number setting */
                    349: #define M88E1000_PHY_GEN_CONTROL   0x1E  /* Its meaning depends on reg 29 */
                    350: #define M88E1000_PHY_VCO_REG_BIT8  0x100 /* Bits 8 & 11 are adjusted for */
                    351: #define M88E1000_PHY_VCO_REG_BIT11 0x800    /* improved BER performance */
                    352: 
                    353: /* Interrupt Cause Read */
                    354: #define E1000_ICR_TXDW          0x00000001 /* Transmit desc written back */
                    355: #define E1000_ICR_TXQE          0x00000002 /* Transmit Queue empty */
                    356: #define E1000_ICR_LSC           0x00000004 /* Link Status Change */
                    357: #define E1000_ICR_RXSEQ         0x00000008 /* rx sequence error */
                    358: #define E1000_ICR_RXDMT0        0x00000010 /* rx desc min. threshold (0) */
                    359: #define E1000_ICR_RXO           0x00000040 /* rx overrun */
                    360: #define E1000_ICR_RXT0          0x00000080 /* rx timer intr (ring 0) */
                    361: #define E1000_ICR_MDAC          0x00000200 /* MDIO access complete */
                    362: #define E1000_ICR_RXCFG         0x00000400 /* RX /c/ ordered set */
                    363: #define E1000_ICR_GPI_EN0       0x00000800 /* GP Int 0 */
                    364: #define E1000_ICR_GPI_EN1       0x00001000 /* GP Int 1 */
                    365: #define E1000_ICR_GPI_EN2       0x00002000 /* GP Int 2 */
                    366: #define E1000_ICR_GPI_EN3       0x00004000 /* GP Int 3 */
                    367: #define E1000_ICR_TXD_LOW       0x00008000
                    368: #define E1000_ICR_SRPD          0x00010000
                    369: #define E1000_ICR_ACK           0x00020000 /* Receive Ack frame */
                    370: #define E1000_ICR_MNG           0x00040000 /* Manageability event */
                    371: #define E1000_ICR_DOCK          0x00080000 /* Dock/Undock */
                    372: #define E1000_ICR_INT_ASSERTED  0x80000000 /* If this bit asserted, the driver should claim the interrupt */
                    373: #define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* queue 0 Rx descriptor FIFO parity error */
                    374: #define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* queue 0 Tx descriptor FIFO parity error */
                    375: #define E1000_ICR_HOST_ARB_PAR  0x00400000 /* host arb read buffer parity error */
                    376: #define E1000_ICR_PB_PAR        0x00800000 /* packet buffer parity error */
                    377: #define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* queue 1 Rx descriptor FIFO parity error */
                    378: #define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* queue 1 Tx descriptor FIFO parity error */
                    379: #define E1000_ICR_ALL_PARITY    0x03F00000 /* all parity error bits */
                    380: #define E1000_ICR_DSW           0x00000020 /* FW changed the status of DISSW bit in the FWSM */
                    381: #define E1000_ICR_PHYINT        0x00001000 /* LAN connected device generates an interrupt */
                    382: #define E1000_ICR_EPRST         0x00100000 /* ME handware reset occurs */
                    383: 
                    384: /* Interrupt Cause Set */
                    385: #define E1000_ICS_TXDW      E1000_ICR_TXDW      /* Transmit desc written back */
                    386: #define E1000_ICS_TXQE      E1000_ICR_TXQE      /* Transmit Queue empty */
                    387: #define E1000_ICS_LSC       E1000_ICR_LSC       /* Link Status Change */
                    388: #define E1000_ICS_RXSEQ     E1000_ICR_RXSEQ     /* rx sequence error */
                    389: #define E1000_ICS_RXDMT0    E1000_ICR_RXDMT0    /* rx desc min. threshold */
                    390: #define E1000_ICS_RXO       E1000_ICR_RXO       /* rx overrun */
                    391: #define E1000_ICS_RXT0      E1000_ICR_RXT0      /* rx timer intr */
                    392: #define E1000_ICS_MDAC      E1000_ICR_MDAC      /* MDIO access complete */
                    393: #define E1000_ICS_RXCFG     E1000_ICR_RXCFG     /* RX /c/ ordered set */
                    394: #define E1000_ICS_GPI_EN0   E1000_ICR_GPI_EN0   /* GP Int 0 */
                    395: #define E1000_ICS_GPI_EN1   E1000_ICR_GPI_EN1   /* GP Int 1 */
                    396: #define E1000_ICS_GPI_EN2   E1000_ICR_GPI_EN2   /* GP Int 2 */
                    397: #define E1000_ICS_GPI_EN3   E1000_ICR_GPI_EN3   /* GP Int 3 */
                    398: #define E1000_ICS_TXD_LOW   E1000_ICR_TXD_LOW
                    399: #define E1000_ICS_SRPD      E1000_ICR_SRPD
                    400: #define E1000_ICS_ACK       E1000_ICR_ACK       /* Receive Ack frame */
                    401: #define E1000_ICS_MNG       E1000_ICR_MNG       /* Manageability event */
                    402: #define E1000_ICS_DOCK      E1000_ICR_DOCK      /* Dock/Undock */
                    403: #define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
                    404: #define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
                    405: #define E1000_ICS_HOST_ARB_PAR  E1000_ICR_HOST_ARB_PAR  /* host arb read buffer parity error */
                    406: #define E1000_ICS_PB_PAR        E1000_ICR_PB_PAR        /* packet buffer parity error */
                    407: #define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
                    408: #define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
                    409: #define E1000_ICS_DSW       E1000_ICR_DSW
                    410: #define E1000_ICS_PHYINT    E1000_ICR_PHYINT
                    411: #define E1000_ICS_EPRST     E1000_ICR_EPRST
                    412: 
                    413: /* Interrupt Mask Set */
                    414: #define E1000_IMS_TXDW      E1000_ICR_TXDW      /* Transmit desc written back */
                    415: #define E1000_IMS_TXQE      E1000_ICR_TXQE      /* Transmit Queue empty */
                    416: #define E1000_IMS_LSC       E1000_ICR_LSC       /* Link Status Change */
                    417: #define E1000_IMS_RXSEQ     E1000_ICR_RXSEQ     /* rx sequence error */
                    418: #define E1000_IMS_RXDMT0    E1000_ICR_RXDMT0    /* rx desc min. threshold */
                    419: #define E1000_IMS_RXO       E1000_ICR_RXO       /* rx overrun */
                    420: #define E1000_IMS_RXT0      E1000_ICR_RXT0      /* rx timer intr */
                    421: #define E1000_IMS_MDAC      E1000_ICR_MDAC      /* MDIO access complete */
                    422: #define E1000_IMS_RXCFG     E1000_ICR_RXCFG     /* RX /c/ ordered set */
                    423: #define E1000_IMS_GPI_EN0   E1000_ICR_GPI_EN0   /* GP Int 0 */
                    424: #define E1000_IMS_GPI_EN1   E1000_ICR_GPI_EN1   /* GP Int 1 */
                    425: #define E1000_IMS_GPI_EN2   E1000_ICR_GPI_EN2   /* GP Int 2 */
                    426: #define E1000_IMS_GPI_EN3   E1000_ICR_GPI_EN3   /* GP Int 3 */
                    427: #define E1000_IMS_TXD_LOW   E1000_ICR_TXD_LOW
                    428: #define E1000_IMS_SRPD      E1000_ICR_SRPD
                    429: #define E1000_IMS_ACK       E1000_ICR_ACK       /* Receive Ack frame */
                    430: #define E1000_IMS_MNG       E1000_ICR_MNG       /* Manageability event */
                    431: #define E1000_IMS_DOCK      E1000_ICR_DOCK      /* Dock/Undock */
                    432: #define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
                    433: #define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
                    434: #define E1000_IMS_HOST_ARB_PAR  E1000_ICR_HOST_ARB_PAR  /* host arb read buffer parity error */
                    435: #define E1000_IMS_PB_PAR        E1000_ICR_PB_PAR        /* packet buffer parity error */
                    436: #define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
                    437: #define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
                    438: #define E1000_IMS_DSW       E1000_ICR_DSW
                    439: #define E1000_IMS_PHYINT    E1000_ICR_PHYINT
                    440: #define E1000_IMS_EPRST     E1000_ICR_EPRST
                    441: 
                    442: /* Interrupt Mask Clear */
                    443: #define E1000_IMC_TXDW      E1000_ICR_TXDW      /* Transmit desc written back */
                    444: #define E1000_IMC_TXQE      E1000_ICR_TXQE      /* Transmit Queue empty */
                    445: #define E1000_IMC_LSC       E1000_ICR_LSC       /* Link Status Change */
                    446: #define E1000_IMC_RXSEQ     E1000_ICR_RXSEQ     /* rx sequence error */
                    447: #define E1000_IMC_RXDMT0    E1000_ICR_RXDMT0    /* rx desc min. threshold */
                    448: #define E1000_IMC_RXO       E1000_ICR_RXO       /* rx overrun */
                    449: #define E1000_IMC_RXT0      E1000_ICR_RXT0      /* rx timer intr */
                    450: #define E1000_IMC_MDAC      E1000_ICR_MDAC      /* MDIO access complete */
                    451: #define E1000_IMC_RXCFG     E1000_ICR_RXCFG     /* RX /c/ ordered set */
                    452: #define E1000_IMC_GPI_EN0   E1000_ICR_GPI_EN0   /* GP Int 0 */
                    453: #define E1000_IMC_GPI_EN1   E1000_ICR_GPI_EN1   /* GP Int 1 */
                    454: #define E1000_IMC_GPI_EN2   E1000_ICR_GPI_EN2   /* GP Int 2 */
                    455: #define E1000_IMC_GPI_EN3   E1000_ICR_GPI_EN3   /* GP Int 3 */
                    456: #define E1000_IMC_TXD_LOW   E1000_ICR_TXD_LOW
                    457: #define E1000_IMC_SRPD      E1000_ICR_SRPD
                    458: #define E1000_IMC_ACK       E1000_ICR_ACK       /* Receive Ack frame */
                    459: #define E1000_IMC_MNG       E1000_ICR_MNG       /* Manageability event */
                    460: #define E1000_IMC_DOCK      E1000_ICR_DOCK      /* Dock/Undock */
                    461: #define E1000_IMC_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */
                    462: #define E1000_IMC_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */
                    463: #define E1000_IMC_HOST_ARB_PAR  E1000_ICR_HOST_ARB_PAR  /* host arb read buffer parity error */
                    464: #define E1000_IMC_PB_PAR        E1000_ICR_PB_PAR        /* packet buffer parity error */
                    465: #define E1000_IMC_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */
                    466: #define E1000_IMC_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */
                    467: #define E1000_IMC_DSW       E1000_ICR_DSW
                    468: #define E1000_IMC_PHYINT    E1000_ICR_PHYINT
                    469: #define E1000_IMC_EPRST     E1000_ICR_EPRST
                    470: 
                    471: /* Receive Control */
                    472: #define E1000_RCTL_RST            0x00000001    /* Software reset */
                    473: #define E1000_RCTL_EN             0x00000002    /* enable */
                    474: #define E1000_RCTL_SBP            0x00000004    /* store bad packet */
                    475: #define E1000_RCTL_UPE            0x00000008    /* unicast promiscuous enable */
                    476: #define E1000_RCTL_MPE            0x00000010    /* multicast promiscuous enab */
                    477: #define E1000_RCTL_LPE            0x00000020    /* long packet enable */
                    478: #define E1000_RCTL_LBM_NO         0x00000000    /* no loopback mode */
                    479: #define E1000_RCTL_LBM_MAC        0x00000040    /* MAC loopback mode */
                    480: #define E1000_RCTL_LBM_SLP        0x00000080    /* serial link loopback mode */
                    481: #define E1000_RCTL_LBM_TCVR       0x000000C0    /* tcvr loopback mode */
                    482: #define E1000_RCTL_DTYP_MASK      0x00000C00    /* Descriptor type mask */
                    483: #define E1000_RCTL_DTYP_PS        0x00000400    /* Packet Split descriptor */
                    484: #define E1000_RCTL_RDMTS_HALF     0x00000000    /* rx desc min threshold size */
                    485: #define E1000_RCTL_RDMTS_QUAT     0x00000100    /* rx desc min threshold size */
                    486: #define E1000_RCTL_RDMTS_EIGTH    0x00000200    /* rx desc min threshold size */
                    487: #define E1000_RCTL_MO_SHIFT       12            /* multicast offset shift */
                    488: #define E1000_RCTL_MO_0           0x00000000    /* multicast offset 11:0 */
                    489: #define E1000_RCTL_MO_1           0x00001000    /* multicast offset 12:1 */
                    490: #define E1000_RCTL_MO_2           0x00002000    /* multicast offset 13:2 */
                    491: #define E1000_RCTL_MO_3           0x00003000    /* multicast offset 15:4 */
                    492: #define E1000_RCTL_MDR            0x00004000    /* multicast desc ring 0 */
                    493: #define E1000_RCTL_BAM            0x00008000    /* broadcast enable */
                    494: /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
                    495: #define E1000_RCTL_SZ_2048        0x00000000    /* rx buffer size 2048 */
                    496: #define E1000_RCTL_SZ_1024        0x00010000    /* rx buffer size 1024 */
                    497: #define E1000_RCTL_SZ_512         0x00020000    /* rx buffer size 512 */
                    498: #define E1000_RCTL_SZ_256         0x00030000    /* rx buffer size 256 */
                    499: /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
                    500: #define E1000_RCTL_SZ_16384       0x00010000    /* rx buffer size 16384 */
                    501: #define E1000_RCTL_SZ_8192        0x00020000    /* rx buffer size 8192 */
                    502: #define E1000_RCTL_SZ_4096        0x00030000    /* rx buffer size 4096 */
                    503: #define E1000_RCTL_VFE            0x00040000    /* vlan filter enable */
                    504: #define E1000_RCTL_CFIEN          0x00080000    /* canonical form enable */
                    505: #define E1000_RCTL_CFI            0x00100000    /* canonical form indicator */
                    506: #define E1000_RCTL_DPF            0x00400000    /* discard pause frames */
                    507: #define E1000_RCTL_PMCF           0x00800000    /* pass MAC control frames */
                    508: #define E1000_RCTL_BSEX           0x02000000    /* Buffer size extension */
                    509: #define E1000_RCTL_SECRC          0x04000000    /* Strip Ethernet CRC */
                    510: #define E1000_RCTL_FLXBUF_MASK    0x78000000    /* Flexible buffer size */
                    511: #define E1000_RCTL_FLXBUF_SHIFT   27            /* Flexible buffer shift */
                    512: 
                    513: 
                    514: #define E1000_EEPROM_SWDPIN0   0x0001   /* SWDPIN 0 EEPROM Value */
                    515: #define E1000_EEPROM_LED_LOGIC 0x0020   /* Led Logic Word */
                    516: #define E1000_EEPROM_RW_REG_DATA   16   /* Offset to data in EEPROM read/write registers */
                    517: #define E1000_EEPROM_RW_REG_DONE   0x10 /* Offset to READ/WRITE done bit */
                    518: #define E1000_EEPROM_RW_REG_START  1    /* First bit for telling part to start operation */
                    519: #define E1000_EEPROM_RW_ADDR_SHIFT 8    /* Shift to the address bits */
                    520: #define E1000_EEPROM_POLL_WRITE    1    /* Flag for polling for write complete */
                    521: #define E1000_EEPROM_POLL_READ     0    /* Flag for polling for read complete */
                    522: /* Register Bit Masks */
                    523: /* Device Control */
                    524: #define E1000_CTRL_FD       0x00000001  /* Full duplex.0=half; 1=full */
                    525: #define E1000_CTRL_BEM      0x00000002  /* Endian Mode.0=little,1=big */
                    526: #define E1000_CTRL_PRIOR    0x00000004  /* Priority on PCI. 0=rx,1=fair */
                    527: #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */
                    528: #define E1000_CTRL_LRST     0x00000008  /* Link reset. 0=normal,1=reset */
                    529: #define E1000_CTRL_TME      0x00000010  /* Test mode. 0=normal,1=test */
                    530: #define E1000_CTRL_SLE      0x00000020  /* Serial Link on 0=dis,1=en */
                    531: #define E1000_CTRL_ASDE     0x00000020  /* Auto-speed detect enable */
                    532: #define E1000_CTRL_SLU      0x00000040  /* Set link up (Force Link) */
                    533: #define E1000_CTRL_ILOS     0x00000080  /* Invert Loss-Of Signal */
                    534: #define E1000_CTRL_SPD_SEL  0x00000300  /* Speed Select Mask */
                    535: #define E1000_CTRL_SPD_10   0x00000000  /* Force 10Mb */
                    536: #define E1000_CTRL_SPD_100  0x00000100  /* Force 100Mb */
                    537: #define E1000_CTRL_SPD_1000 0x00000200  /* Force 1Gb */
                    538: #define E1000_CTRL_BEM32    0x00000400  /* Big Endian 32 mode */
                    539: #define E1000_CTRL_FRCSPD   0x00000800  /* Force Speed */
                    540: #define E1000_CTRL_FRCDPX   0x00001000  /* Force Duplex */
                    541: #define E1000_CTRL_D_UD_EN  0x00002000  /* Dock/Undock enable */
                    542: #define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock indication in SDP[0] */
                    543: #define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through PHYRST_N pin */
                    544: #define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external LINK_0 and LINK_1 pins */
                    545: #define E1000_CTRL_SWDPIN0  0x00040000  /* SWDPIN 0 value */
                    546: #define E1000_CTRL_SWDPIN1  0x00080000  /* SWDPIN 1 value */
                    547: #define E1000_CTRL_SWDPIN2  0x00100000  /* SWDPIN 2 value */
                    548: #define E1000_CTRL_SWDPIN3  0x00200000  /* SWDPIN 3 value */
                    549: #define E1000_CTRL_SWDPIO0  0x00400000  /* SWDPIN 0 Input or output */
                    550: #define E1000_CTRL_SWDPIO1  0x00800000  /* SWDPIN 1 input or output */
                    551: #define E1000_CTRL_SWDPIO2  0x01000000  /* SWDPIN 2 input or output */
                    552: #define E1000_CTRL_SWDPIO3  0x02000000  /* SWDPIN 3 input or output */
                    553: #define E1000_CTRL_RST      0x04000000  /* Global reset */
                    554: #define E1000_CTRL_RFCE     0x08000000  /* Receive Flow Control enable */
                    555: #define E1000_CTRL_TFCE     0x10000000  /* Transmit flow control enable */
                    556: #define E1000_CTRL_RTE      0x20000000  /* Routing tag enable */
                    557: #define E1000_CTRL_VME      0x40000000  /* IEEE VLAN mode enable */
                    558: #define E1000_CTRL_PHY_RST  0x80000000  /* PHY Reset */
                    559: #define E1000_CTRL_SW2FW_INT 0x02000000  /* Initiate an interrupt to manageability engine */
                    560: 
                    561: /* Device Status */
                    562: #define E1000_STATUS_FD         0x00000001      /* Full duplex.0=half,1=full */
                    563: #define E1000_STATUS_LU         0x00000002      /* Link up.0=no,1=link */
                    564: #define E1000_STATUS_FUNC_MASK  0x0000000C      /* PCI Function Mask */
                    565: #define E1000_STATUS_FUNC_SHIFT 2
                    566: #define E1000_STATUS_FUNC_0     0x00000000      /* Function 0 */
                    567: #define E1000_STATUS_FUNC_1     0x00000004      /* Function 1 */
                    568: #define E1000_STATUS_TXOFF      0x00000010      /* transmission paused */
                    569: #define E1000_STATUS_TBIMODE    0x00000020      /* TBI mode */
                    570: #define E1000_STATUS_SPEED_MASK 0x000000C0
                    571: #define E1000_STATUS_SPEED_10   0x00000000      /* Speed 10Mb/s */
                    572: #define E1000_STATUS_SPEED_100  0x00000040      /* Speed 100Mb/s */
                    573: #define E1000_STATUS_SPEED_1000 0x00000080      /* Speed 1000Mb/s */
                    574: #define E1000_STATUS_LAN_INIT_DONE 0x00000200   /* Lan Init Completion
                    575:                                                    by EEPROM/Flash */
                    576: #define E1000_STATUS_ASDV       0x00000300      /* Auto speed detect value */
                    577: #define E1000_STATUS_DOCK_CI    0x00000800      /* Change in Dock/Undock state. Clear on write '0'. */
                    578: #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */
                    579: #define E1000_STATUS_MTXCKOK    0x00000400      /* MTX clock running OK */
                    580: #define E1000_STATUS_PCI66      0x00000800      /* In 66Mhz slot */
                    581: #define E1000_STATUS_BUS64      0x00001000      /* In 64 bit slot */
                    582: #define E1000_STATUS_PCIX_MODE  0x00002000      /* PCI-X mode */
                    583: #define E1000_STATUS_PCIX_SPEED 0x0000C000      /* PCI-X bus speed */
                    584: #define E1000_STATUS_BMC_SKU_0  0x00100000 /* BMC USB redirect disabled */
                    585: #define E1000_STATUS_BMC_SKU_1  0x00200000 /* BMC SRAM disabled */
                    586: #define E1000_STATUS_BMC_SKU_2  0x00400000 /* BMC SDRAM disabled */
                    587: #define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */
                    588: #define E1000_STATUS_BMC_LITE   0x01000000 /* BMC external code execution disabled */
                    589: #define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */
                    590: #define E1000_STATUS_FUSE_8       0x04000000
                    591: #define E1000_STATUS_FUSE_9       0x08000000
                    592: #define E1000_STATUS_SERDES0_DIS  0x10000000 /* SERDES disabled on port 0 */
                    593: #define E1000_STATUS_SERDES1_DIS  0x20000000 /* SERDES disabled on port 1 */
                    594: 
                    595: /* EEPROM/Flash Control */
                    596: #define E1000_EECD_SK        0x00000001 /* EEPROM Clock */
                    597: #define E1000_EECD_CS        0x00000002 /* EEPROM Chip Select */
                    598: #define E1000_EECD_DI        0x00000004 /* EEPROM Data In */
                    599: #define E1000_EECD_DO        0x00000008 /* EEPROM Data Out */
                    600: #define E1000_EECD_FWE_MASK  0x00000030
                    601: #define E1000_EECD_FWE_DIS   0x00000010 /* Disable FLASH writes */
                    602: #define E1000_EECD_FWE_EN    0x00000020 /* Enable FLASH writes */
                    603: #define E1000_EECD_FWE_SHIFT 4
                    604: #define E1000_EECD_REQ       0x00000040 /* EEPROM Access Request */
                    605: #define E1000_EECD_GNT       0x00000080 /* EEPROM Access Grant */
                    606: #define E1000_EECD_PRES      0x00000100 /* EEPROM Present */
                    607: #define E1000_EECD_SIZE      0x00000200 /* EEPROM Size (0=64 word 1=256 word) */
                    608: #define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type
                    609:                                          * (0-small, 1-large) */
                    610: #define E1000_EECD_TYPE      0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */
                    611: #ifndef E1000_EEPROM_GRANT_ATTEMPTS
                    612: #define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
                    613: #endif
                    614: #define E1000_EECD_AUTO_RD          0x00000200  /* EEPROM Auto Read done */
                    615: #define E1000_EECD_SIZE_EX_MASK     0x00007800  /* EEprom Size */
                    616: #define E1000_EECD_SIZE_EX_SHIFT    11
                    617: #define E1000_EECD_NVADDS    0x00018000 /* NVM Address Size */
                    618: #define E1000_EECD_SELSHAD   0x00020000 /* Select Shadow RAM */
                    619: #define E1000_EECD_INITSRAM  0x00040000 /* Initialize Shadow RAM */
                    620: #define E1000_EECD_FLUPD     0x00080000 /* Update FLASH */
                    621: #define E1000_EECD_AUPDEN    0x00100000 /* Enable Autonomous FLASH update */
                    622: #define E1000_EECD_SHADV     0x00200000 /* Shadow RAM Data Valid */
                    623: #define E1000_EECD_SEC1VAL   0x00400000 /* Sector One Valid */
                    624: #define E1000_EECD_SECVAL_SHIFT      22
                    625: #define E1000_STM_OPCODE     0xDB00
                    626: #define E1000_HICR_FW_RESET  0xC0
                    627: 
                    628: #define E1000_SHADOW_RAM_WORDS     2048
                    629: #define E1000_ICH_NVM_SIG_WORD     0x13
                    630: #define E1000_ICH_NVM_SIG_MASK     0xC0
                    631: 
                    632: /* MDI Control */
                    633: #define E1000_MDIC_DATA_MASK 0x0000FFFF
                    634: #define E1000_MDIC_REG_MASK  0x001F0000
                    635: #define E1000_MDIC_REG_SHIFT 16
                    636: #define E1000_MDIC_PHY_MASK  0x03E00000
                    637: #define E1000_MDIC_PHY_SHIFT 21
                    638: #define E1000_MDIC_OP_WRITE  0x04000000
                    639: #define E1000_MDIC_OP_READ   0x08000000
                    640: #define E1000_MDIC_READY     0x10000000
                    641: #define E1000_MDIC_INT_EN    0x20000000
                    642: #define E1000_MDIC_ERROR     0x40000000
                    643: 
                    644: /* EEPROM Commands - Microwire */
                    645: #define EEPROM_READ_OPCODE_MICROWIRE  0x6  /* EEPROM read opcode */
                    646: #define EEPROM_WRITE_OPCODE_MICROWIRE 0x5  /* EEPROM write opcode */
                    647: #define EEPROM_ERASE_OPCODE_MICROWIRE 0x7  /* EEPROM erase opcode */
                    648: #define EEPROM_EWEN_OPCODE_MICROWIRE  0x13 /* EEPROM erase/write enable */
                    649: #define EEPROM_EWDS_OPCODE_MICROWIRE  0x10 /* EEPROM erast/write disable */
                    650: 
                    651: /* EEPROM Word Offsets */
                    652: #define EEPROM_COMPAT                 0x0003
                    653: #define EEPROM_ID_LED_SETTINGS        0x0004
                    654: #define EEPROM_VERSION                0x0005
                    655: #define EEPROM_SERDES_AMPLITUDE       0x0006 /* For SERDES output amplitude adjustment. */
                    656: #define EEPROM_PHY_CLASS_WORD         0x0007
                    657: #define EEPROM_INIT_CONTROL1_REG      0x000A
                    658: #define EEPROM_INIT_CONTROL2_REG      0x000F
                    659: #define EEPROM_SWDEF_PINS_CTRL_PORT_1 0x0010
                    660: #define EEPROM_INIT_CONTROL3_PORT_B   0x0014
                    661: #define EEPROM_INIT_3GIO_3            0x001A
                    662: #define EEPROM_SWDEF_PINS_CTRL_PORT_0 0x0020
                    663: #define EEPROM_INIT_CONTROL3_PORT_A   0x0024
                    664: #define EEPROM_CFG                    0x0012
                    665: #define EEPROM_FLASH_VERSION          0x0032
                    666: #define EEPROM_CHECKSUM_REG           0x003F
                    667: 
                    668: #define E1000_EEPROM_CFG_DONE         0x00040000   /* MNG config cycle done */
                    669: #define E1000_EEPROM_CFG_DONE_PORT_1  0x00080000   /* ...for second port */
                    670: 
                    671: /* Transmit Descriptor */
                    672: struct e1000_tx_desc {
                    673:     uint64_t buffer_addr;       /* Address of the descriptor's data buffer */
                    674:     union {
                    675:         uint32_t data;
                    676:         struct {
                    677:             uint16_t length;    /* Data buffer length */
                    678:             uint8_t cso;        /* Checksum offset */
                    679:             uint8_t cmd;        /* Descriptor control */
                    680:         } flags;
                    681:     } lower;
                    682:     union {
                    683:         uint32_t data;
                    684:         struct {
                    685:             uint8_t status;     /* Descriptor status */
                    686:             uint8_t css;        /* Checksum start */
                    687:             uint16_t special;
                    688:         } fields;
                    689:     } upper;
                    690: };
                    691: 
                    692: /* Transmit Descriptor bit definitions */
                    693: #define E1000_TXD_DTYP_D     0x00100000 /* Data Descriptor */
                    694: #define E1000_TXD_DTYP_C     0x00000000 /* Context Descriptor */
                    695: #define E1000_TXD_POPTS_IXSM 0x01       /* Insert IP checksum */
                    696: #define E1000_TXD_POPTS_TXSM 0x02       /* Insert TCP/UDP checksum */
                    697: #define E1000_TXD_CMD_EOP    0x01000000 /* End of Packet */
                    698: #define E1000_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */
                    699: #define E1000_TXD_CMD_IC     0x04000000 /* Insert Checksum */
                    700: #define E1000_TXD_CMD_RS     0x08000000 /* Report Status */
                    701: #define E1000_TXD_CMD_RPS    0x10000000 /* Report Packet Sent */
                    702: #define E1000_TXD_CMD_DEXT   0x20000000 /* Descriptor extension (0 = legacy) */
                    703: #define E1000_TXD_CMD_VLE    0x40000000 /* Add VLAN tag */
                    704: #define E1000_TXD_CMD_IDE    0x80000000 /* Enable Tidv register */
                    705: #define E1000_TXD_STAT_DD    0x00000001 /* Descriptor Done */
                    706: #define E1000_TXD_STAT_EC    0x00000002 /* Excess Collisions */
                    707: #define E1000_TXD_STAT_LC    0x00000004 /* Late Collisions */
                    708: #define E1000_TXD_STAT_TU    0x00000008 /* Transmit underrun */
                    709: #define E1000_TXD_CMD_TCP    0x01000000 /* TCP packet */
                    710: #define E1000_TXD_CMD_IP     0x02000000 /* IP packet */
                    711: #define E1000_TXD_CMD_TSE    0x04000000 /* TCP Seg enable */
                    712: #define E1000_TXD_STAT_TC    0x00000004 /* Tx Underrun */
                    713: 
                    714: /* Transmit Control */
                    715: #define E1000_TCTL_RST    0x00000001    /* software reset */
                    716: #define E1000_TCTL_EN     0x00000002    /* enable tx */
                    717: #define E1000_TCTL_BCE    0x00000004    /* busy check enable */
                    718: #define E1000_TCTL_PSP    0x00000008    /* pad short packets */
                    719: #define E1000_TCTL_CT     0x00000ff0    /* collision threshold */
                    720: #define E1000_TCTL_COLD   0x003ff000    /* collision distance */
                    721: #define E1000_TCTL_SWXOFF 0x00400000    /* SW Xoff transmission */
                    722: #define E1000_TCTL_PBE    0x00800000    /* Packet Burst Enable */
                    723: #define E1000_TCTL_RTLC   0x01000000    /* Re-transmit on late collision */
                    724: #define E1000_TCTL_NRTU   0x02000000    /* No Re-transmit on underrun */
                    725: #define E1000_TCTL_MULR   0x10000000    /* Multiple request support */
                    726: 
                    727: /* Receive Descriptor */
                    728: struct e1000_rx_desc {
                    729:     uint64_t buffer_addr; /* Address of the descriptor's data buffer */
                    730:     uint16_t length;     /* Length of data DMAed into data buffer */
                    731:     uint16_t csum;       /* Packet checksum */
                    732:     uint8_t status;      /* Descriptor status */
                    733:     uint8_t errors;      /* Descriptor Errors */
                    734:     uint16_t special;
                    735: };
                    736: 
                    737: /* Receive Descriptor bit definitions */
                    738: #define E1000_RXD_STAT_DD       0x01    /* Descriptor Done */
                    739: #define E1000_RXD_STAT_EOP      0x02    /* End of Packet */
                    740: #define E1000_RXD_STAT_IXSM     0x04    /* Ignore checksum */
                    741: #define E1000_RXD_STAT_VP       0x08    /* IEEE VLAN Packet */
                    742: #define E1000_RXD_STAT_UDPCS    0x10    /* UDP xsum caculated */
                    743: #define E1000_RXD_STAT_TCPCS    0x20    /* TCP xsum calculated */
                    744: #define E1000_RXD_STAT_IPCS     0x40    /* IP xsum calculated */
                    745: #define E1000_RXD_STAT_PIF      0x80    /* passed in-exact filter */
                    746: #define E1000_RXD_STAT_IPIDV    0x200   /* IP identification valid */
                    747: #define E1000_RXD_STAT_UDPV     0x400   /* Valid UDP checksum */
                    748: #define E1000_RXD_STAT_ACK      0x8000  /* ACK Packet indication */
                    749: #define E1000_RXD_ERR_CE        0x01    /* CRC Error */
                    750: #define E1000_RXD_ERR_SE        0x02    /* Symbol Error */
                    751: #define E1000_RXD_ERR_SEQ       0x04    /* Sequence Error */
                    752: #define E1000_RXD_ERR_CXE       0x10    /* Carrier Extension Error */
                    753: #define E1000_RXD_ERR_TCPE      0x20    /* TCP/UDP Checksum Error */
                    754: #define E1000_RXD_ERR_IPE       0x40    /* IP Checksum Error */
                    755: #define E1000_RXD_ERR_RXE       0x80    /* Rx Data Error */
                    756: #define E1000_RXD_SPC_VLAN_MASK 0x0FFF  /* VLAN ID is in lower 12 bits */
                    757: #define E1000_RXD_SPC_PRI_MASK  0xE000  /* Priority is in upper 3 bits */
                    758: #define E1000_RXD_SPC_PRI_SHIFT 13
                    759: #define E1000_RXD_SPC_CFI_MASK  0x1000  /* CFI is bit 12 */
                    760: #define E1000_RXD_SPC_CFI_SHIFT 12
                    761: 
                    762: #define E1000_RXDEXT_STATERR_CE    0x01000000
                    763: #define E1000_RXDEXT_STATERR_SE    0x02000000
                    764: #define E1000_RXDEXT_STATERR_SEQ   0x04000000
                    765: #define E1000_RXDEXT_STATERR_CXE   0x10000000
                    766: #define E1000_RXDEXT_STATERR_TCPE  0x20000000
                    767: #define E1000_RXDEXT_STATERR_IPE   0x40000000
                    768: #define E1000_RXDEXT_STATERR_RXE   0x80000000
                    769: 
                    770: #define E1000_RXDPS_HDRSTAT_HDRSP        0x00008000
                    771: #define E1000_RXDPS_HDRSTAT_HDRLEN_MASK  0x000003FF
                    772: 
                    773: /* Receive Address */
                    774: #define E1000_RAH_AV  0x80000000        /* Receive descriptor valid */
                    775: 
                    776: /* Offload Context Descriptor */
                    777: struct e1000_context_desc {
                    778:     union {
                    779:         uint32_t ip_config;
                    780:         struct {
                    781:             uint8_t ipcss;      /* IP checksum start */
                    782:             uint8_t ipcso;      /* IP checksum offset */
                    783:             uint16_t ipcse;     /* IP checksum end */
                    784:         } ip_fields;
                    785:     } lower_setup;
                    786:     union {
                    787:         uint32_t tcp_config;
                    788:         struct {
                    789:             uint8_t tucss;      /* TCP checksum start */
                    790:             uint8_t tucso;      /* TCP checksum offset */
                    791:             uint16_t tucse;     /* TCP checksum end */
                    792:         } tcp_fields;
                    793:     } upper_setup;
                    794:     uint32_t cmd_and_length;    /* */
                    795:     union {
                    796:         uint32_t data;
                    797:         struct {
                    798:             uint8_t status;     /* Descriptor status */
                    799:             uint8_t hdr_len;    /* Header length */
                    800:             uint16_t mss;       /* Maximum segment size */
                    801:         } fields;
                    802:     } tcp_seg_setup;
                    803: };
                    804: 
                    805: /* Offload data descriptor */
                    806: struct e1000_data_desc {
                    807:     uint64_t buffer_addr;       /* Address of the descriptor's buffer address */
                    808:     union {
                    809:         uint32_t data;
                    810:         struct {
                    811:             uint16_t length;    /* Data buffer length */
                    812:             uint8_t typ_len_ext;        /* */
                    813:             uint8_t cmd;        /* */
                    814:         } flags;
                    815:     } lower;
                    816:     union {
                    817:         uint32_t data;
                    818:         struct {
                    819:             uint8_t status;     /* Descriptor status */
                    820:             uint8_t popts;      /* Packet Options */
                    821:             uint16_t special;   /* */
                    822:         } fields;
                    823:     } upper;
                    824: };
                    825: 
                    826: /* Management Control */
                    827: #define E1000_MANC_SMBUS_EN      0x00000001 /* SMBus Enabled - RO */
                    828: #define E1000_MANC_ASF_EN        0x00000002 /* ASF Enabled - RO */
                    829: #define E1000_MANC_R_ON_FORCE    0x00000004 /* Reset on Force TCO - RO */
                    830: #define E1000_MANC_RMCP_EN       0x00000100 /* Enable RCMP 026Fh Filtering */
                    831: #define E1000_MANC_0298_EN       0x00000200 /* Enable RCMP 0298h Filtering */
                    832: #define E1000_MANC_IPV4_EN       0x00000400 /* Enable IPv4 */
                    833: #define E1000_MANC_IPV6_EN       0x00000800 /* Enable IPv6 */
                    834: #define E1000_MANC_SNAP_EN       0x00001000 /* Accept LLC/SNAP */
                    835: #define E1000_MANC_ARP_EN        0x00002000 /* Enable ARP Request Filtering */
                    836: #define E1000_MANC_NEIGHBOR_EN   0x00004000 /* Enable Neighbor Discovery
                    837:                                              * Filtering */
                    838: #define E1000_MANC_ARP_RES_EN    0x00008000 /* Enable ARP response Filtering */
                    839: #define E1000_MANC_TCO_RESET     0x00010000 /* TCO Reset Occurred */
                    840: #define E1000_MANC_RCV_TCO_EN    0x00020000 /* Receive TCO Packets Enabled */
                    841: #define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
                    842: #define E1000_MANC_RCV_ALL       0x00080000 /* Receive All Enabled */
                    843: #define E1000_MANC_BLK_PHY_RST_ON_IDE   0x00040000 /* Block phy resets */
                    844: #define E1000_MANC_EN_MAC_ADDR_FILTER   0x00100000 /* Enable MAC address
                    845:                                                     * filtering */
                    846: #define E1000_MANC_EN_MNG2HOST   0x00200000 /* Enable MNG packets to host
                    847:                                              * memory */
                    848: #define E1000_MANC_EN_IP_ADDR_FILTER    0x00400000 /* Enable IP address
                    849:                                                     * filtering */
                    850: #define E1000_MANC_EN_XSUM_FILTER   0x00800000 /* Enable checksum filtering */
                    851: #define E1000_MANC_BR_EN         0x01000000 /* Enable broadcast filtering */
                    852: #define E1000_MANC_SMB_REQ       0x01000000 /* SMBus Request */
                    853: #define E1000_MANC_SMB_GNT       0x02000000 /* SMBus Grant */
                    854: #define E1000_MANC_SMB_CLK_IN    0x04000000 /* SMBus Clock In */
                    855: #define E1000_MANC_SMB_DATA_IN   0x08000000 /* SMBus Data In */
                    856: #define E1000_MANC_SMB_DATA_OUT  0x10000000 /* SMBus Data Out */
                    857: #define E1000_MANC_SMB_CLK_OUT   0x20000000 /* SMBus Clock Out */
                    858: 
                    859: #define E1000_MANC_SMB_DATA_OUT_SHIFT  28 /* SMBus Data Out Shift */
                    860: #define E1000_MANC_SMB_CLK_OUT_SHIFT   29 /* SMBus Clock Out Shift */
                    861: 
                    862: /* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */
                    863: #define EEPROM_SUM 0xBABA
                    864: 
                    865: #endif /* _E1000_HW_H_ */

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