Diff for /qemu/hw/eccmemctl.c between versions 1.1.1.1 and 1.1.1.2

version 1.1.1.1, 2018/04/24 16:48:58 version 1.1.1.2, 2018/04/24 16:53:58
Line 40 Line 40
  * SMC (version 0, implementation 2) SS-10SX and SS-20   * SMC (version 0, implementation 2) SS-10SX and SS-20
  */   */
   
 /* Register offsets */  #define ECC_MCC        0x00000000
 #define ECC_FCR_REG    0  #define ECC_EMC        0x10000000
 #define ECC_FSR_REG    8  #define ECC_SMC        0x20000000
 #define ECC_FAR0_REG   16  
 #define ECC_FAR1_REG   20  /* Register indexes */
 #define ECC_DIAG_REG   24  #define ECC_MER        0               /* Memory Enable Register */
   #define ECC_MDR        1               /* Memory Delay Register */
   #define ECC_MFSR       2               /* Memory Fault Status Register */
   #define ECC_VCR        3               /* Video Configuration Register */
   #define ECC_MFAR0      4               /* Memory Fault Address Register 0 */
   #define ECC_MFAR1      5               /* Memory Fault Address Register 1 */
   #define ECC_DR         6               /* Diagnostic Register */
   #define ECC_ECR0       7               /* Event Count Register 0 */
   #define ECC_ECR1       8               /* Event Count Register 1 */
   
 /* ECC fault control register */  /* ECC fault control register */
 #define ECC_FCR_EE     0x00000001      /* Enable ECC checking */  #define ECC_MER_EE     0x00000001      /* Enable ECC checking */
 #define ECC_FCR_EI     0x00000010      /* Enable Interrupts on correctable errors */  #define ECC_MER_EI     0x00000002      /* Enable Interrupts on
 #define ECC_FCR_VER    0x0f000000      /* Version */                                            correctable errors */
 #define ECC_FCR_IMPL   0xf0000000      /* Implementation */  #define ECC_MER_MRR0   0x00000004      /* SIMM 0 */
   #define ECC_MER_MRR1   0x00000008      /* SIMM 1 */
   #define ECC_MER_MRR2   0x00000010      /* SIMM 2 */
   #define ECC_MER_MRR3   0x00000020      /* SIMM 3 */
   #define ECC_MER_MRR4   0x00000040      /* SIMM 4 */
   #define ECC_MER_MRR5   0x00000080      /* SIMM 5 */
   #define ECC_MER_MRR6   0x00000100      /* SIMM 6 */
   #define ECC_MER_MRR7   0x00000200      /* SIMM 7 */
   #define ECC_MER_REU    0x00000100      /* Memory Refresh Enable (600MP) */
   #define ECC_MER_MRR    0x000003fc      /* MRR mask */
   #define ECC_MER_A      0x00000400      /* Memory controller addr map select */
   #define ECC_MER_DCI    0x00000800      /* Disables Coherent Invalidate ACK */
   #define ECC_MER_VER    0x0f000000      /* Version */
   #define ECC_MER_IMPL   0xf0000000      /* Implementation */
   #define ECC_MER_MASK_0 0x00000103      /* Version 0 (MCC) mask */
   #define ECC_MER_MASK_1 0x00000bff      /* Version 1 (EMC) mask */
   #define ECC_MER_MASK_2 0x00000bff      /* Version 2 (SMC) mask */
   
   /* ECC memory delay register */
   #define ECC_MDR_RRI    0x000003ff      /* Refresh Request Interval */
   #define ECC_MDR_MI     0x00001c00      /* MIH Delay */
   #define ECC_MDR_CI     0x0000e000      /* Coherent Invalidate Delay */
   #define ECC_MDR_MDL    0x001f0000      /* MBus Master arbitration delay */
   #define ECC_MDR_MDH    0x03e00000      /* MBus Master arbitration delay */
   #define ECC_MDR_GAD    0x7c000000      /* Graphics Arbitration Delay */
   #define ECC_MDR_RSC    0x80000000      /* Refresh load control */
   #define ECC_MDR_MASK   0x7fffffff
   
 /* ECC fault status register */  /* ECC fault status register */
 #define ECC_FSR_CE     0x00000001      /* Correctable error */  #define ECC_MFSR_CE    0x00000001      /* Correctable error */
 #define ECC_FSR_BS     0x00000002      /* C2 graphics bad slot access */  #define ECC_MFSR_BS    0x00000002      /* C2 graphics bad slot access */
 #define ECC_FSR_TO     0x00000004      /* Timeout on write */  #define ECC_MFSR_TO    0x00000004      /* Timeout on write */
 #define ECC_FSR_UE     0x00000008      /* Uncorrectable error */  #define ECC_MFSR_UE    0x00000008      /* Uncorrectable error */
 #define ECC_FSR_DW     0x000000f0      /* Index of double word in block */  #define ECC_MFSR_DW    0x000000f0      /* Index of double word in block */
 #define ECC_FSR_SYND   0x0000ff00      /* Syndrome for correctable error */  #define ECC_MFSR_SYND  0x0000ff00      /* Syndrome for correctable error */
 #define ECC_FSR_ME     0x00010000      /* Multiple errors */  #define ECC_MFSR_ME    0x00010000      /* Multiple errors */
 #define ECC_FSR_C2ERR  0x00020000      /* C2 graphics error */  #define ECC_MFSR_C2ERR 0x00020000      /* C2 graphics error */
   
 /* ECC fault address register 0 */  /* ECC fault address register 0 */
 #define ECC_FAR0_PADDR 0x0000000f      /* PA[32-35] */  #define ECC_MFAR0_PADDR 0x0000000f     /* PA[32-35] */
 #define ECC_FAR0_TYPE  0x000000f0      /* Transaction type */  #define ECC_MFAR0_TYPE  0x000000f0     /* Transaction type */
 #define ECC_FAR0_SIZE  0x00000700      /* Transaction size */  #define ECC_MFAR0_SIZE  0x00000700     /* Transaction size */
 #define ECC_FAR0_CACHE 0x00000800      /* Mapped cacheable */  #define ECC_MFAR0_CACHE 0x00000800     /* Mapped cacheable */
 #define ECC_FAR0_LOCK  0x00001000      /* Error occurred in attomic cycle */  #define ECC_MFAR0_LOCK  0x00001000     /* Error occurred in atomic cycle */
 #define ECC_FAR0_BMODE 0x00002000      /* Boot mode */  #define ECC_MFAR0_BMODE 0x00002000     /* Boot mode */
 #define ECC_FAR0_VADDR 0x003fc000      /* VA[12-19] (superset bits) */  #define ECC_MFAR0_VADDR 0x003fc000     /* VA[12-19] (superset bits) */
 #define ECC_FAR0_S     0x08000000      /* Supervisor mode */  #define ECC_MFAR0_S     0x08000000     /* Supervisor mode */
 #define ECC_FARO_MID   0xf0000000      /* Module ID */  #define ECC_MFARO_MID   0xf0000000     /* Module ID */
   
 /* ECC diagnostic register */  /* ECC diagnostic register */
 #define ECC_DIAG_CBX   0x00000001  #define ECC_DR_CBX     0x00000001
 #define ECC_DIAG_CB0   0x00000002  #define ECC_DR_CB0     0x00000002
 #define ECC_DIAG_CB1   0x00000004  #define ECC_DR_CB1     0x00000004
 #define ECC_DIAG_CB2   0x00000008  #define ECC_DR_CB2     0x00000008
 #define ECC_DIAG_CB4   0x00000010  #define ECC_DR_CB4     0x00000010
 #define ECC_DIAG_CB8   0x00000020  #define ECC_DR_CB8     0x00000020
 #define ECC_DIAG_CB16  0x00000040  #define ECC_DR_CB16    0x00000040
 #define ECC_DIAG_CB32  0x00000080  #define ECC_DR_CB32    0x00000080
 #define ECC_DIAG_DMODE 0x00000c00  #define ECC_DR_DMODE   0x00000c00
   
 #define ECC_NREGS      8  #define ECC_NREGS      9
 #define ECC_SIZE       (ECC_NREGS * sizeof(uint32_t))  #define ECC_SIZE       (ECC_NREGS * sizeof(uint32_t))
 #define ECC_ADDR_MASK  (ECC_SIZE - 1)  
   #define ECC_DIAG_SIZE  4
   #define ECC_DIAG_MASK  (ECC_DIAG_SIZE - 1)
   
 typedef struct ECCState {  typedef struct ECCState {
       qemu_irq irq;
     uint32_t regs[ECC_NREGS];      uint32_t regs[ECC_NREGS];
       uint8_t diag[ECC_DIAG_SIZE];
       uint32_t version;
 } ECCState;  } ECCState;
   
 static void ecc_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)  static void ecc_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 {  {
     ECCState *s = opaque;      ECCState *s = opaque;
   
     switch (addr & ECC_ADDR_MASK) {      switch (addr >> 2) {
     case ECC_FCR_REG:      case ECC_MER:
         s->regs[0] = (s->regs[0] & (ECC_FCR_VER | ECC_FCR_IMPL)) |          if (s->version == ECC_MCC)
                      (val & ~(ECC_FCR_VER | ECC_FCR_IMPL));              s->regs[ECC_MER] = (val & ECC_MER_MASK_0);
         DPRINTF("Write fault control %08x\n", val);          else if (s->version == ECC_EMC)
         break;              s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_1);
     case 4:          else if (s->version == ECC_SMC)
         s->regs[1] =  val;              s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_2);
         DPRINTF("Write reg[1] %08x\n", val);          DPRINTF("Write memory enable %08x\n", val);
         break;          break;
     case ECC_FSR_REG:      case ECC_MDR:
         s->regs[2] =  val;          s->regs[ECC_MDR] =  val & ECC_MDR_MASK;
         DPRINTF("Write fault status %08x\n", val);          DPRINTF("Write memory delay %08x\n", val);
         break;          break;
     case 12:      case ECC_MFSR:
         s->regs[3] =  val;          s->regs[ECC_MFSR] =  val;
         DPRINTF("Write reg[3] %08x\n", val);          qemu_irq_lower(s->irq);
         break;          DPRINTF("Write memory fault status %08x\n", val);
     case ECC_FAR0_REG:          break;
         s->regs[4] =  val;      case ECC_VCR:
         DPRINTF("Write fault address 0 %08x\n", val);          s->regs[ECC_VCR] =  val;
         break;          DPRINTF("Write slot configuration %08x\n", val);
     case ECC_FAR1_REG:          break;
         s->regs[5] =  val;      case ECC_DR:
         DPRINTF("Write fault address 1 %08x\n", val);          s->regs[ECC_DR] =  val;
         break;          DPRINTF("Write diagnostic %08x\n", val);
     case ECC_DIAG_REG:          break;
         s->regs[6] =  val;      case ECC_ECR0:
         DPRINTF("Write diag %08x\n", val);          s->regs[ECC_ECR0] =  val;
         break;          DPRINTF("Write event count 1 %08x\n", val);
     case 28:          break;
         s->regs[7] =  val;      case ECC_ECR1:
         DPRINTF("Write reg[7] %08x\n", val);          s->regs[ECC_ECR0] =  val;
           DPRINTF("Write event count 2 %08x\n", val);
         break;          break;
     }      }
 }  }
Line 139  static uint32_t ecc_mem_readl(void *opaq Line 179  static uint32_t ecc_mem_readl(void *opaq
     ECCState *s = opaque;      ECCState *s = opaque;
     uint32_t ret = 0;      uint32_t ret = 0;
   
     switch (addr & ECC_ADDR_MASK) {      switch (addr >> 2) {
     case ECC_FCR_REG:      case ECC_MER:
         ret = s->regs[0];          ret = s->regs[ECC_MER];
         DPRINTF("Read enable %08x\n", ret);          DPRINTF("Read memory enable %08x\n", ret);
         break;          break;
     case 4:      case ECC_MDR:
         ret = s->regs[1];          ret = s->regs[ECC_MDR];
         DPRINTF("Read register[1] %08x\n", ret);          DPRINTF("Read memory delay %08x\n", ret);
         break;          break;
     case ECC_FSR_REG:      case ECC_MFSR:
         ret = s->regs[2];          ret = s->regs[ECC_MFSR];
         DPRINTF("Read fault status %08x\n", ret);          DPRINTF("Read memory fault status %08x\n", ret);
         break;          break;
     case 12:      case ECC_VCR:
         ret = s->regs[3];          ret = s->regs[ECC_VCR];
         DPRINTF("Read reg[3] %08x\n", ret);          DPRINTF("Read slot configuration %08x\n", ret);
         break;          break;
     case ECC_FAR0_REG:      case ECC_MFAR0:
         ret = s->regs[4];          ret = s->regs[ECC_MFAR0];
         DPRINTF("Read fault address 0 %08x\n", ret);          DPRINTF("Read memory fault address 0 %08x\n", ret);
         break;          break;
     case ECC_FAR1_REG:      case ECC_MFAR1:
         ret = s->regs[5];          ret = s->regs[ECC_MFAR1];
         DPRINTF("Read fault address 1 %08x\n", ret);          DPRINTF("Read memory fault address 1 %08x\n", ret);
         break;          break;
     case ECC_DIAG_REG:      case ECC_DR:
         ret = s->regs[6];          ret = s->regs[ECC_DR];
         DPRINTF("Read diag %08x\n", ret);          DPRINTF("Read diagnostic %08x\n", ret);
         break;          break;
     case 28:      case ECC_ECR0:
         ret = s->regs[7];          ret = s->regs[ECC_ECR0];
         DPRINTF("Read reg[7] %08x\n", ret);          DPRINTF("Read event count 1 %08x\n", ret);
           break;
       case ECC_ECR1:
           ret = s->regs[ECC_ECR0];
           DPRINTF("Read event count 2 %08x\n", ret);
         break;          break;
     }      }
     return ret;      return ret;
Line 188  static CPUWriteMemoryFunc *ecc_mem_write Line 232  static CPUWriteMemoryFunc *ecc_mem_write
     ecc_mem_writel,      ecc_mem_writel,
 };  };
   
   static void ecc_diag_mem_writeb(void *opaque, target_phys_addr_t addr,
                                   uint32_t val)
   {
       ECCState *s = opaque;
   
       DPRINTF("Write diagnostic[%d] = %02x\n", (int)addr, val);
       s->diag[addr & ECC_DIAG_MASK] = val;
   }
   
   static uint32_t ecc_diag_mem_readb(void *opaque, target_phys_addr_t addr)
   {
       ECCState *s = opaque;
       uint32_t ret = s->diag[(int)addr];
   
       DPRINTF("Read diagnostic[%d] = %02x\n", (int)addr, ret);
       return ret;
   }
   
   static CPUReadMemoryFunc *ecc_diag_mem_read[3] = {
       ecc_diag_mem_readb,
       NULL,
       NULL,
   };
   
   static CPUWriteMemoryFunc *ecc_diag_mem_write[3] = {
       ecc_diag_mem_writeb,
       NULL,
       NULL,
   };
   
 static int ecc_load(QEMUFile *f, void *opaque, int version_id)  static int ecc_load(QEMUFile *f, void *opaque, int version_id)
 {  {
     ECCState *s = opaque;      ECCState *s = opaque;
     int i;      int i;
   
     if (version_id != 1)      if (version_id != 3)
         return -EINVAL;          return -EINVAL;
   
     for (i = 0; i < ECC_NREGS; i++)      for (i = 0; i < ECC_NREGS; i++)
         qemu_get_be32s(f, &s->regs[i]);          qemu_get_be32s(f, &s->regs[i]);
   
       for (i = 0; i < ECC_DIAG_SIZE; i++)
           qemu_get_8s(f, &s->diag[i]);
   
       qemu_get_be32s(f, &s->version);
   
     return 0;      return 0;
 }  }
   
Line 209  static void ecc_save(QEMUFile *f, void * Line 288  static void ecc_save(QEMUFile *f, void *
   
     for (i = 0; i < ECC_NREGS; i++)      for (i = 0; i < ECC_NREGS; i++)
         qemu_put_be32s(f, &s->regs[i]);          qemu_put_be32s(f, &s->regs[i]);
   
       for (i = 0; i < ECC_DIAG_SIZE; i++)
           qemu_put_8s(f, &s->diag[i]);
   
       qemu_put_be32s(f, &s->version);
 }  }
   
 static void ecc_reset(void *opaque)  static void ecc_reset(void *opaque)
 {  {
     ECCState *s = opaque;      ECCState *s = opaque;
     int i;  
   
     s->regs[ECC_FCR_REG] &= (ECC_FCR_VER | ECC_FCR_IMPL);  
   
     for (i = 1; i < ECC_NREGS; i++)      if (s->version == ECC_MCC)
         s->regs[i] = 0;          s->regs[ECC_MER] &= ECC_MER_REU;
       else
           s->regs[ECC_MER] &= (ECC_MER_VER | ECC_MER_IMPL | ECC_MER_MRR |
                                ECC_MER_DCI);
       s->regs[ECC_MDR] = 0x20;
       s->regs[ECC_MFSR] = 0;
       s->regs[ECC_VCR] = 0;
       s->regs[ECC_MFAR0] = 0x07c00000;
       s->regs[ECC_MFAR1] = 0;
       s->regs[ECC_DR] = 0;
       s->regs[ECC_ECR0] = 0;
       s->regs[ECC_ECR1] = 0;
 }  }
   
 void * ecc_init(target_phys_addr_t base, uint32_t version)  void * ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
 {  {
     int ecc_io_memory;      int ecc_io_memory;
     ECCState *s;      ECCState *s;
   
     s = qemu_mallocz(sizeof(ECCState));      s = qemu_mallocz(sizeof(ECCState));
     if (!s)  
         return NULL;  
   
       s->version = version;
     s->regs[0] = version;      s->regs[0] = version;
       s->irq = irq;
   
     ecc_io_memory = cpu_register_io_memory(0, ecc_mem_read, ecc_mem_write, s);      ecc_io_memory = cpu_register_io_memory(0, ecc_mem_read, ecc_mem_write, s);
     cpu_register_physical_memory(base, ECC_SIZE, ecc_io_memory);      cpu_register_physical_memory(base, ECC_SIZE, ecc_io_memory);
     register_savevm("ECC", base, 1, ecc_save, ecc_load, s);      if (version == ECC_MCC) { // SS-600MP only
           ecc_io_memory = cpu_register_io_memory(0, ecc_diag_mem_read,
                                                  ecc_diag_mem_write, s);
           cpu_register_physical_memory(base + 0x1000, ECC_DIAG_SIZE,
                                        ecc_io_memory);
       }
       register_savevm("ECC", base, 3, ecc_save, ecc_load, s);
     qemu_register_reset(ecc_reset, s);      qemu_register_reset(ecc_reset, s);
     ecc_reset(s);      ecc_reset(s);
     return s;      return s;

Removed from v.1.1.1.1  
changed lines
  Added in v.1.1.1.2


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