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1.1 root 1: /*
2: * QEMU Sparc Sun4m ECC memory controller emulation
3: *
4: * Copyright (c) 2007 Robert Reif
5: *
6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
1.1.1.3 ! root 24:
1.1 root 25: #include "sun4m.h"
1.1.1.3 ! root 26: #include "sysbus.h"
1.1 root 27:
28: //#define DEBUG_ECC
29:
30: #ifdef DEBUG_ECC
1.1.1.3 ! root 31: #define DPRINTF(fmt, ...) \
! 32: do { printf("ECC: " fmt , ## __VA_ARGS__); } while (0)
1.1 root 33: #else
1.1.1.3 ! root 34: #define DPRINTF(fmt, ...)
1.1 root 35: #endif
36:
37: /* There are 3 versions of this chip used in SMP sun4m systems:
38: * MCC (version 0, implementation 0) SS-600MP
39: * EMC (version 0, implementation 1) SS-10
40: * SMC (version 0, implementation 2) SS-10SX and SS-20
41: */
42:
1.1.1.2 root 43: #define ECC_MCC 0x00000000
44: #define ECC_EMC 0x10000000
45: #define ECC_SMC 0x20000000
46:
47: /* Register indexes */
48: #define ECC_MER 0 /* Memory Enable Register */
49: #define ECC_MDR 1 /* Memory Delay Register */
50: #define ECC_MFSR 2 /* Memory Fault Status Register */
51: #define ECC_VCR 3 /* Video Configuration Register */
52: #define ECC_MFAR0 4 /* Memory Fault Address Register 0 */
53: #define ECC_MFAR1 5 /* Memory Fault Address Register 1 */
54: #define ECC_DR 6 /* Diagnostic Register */
55: #define ECC_ECR0 7 /* Event Count Register 0 */
56: #define ECC_ECR1 8 /* Event Count Register 1 */
1.1 root 57:
58: /* ECC fault control register */
1.1.1.2 root 59: #define ECC_MER_EE 0x00000001 /* Enable ECC checking */
60: #define ECC_MER_EI 0x00000002 /* Enable Interrupts on
61: correctable errors */
62: #define ECC_MER_MRR0 0x00000004 /* SIMM 0 */
63: #define ECC_MER_MRR1 0x00000008 /* SIMM 1 */
64: #define ECC_MER_MRR2 0x00000010 /* SIMM 2 */
65: #define ECC_MER_MRR3 0x00000020 /* SIMM 3 */
66: #define ECC_MER_MRR4 0x00000040 /* SIMM 4 */
67: #define ECC_MER_MRR5 0x00000080 /* SIMM 5 */
68: #define ECC_MER_MRR6 0x00000100 /* SIMM 6 */
69: #define ECC_MER_MRR7 0x00000200 /* SIMM 7 */
70: #define ECC_MER_REU 0x00000100 /* Memory Refresh Enable (600MP) */
71: #define ECC_MER_MRR 0x000003fc /* MRR mask */
72: #define ECC_MER_A 0x00000400 /* Memory controller addr map select */
73: #define ECC_MER_DCI 0x00000800 /* Disables Coherent Invalidate ACK */
74: #define ECC_MER_VER 0x0f000000 /* Version */
75: #define ECC_MER_IMPL 0xf0000000 /* Implementation */
76: #define ECC_MER_MASK_0 0x00000103 /* Version 0 (MCC) mask */
77: #define ECC_MER_MASK_1 0x00000bff /* Version 1 (EMC) mask */
78: #define ECC_MER_MASK_2 0x00000bff /* Version 2 (SMC) mask */
79:
80: /* ECC memory delay register */
81: #define ECC_MDR_RRI 0x000003ff /* Refresh Request Interval */
82: #define ECC_MDR_MI 0x00001c00 /* MIH Delay */
83: #define ECC_MDR_CI 0x0000e000 /* Coherent Invalidate Delay */
84: #define ECC_MDR_MDL 0x001f0000 /* MBus Master arbitration delay */
85: #define ECC_MDR_MDH 0x03e00000 /* MBus Master arbitration delay */
86: #define ECC_MDR_GAD 0x7c000000 /* Graphics Arbitration Delay */
87: #define ECC_MDR_RSC 0x80000000 /* Refresh load control */
88: #define ECC_MDR_MASK 0x7fffffff
1.1 root 89:
90: /* ECC fault status register */
1.1.1.2 root 91: #define ECC_MFSR_CE 0x00000001 /* Correctable error */
92: #define ECC_MFSR_BS 0x00000002 /* C2 graphics bad slot access */
93: #define ECC_MFSR_TO 0x00000004 /* Timeout on write */
94: #define ECC_MFSR_UE 0x00000008 /* Uncorrectable error */
95: #define ECC_MFSR_DW 0x000000f0 /* Index of double word in block */
96: #define ECC_MFSR_SYND 0x0000ff00 /* Syndrome for correctable error */
97: #define ECC_MFSR_ME 0x00010000 /* Multiple errors */
98: #define ECC_MFSR_C2ERR 0x00020000 /* C2 graphics error */
1.1 root 99:
100: /* ECC fault address register 0 */
1.1.1.2 root 101: #define ECC_MFAR0_PADDR 0x0000000f /* PA[32-35] */
102: #define ECC_MFAR0_TYPE 0x000000f0 /* Transaction type */
103: #define ECC_MFAR0_SIZE 0x00000700 /* Transaction size */
104: #define ECC_MFAR0_CACHE 0x00000800 /* Mapped cacheable */
105: #define ECC_MFAR0_LOCK 0x00001000 /* Error occurred in atomic cycle */
106: #define ECC_MFAR0_BMODE 0x00002000 /* Boot mode */
107: #define ECC_MFAR0_VADDR 0x003fc000 /* VA[12-19] (superset bits) */
108: #define ECC_MFAR0_S 0x08000000 /* Supervisor mode */
109: #define ECC_MFARO_MID 0xf0000000 /* Module ID */
1.1 root 110:
111: /* ECC diagnostic register */
1.1.1.2 root 112: #define ECC_DR_CBX 0x00000001
113: #define ECC_DR_CB0 0x00000002
114: #define ECC_DR_CB1 0x00000004
115: #define ECC_DR_CB2 0x00000008
116: #define ECC_DR_CB4 0x00000010
117: #define ECC_DR_CB8 0x00000020
118: #define ECC_DR_CB16 0x00000040
119: #define ECC_DR_CB32 0x00000080
120: #define ECC_DR_DMODE 0x00000c00
1.1 root 121:
1.1.1.2 root 122: #define ECC_NREGS 9
1.1 root 123: #define ECC_SIZE (ECC_NREGS * sizeof(uint32_t))
1.1.1.2 root 124:
125: #define ECC_DIAG_SIZE 4
126: #define ECC_DIAG_MASK (ECC_DIAG_SIZE - 1)
1.1 root 127:
128: typedef struct ECCState {
1.1.1.3 ! root 129: SysBusDevice busdev;
1.1.1.2 root 130: qemu_irq irq;
1.1 root 131: uint32_t regs[ECC_NREGS];
1.1.1.2 root 132: uint8_t diag[ECC_DIAG_SIZE];
133: uint32_t version;
1.1 root 134: } ECCState;
135:
136: static void ecc_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
137: {
138: ECCState *s = opaque;
139:
1.1.1.2 root 140: switch (addr >> 2) {
141: case ECC_MER:
142: if (s->version == ECC_MCC)
143: s->regs[ECC_MER] = (val & ECC_MER_MASK_0);
144: else if (s->version == ECC_EMC)
145: s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_1);
146: else if (s->version == ECC_SMC)
147: s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_2);
148: DPRINTF("Write memory enable %08x\n", val);
149: break;
150: case ECC_MDR:
151: s->regs[ECC_MDR] = val & ECC_MDR_MASK;
152: DPRINTF("Write memory delay %08x\n", val);
153: break;
154: case ECC_MFSR:
155: s->regs[ECC_MFSR] = val;
156: qemu_irq_lower(s->irq);
157: DPRINTF("Write memory fault status %08x\n", val);
158: break;
159: case ECC_VCR:
160: s->regs[ECC_VCR] = val;
161: DPRINTF("Write slot configuration %08x\n", val);
162: break;
163: case ECC_DR:
164: s->regs[ECC_DR] = val;
165: DPRINTF("Write diagnostic %08x\n", val);
166: break;
167: case ECC_ECR0:
168: s->regs[ECC_ECR0] = val;
169: DPRINTF("Write event count 1 %08x\n", val);
170: break;
171: case ECC_ECR1:
172: s->regs[ECC_ECR0] = val;
173: DPRINTF("Write event count 2 %08x\n", val);
1.1 root 174: break;
175: }
176: }
177:
178: static uint32_t ecc_mem_readl(void *opaque, target_phys_addr_t addr)
179: {
180: ECCState *s = opaque;
181: uint32_t ret = 0;
182:
1.1.1.2 root 183: switch (addr >> 2) {
184: case ECC_MER:
185: ret = s->regs[ECC_MER];
186: DPRINTF("Read memory enable %08x\n", ret);
187: break;
188: case ECC_MDR:
189: ret = s->regs[ECC_MDR];
190: DPRINTF("Read memory delay %08x\n", ret);
191: break;
192: case ECC_MFSR:
193: ret = s->regs[ECC_MFSR];
194: DPRINTF("Read memory fault status %08x\n", ret);
195: break;
196: case ECC_VCR:
197: ret = s->regs[ECC_VCR];
198: DPRINTF("Read slot configuration %08x\n", ret);
199: break;
200: case ECC_MFAR0:
201: ret = s->regs[ECC_MFAR0];
202: DPRINTF("Read memory fault address 0 %08x\n", ret);
203: break;
204: case ECC_MFAR1:
205: ret = s->regs[ECC_MFAR1];
206: DPRINTF("Read memory fault address 1 %08x\n", ret);
207: break;
208: case ECC_DR:
209: ret = s->regs[ECC_DR];
210: DPRINTF("Read diagnostic %08x\n", ret);
211: break;
212: case ECC_ECR0:
213: ret = s->regs[ECC_ECR0];
214: DPRINTF("Read event count 1 %08x\n", ret);
215: break;
216: case ECC_ECR1:
217: ret = s->regs[ECC_ECR0];
218: DPRINTF("Read event count 2 %08x\n", ret);
1.1 root 219: break;
220: }
221: return ret;
222: }
223:
224: static CPUReadMemoryFunc *ecc_mem_read[3] = {
225: NULL,
226: NULL,
227: ecc_mem_readl,
228: };
229:
230: static CPUWriteMemoryFunc *ecc_mem_write[3] = {
231: NULL,
232: NULL,
233: ecc_mem_writel,
234: };
235:
1.1.1.2 root 236: static void ecc_diag_mem_writeb(void *opaque, target_phys_addr_t addr,
237: uint32_t val)
238: {
239: ECCState *s = opaque;
240:
241: DPRINTF("Write diagnostic[%d] = %02x\n", (int)addr, val);
242: s->diag[addr & ECC_DIAG_MASK] = val;
243: }
244:
245: static uint32_t ecc_diag_mem_readb(void *opaque, target_phys_addr_t addr)
246: {
247: ECCState *s = opaque;
248: uint32_t ret = s->diag[(int)addr];
249:
250: DPRINTF("Read diagnostic[%d] = %02x\n", (int)addr, ret);
251: return ret;
252: }
253:
254: static CPUReadMemoryFunc *ecc_diag_mem_read[3] = {
255: ecc_diag_mem_readb,
256: NULL,
257: NULL,
258: };
259:
260: static CPUWriteMemoryFunc *ecc_diag_mem_write[3] = {
261: ecc_diag_mem_writeb,
262: NULL,
263: NULL,
264: };
265:
1.1 root 266: static int ecc_load(QEMUFile *f, void *opaque, int version_id)
267: {
268: ECCState *s = opaque;
269: int i;
270:
1.1.1.2 root 271: if (version_id != 3)
1.1 root 272: return -EINVAL;
273:
274: for (i = 0; i < ECC_NREGS; i++)
275: qemu_get_be32s(f, &s->regs[i]);
276:
1.1.1.2 root 277: for (i = 0; i < ECC_DIAG_SIZE; i++)
278: qemu_get_8s(f, &s->diag[i]);
279:
280: qemu_get_be32s(f, &s->version);
281:
1.1 root 282: return 0;
283: }
284:
285: static void ecc_save(QEMUFile *f, void *opaque)
286: {
287: ECCState *s = opaque;
288: int i;
289:
290: for (i = 0; i < ECC_NREGS; i++)
291: qemu_put_be32s(f, &s->regs[i]);
1.1.1.2 root 292:
293: for (i = 0; i < ECC_DIAG_SIZE; i++)
294: qemu_put_8s(f, &s->diag[i]);
295:
296: qemu_put_be32s(f, &s->version);
1.1 root 297: }
298:
299: static void ecc_reset(void *opaque)
300: {
301: ECCState *s = opaque;
302:
1.1.1.2 root 303: if (s->version == ECC_MCC)
304: s->regs[ECC_MER] &= ECC_MER_REU;
305: else
306: s->regs[ECC_MER] &= (ECC_MER_VER | ECC_MER_IMPL | ECC_MER_MRR |
307: ECC_MER_DCI);
308: s->regs[ECC_MDR] = 0x20;
309: s->regs[ECC_MFSR] = 0;
310: s->regs[ECC_VCR] = 0;
311: s->regs[ECC_MFAR0] = 0x07c00000;
312: s->regs[ECC_MFAR1] = 0;
313: s->regs[ECC_DR] = 0;
314: s->regs[ECC_ECR0] = 0;
315: s->regs[ECC_ECR1] = 0;
1.1 root 316: }
317:
1.1.1.3 ! root 318: static void ecc_init1(SysBusDevice *dev)
1.1 root 319: {
320: int ecc_io_memory;
1.1.1.3 ! root 321: ECCState *s = FROM_SYSBUS(ECCState, dev);
1.1 root 322:
1.1.1.3 ! root 323: sysbus_init_irq(dev, &s->irq);
! 324: s->regs[0] = s->version;
! 325: ecc_io_memory = cpu_register_io_memory(ecc_mem_read, ecc_mem_write, s);
! 326: sysbus_init_mmio(dev, ECC_SIZE, ecc_io_memory);
1.1 root 327:
1.1.1.3 ! root 328: if (s->version == ECC_MCC) { // SS-600MP only
! 329: ecc_io_memory = cpu_register_io_memory(ecc_diag_mem_read,
1.1.1.2 root 330: ecc_diag_mem_write, s);
1.1.1.3 ! root 331: sysbus_init_mmio(dev, ECC_DIAG_SIZE, ecc_io_memory);
1.1.1.2 root 332: }
1.1.1.3 ! root 333: register_savevm("ECC", -1, 3, ecc_save, ecc_load, s);
1.1 root 334: qemu_register_reset(ecc_reset, s);
335: ecc_reset(s);
336: }
1.1.1.3 ! root 337:
! 338: void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
! 339: {
! 340: DeviceState *dev;
! 341: SysBusDevice *s;
! 342:
! 343: dev = qdev_create(NULL, "eccmemctl");
! 344: qdev_prop_set_uint32(dev, "version", version);
! 345: qdev_init(dev);
! 346: s = sysbus_from_qdev(dev);
! 347: sysbus_connect_irq(s, 0, irq);
! 348: sysbus_mmio_map(s, 0, base);
! 349: if (version == ECC_MCC) { // SS-600MP only
! 350: sysbus_mmio_map(s, 1, base + 0x1000);
! 351: }
! 352: }
! 353:
! 354: static SysBusDeviceInfo ecc_info = {
! 355: .init = ecc_init1,
! 356: .qdev.name = "eccmemctl",
! 357: .qdev.size = sizeof(ECCState),
! 358: .qdev.props = (Property[]) {
! 359: {
! 360: .name = "version",
! 361: .info = &qdev_prop_hex32,
! 362: .offset = offsetof(ECCState, version),
! 363: .defval = (uint32_t[]) { -1 },
! 364: },
! 365: {/* end of list */}
! 366: }
! 367: };
! 368:
! 369:
! 370: static void ecc_register_devices(void)
! 371: {
! 372: sysbus_register_withprop(&ecc_info);
! 373: }
! 374:
! 375: device_init(ecc_register_devices)
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