version 1.1.1.10, 2018/04/24 18:30:12
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version 1.1.1.11, 2018/04/24 18:39:39
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Line 80 struct ESPState {
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Line 80 struct ESPState {
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ESPDMAMemoryReadWriteFunc dma_memory_read; |
ESPDMAMemoryReadWriteFunc dma_memory_read; |
ESPDMAMemoryReadWriteFunc dma_memory_write; |
ESPDMAMemoryReadWriteFunc dma_memory_write; |
void *dma_opaque; |
void *dma_opaque; |
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int dma_enabled; |
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void (*dma_cb)(ESPState *s); |
}; |
}; |
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#define ESP_TCLO 0x0 |
#define ESP_TCLO 0x0 |
Line 167 static void esp_lower_irq(ESPState *s)
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Line 169 static void esp_lower_irq(ESPState *s)
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} |
} |
} |
} |
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static void esp_dma_enable(void *opaque, int irq, int level) |
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{ |
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DeviceState *d = opaque; |
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ESPState *s = container_of(d, ESPState, busdev.qdev); |
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if (level) { |
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s->dma_enabled = 1; |
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DPRINTF("Raise enable\n"); |
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if (s->dma_cb) { |
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s->dma_cb(s); |
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s->dma_cb = NULL; |
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} |
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} else { |
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DPRINTF("Lower enable\n"); |
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s->dma_enabled = 0; |
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} |
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} |
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static uint32_t get_cmd(ESPState *s, uint8_t *buf) |
static uint32_t get_cmd(ESPState *s, uint8_t *buf) |
{ |
{ |
uint32_t dmalen; |
uint32_t dmalen; |
Line 243 static void handle_satn(ESPState *s)
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Line 263 static void handle_satn(ESPState *s)
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uint8_t buf[32]; |
uint8_t buf[32]; |
int len; |
int len; |
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if (!s->dma_enabled) { |
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s->dma_cb = handle_satn; |
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return; |
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} |
len = get_cmd(s, buf); |
len = get_cmd(s, buf); |
if (len) |
if (len) |
do_cmd(s, buf); |
do_cmd(s, buf); |
Line 253 static void handle_s_without_atn(ESPStat
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Line 277 static void handle_s_without_atn(ESPStat
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uint8_t buf[32]; |
uint8_t buf[32]; |
int len; |
int len; |
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if (!s->dma_enabled) { |
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s->dma_cb = handle_s_without_atn; |
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return; |
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} |
len = get_cmd(s, buf); |
len = get_cmd(s, buf); |
if (len) { |
if (len) { |
do_busid_cmd(s, buf, 0); |
do_busid_cmd(s, buf, 0); |
Line 261 static void handle_s_without_atn(ESPStat
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Line 289 static void handle_s_without_atn(ESPStat
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static void handle_satn_stop(ESPState *s) |
static void handle_satn_stop(ESPState *s) |
{ |
{ |
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if (!s->dma_enabled) { |
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s->dma_cb = handle_satn_stop; |
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return; |
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} |
s->cmdlen = get_cmd(s, s->cmdbuf); |
s->cmdlen = get_cmd(s, s->cmdbuf); |
if (s->cmdlen) { |
if (s->cmdlen) { |
DPRINTF("Set ATN & Stop: cmdlen %d\n", s->cmdlen); |
DPRINTF("Set ATN & Stop: cmdlen %d\n", s->cmdlen); |
Line 431 static void esp_hard_reset(DeviceState *
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Line 463 static void esp_hard_reset(DeviceState *
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s->ti_wptr = 0; |
s->ti_wptr = 0; |
s->dma = 0; |
s->dma = 0; |
s->do_cmd = 0; |
s->do_cmd = 0; |
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s->dma_cb = NULL; |
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s->rregs[ESP_CFG1] = 7; |
s->rregs[ESP_CFG1] = 7; |
} |
} |
Line 450 static void parent_esp_reset(void *opaqu
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Line 483 static void parent_esp_reset(void *opaqu
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} |
} |
} |
} |
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static void esp_gpio_demux(void *opaque, int irq, int level) |
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{ |
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switch (irq) { |
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case 0: |
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parent_esp_reset(opaque, irq, level); |
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break; |
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case 1: |
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esp_dma_enable(opaque, irq, level); |
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break; |
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} |
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} |
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static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr) |
static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr) |
{ |
{ |
ESPState *s = opaque; |
ESPState *s = opaque; |
Line 646 static const VMStateDescription vmstate_
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Line 691 static const VMStateDescription vmstate_
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void esp_init(target_phys_addr_t espaddr, int it_shift, |
void esp_init(target_phys_addr_t espaddr, int it_shift, |
ESPDMAMemoryReadWriteFunc dma_memory_read, |
ESPDMAMemoryReadWriteFunc dma_memory_read, |
ESPDMAMemoryReadWriteFunc dma_memory_write, |
ESPDMAMemoryReadWriteFunc dma_memory_write, |
void *dma_opaque, qemu_irq irq, qemu_irq *reset) |
void *dma_opaque, qemu_irq irq, qemu_irq *reset, |
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qemu_irq *dma_enable) |
{ |
{ |
DeviceState *dev; |
DeviceState *dev; |
SysBusDevice *s; |
SysBusDevice *s; |
Line 658 void esp_init(target_phys_addr_t espaddr
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Line 704 void esp_init(target_phys_addr_t espaddr
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esp->dma_memory_write = dma_memory_write; |
esp->dma_memory_write = dma_memory_write; |
esp->dma_opaque = dma_opaque; |
esp->dma_opaque = dma_opaque; |
esp->it_shift = it_shift; |
esp->it_shift = it_shift; |
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/* XXX for now until rc4030 has been changed to use DMA enable signal */ |
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esp->dma_enabled = 1; |
qdev_init_nofail(dev); |
qdev_init_nofail(dev); |
s = sysbus_from_qdev(dev); |
s = sysbus_from_qdev(dev); |
sysbus_connect_irq(s, 0, irq); |
sysbus_connect_irq(s, 0, irq); |
sysbus_mmio_map(s, 0, espaddr); |
sysbus_mmio_map(s, 0, espaddr); |
*reset = qdev_get_gpio_in(dev, 0); |
*reset = qdev_get_gpio_in(dev, 0); |
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*dma_enable = qdev_get_gpio_in(dev, 1); |
} |
} |
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static int esp_init1(SysBusDevice *dev) |
static int esp_init1(SysBusDevice *dev) |
Line 673 static int esp_init1(SysBusDevice *dev)
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Line 722 static int esp_init1(SysBusDevice *dev)
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sysbus_init_irq(dev, &s->irq); |
sysbus_init_irq(dev, &s->irq); |
assert(s->it_shift != -1); |
assert(s->it_shift != -1); |
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esp_io_memory = cpu_register_io_memory(esp_mem_read, esp_mem_write, s); |
esp_io_memory = cpu_register_io_memory(esp_mem_read, esp_mem_write, s, |
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DEVICE_NATIVE_ENDIAN); |
sysbus_init_mmio(dev, ESP_REGS << s->it_shift, esp_io_memory); |
sysbus_init_mmio(dev, ESP_REGS << s->it_shift, esp_io_memory); |
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qdev_init_gpio_in(&dev->qdev, parent_esp_reset, 1); |
qdev_init_gpio_in(&dev->qdev, esp_gpio_demux, 2); |
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scsi_bus_new(&s->bus, &dev->qdev, 0, ESP_MAX_DEVS, esp_command_complete); |
scsi_bus_new(&s->bus, &dev->qdev, 0, ESP_MAX_DEVS, esp_command_complete); |
return scsi_bus_legacy_handle_cmdline(&s->bus); |
return scsi_bus_legacy_handle_cmdline(&s->bus); |