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1.1 root 1: /*
1.1.1.2 root 2: * QEMU ETRAX Timers
1.1 root 3: *
4: * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
5: *
6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
1.1.1.3 root 24: #include "sysbus.h"
1.1.1.2 root 25: #include "sysemu.h"
1.1 root 26: #include "qemu-timer.h"
27:
1.1.1.2 root 28: #define D(x)
1.1 root 29:
1.1.1.2 root 30: #define RW_TMR0_DIV 0x00
31: #define R_TMR0_DATA 0x04
32: #define RW_TMR0_CTRL 0x08
33: #define RW_TMR1_DIV 0x10
34: #define R_TMR1_DATA 0x14
35: #define RW_TMR1_CTRL 0x18
36: #define R_TIME 0x38
37: #define RW_WD_CTRL 0x40
38: #define R_WD_STAT 0x44
39: #define RW_INTR_MASK 0x48
40: #define RW_ACK_INTR 0x4c
41: #define R_INTR 0x50
42: #define R_MASKED_INTR 0x54
1.1 root 43:
1.1.1.3 root 44: struct etrax_timer {
45: SysBusDevice busdev;
46: qemu_irq irq;
47: qemu_irq nmi;
48:
49: QEMUBH *bh_t0;
50: QEMUBH *bh_t1;
51: QEMUBH *bh_wd;
52: ptimer_state *ptimer_t0;
53: ptimer_state *ptimer_t1;
54: ptimer_state *ptimer_wd;
55:
56: int wd_hits;
57:
58: /* Control registers. */
59: uint32_t rw_tmr0_div;
60: uint32_t r_tmr0_data;
61: uint32_t rw_tmr0_ctrl;
62:
63: uint32_t rw_tmr1_div;
64: uint32_t r_tmr1_data;
65: uint32_t rw_tmr1_ctrl;
66:
67: uint32_t rw_wd_ctrl;
68:
69: uint32_t rw_intr_mask;
70: uint32_t rw_ack_intr;
71: uint32_t r_intr;
72: uint32_t r_masked_intr;
1.1.1.2 root 73: };
1.1 root 74:
75: static uint32_t timer_readl (void *opaque, target_phys_addr_t addr)
76: {
1.1.1.3 root 77: struct etrax_timer *t = opaque;
78: uint32_t r = 0;
1.1 root 79:
1.1.1.3 root 80: switch (addr) {
81: case R_TMR0_DATA:
82: r = ptimer_get_count(t->ptimer_t0);
83: break;
84: case R_TMR1_DATA:
85: r = ptimer_get_count(t->ptimer_t1);
86: break;
87: case R_TIME:
88: r = qemu_get_clock(vm_clock) / 10;
89: break;
90: case RW_INTR_MASK:
91: r = t->rw_intr_mask;
92: break;
93: case R_MASKED_INTR:
94: r = t->r_intr & t->rw_intr_mask;
95: break;
96: default:
97: D(printf ("%s %x\n", __func__, addr));
98: break;
99: }
100: return r;
1.1 root 101: }
102:
1.1.1.3 root 103: static void update_ctrl(struct etrax_timer *t, int tnum)
1.1 root 104: {
1.1.1.3 root 105: unsigned int op;
106: unsigned int freq;
107: unsigned int freq_hz;
108: unsigned int div;
109: uint32_t ctrl;
110:
111: ptimer_state *timer;
112:
113: if (tnum == 0) {
114: ctrl = t->rw_tmr0_ctrl;
115: div = t->rw_tmr0_div;
116: timer = t->ptimer_t0;
117: } else {
118: ctrl = t->rw_tmr1_ctrl;
119: div = t->rw_tmr1_div;
120: timer = t->ptimer_t1;
121: }
122:
123:
124: op = ctrl & 3;
125: freq = ctrl >> 2;
126: freq_hz = 32000000;
127:
128: switch (freq)
129: {
130: case 0:
131: case 1:
132: D(printf ("extern or disabled timer clock?\n"));
133: break;
134: case 4: freq_hz = 29493000; break;
135: case 5: freq_hz = 32000000; break;
136: case 6: freq_hz = 32768000; break;
137: case 7: freq_hz = 100000000; break;
138: default:
139: abort();
140: break;
141: }
142:
143: D(printf ("freq_hz=%d div=%d\n", freq_hz, div));
144: ptimer_set_freq(timer, freq_hz);
145: ptimer_set_limit(timer, div, 0);
146:
147: switch (op)
148: {
149: case 0:
150: /* Load. */
151: ptimer_set_limit(timer, div, 1);
152: break;
153: case 1:
154: /* Hold. */
155: ptimer_stop(timer);
156: break;
157: case 2:
158: /* Run. */
159: ptimer_run(timer, 0);
160: break;
161: default:
162: abort();
163: break;
164: }
165: }
166:
167: static void timer_update_irq(struct etrax_timer *t)
168: {
169: t->r_intr &= ~(t->rw_ack_intr);
170: t->r_masked_intr = t->r_intr & t->rw_intr_mask;
171:
172: D(printf("%s: masked_intr=%x\n", __func__, t->r_masked_intr));
173: qemu_set_irq(t->irq, !!t->r_masked_intr);
1.1.1.2 root 174: }
175:
176: static void timer0_hit(void *opaque)
177: {
1.1.1.3 root 178: struct etrax_timer *t = opaque;
179: t->r_intr |= 1;
180: timer_update_irq(t);
1.1.1.2 root 181: }
182:
183: static void timer1_hit(void *opaque)
1.1 root 184: {
1.1.1.3 root 185: struct etrax_timer *t = opaque;
186: t->r_intr |= 2;
187: timer_update_irq(t);
1.1.1.2 root 188: }
189:
190: static void watchdog_hit(void *opaque)
191: {
1.1.1.3 root 192: struct etrax_timer *t = opaque;
193: if (t->wd_hits == 0) {
194: /* real hw gives a single tick before reseting but we are
195: a bit friendlier to compensate for our slower execution. */
196: ptimer_set_count(t->ptimer_wd, 10);
197: ptimer_run(t->ptimer_wd, 1);
198: qemu_irq_raise(t->nmi);
199: }
200: else
201: qemu_system_reset_request();
1.1.1.2 root 202:
1.1.1.3 root 203: t->wd_hits++;
204: }
205:
206: static inline void timer_watchdog_update(struct etrax_timer *t, uint32_t value)
207: {
208: unsigned int wd_en = t->rw_wd_ctrl & (1 << 8);
209: unsigned int wd_key = t->rw_wd_ctrl >> 9;
210: unsigned int wd_cnt = t->rw_wd_ctrl & 511;
211: unsigned int new_key = value >> 9 & ((1 << 7) - 1);
212: unsigned int new_cmd = (value >> 8) & 1;
213:
214: /* If the watchdog is enabled, they written key must match the
215: complement of the previous. */
216: wd_key = ~wd_key & ((1 << 7) - 1);
217:
218: if (wd_en && wd_key != new_key)
219: return;
220:
221: D(printf("en=%d new_key=%x oldkey=%x cmd=%d cnt=%d\n",
222: wd_en, new_key, wd_key, new_cmd, wd_cnt));
223:
224: if (t->wd_hits)
225: qemu_irq_lower(t->nmi);
226:
227: t->wd_hits = 0;
228:
229: ptimer_set_freq(t->ptimer_wd, 760);
230: if (wd_cnt == 0)
231: wd_cnt = 256;
232: ptimer_set_count(t->ptimer_wd, wd_cnt);
233: if (new_cmd)
234: ptimer_run(t->ptimer_wd, 1);
235: else
236: ptimer_stop(t->ptimer_wd);
237:
238: t->rw_wd_ctrl = value;
1.1 root 239: }
240:
241: static void
242: timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
243: {
1.1.1.3 root 244: struct etrax_timer *t = opaque;
1.1.1.2 root 245:
1.1.1.3 root 246: switch (addr)
247: {
248: case RW_TMR0_DIV:
249: t->rw_tmr0_div = value;
250: break;
251: case RW_TMR0_CTRL:
252: D(printf ("RW_TMR0_CTRL=%x\n", value));
253: t->rw_tmr0_ctrl = value;
254: update_ctrl(t, 0);
255: break;
256: case RW_TMR1_DIV:
257: t->rw_tmr1_div = value;
258: break;
259: case RW_TMR1_CTRL:
260: D(printf ("RW_TMR1_CTRL=%x\n", value));
261: t->rw_tmr1_ctrl = value;
262: update_ctrl(t, 1);
263: break;
264: case RW_INTR_MASK:
265: D(printf ("RW_INTR_MASK=%x\n", value));
266: t->rw_intr_mask = value;
267: timer_update_irq(t);
268: break;
269: case RW_WD_CTRL:
270: timer_watchdog_update(t, value);
271: break;
272: case RW_ACK_INTR:
273: t->rw_ack_intr = value;
274: timer_update_irq(t);
275: t->rw_ack_intr = 0;
276: break;
277: default:
278: printf ("%s " TARGET_FMT_plx " %x\n",
279: __func__, addr, value);
280: break;
281: }
1.1 root 282: }
283:
1.1.1.4 root 284: static CPUReadMemoryFunc * const timer_read[] = {
1.1.1.3 root 285: NULL, NULL,
286: &timer_readl,
1.1 root 287: };
288:
1.1.1.4 root 289: static CPUWriteMemoryFunc * const timer_write[] = {
1.1.1.3 root 290: NULL, NULL,
291: &timer_writel,
1.1 root 292: };
293:
1.1.1.2 root 294: static void etraxfs_timer_reset(void *opaque)
1.1 root 295: {
1.1.1.3 root 296: struct etrax_timer *t = opaque;
1.1 root 297:
1.1.1.3 root 298: ptimer_stop(t->ptimer_t0);
299: ptimer_stop(t->ptimer_t1);
300: ptimer_stop(t->ptimer_wd);
301: t->rw_wd_ctrl = 0;
302: t->r_intr = 0;
303: t->rw_intr_mask = 0;
304: qemu_irq_lower(t->irq);
305: }
1.1.1.2 root 306:
1.1.1.4 root 307: static int etraxfs_timer_init(SysBusDevice *dev)
1.1.1.3 root 308: {
309: struct etrax_timer *t = FROM_SYSBUS(typeof (*t), dev);
310: int timer_regs;
311:
312: t->bh_t0 = qemu_bh_new(timer0_hit, t);
313: t->bh_t1 = qemu_bh_new(timer1_hit, t);
314: t->bh_wd = qemu_bh_new(watchdog_hit, t);
315: t->ptimer_t0 = ptimer_init(t->bh_t0);
316: t->ptimer_t1 = ptimer_init(t->bh_t1);
317: t->ptimer_wd = ptimer_init(t->bh_wd);
318:
319: sysbus_init_irq(dev, &t->irq);
320: sysbus_init_irq(dev, &t->nmi);
321:
1.1.1.5 ! root 322: timer_regs = cpu_register_io_memory(timer_read, timer_write, t,
! 323: DEVICE_NATIVE_ENDIAN);
1.1.1.3 root 324: sysbus_init_mmio(dev, 0x5c, timer_regs);
1.1 root 325:
1.1.1.3 root 326: qemu_register_reset(etraxfs_timer_reset, t);
1.1.1.4 root 327: return 0;
1.1 root 328: }
1.1.1.3 root 329:
330: static void etraxfs_timer_register(void)
331: {
332: sysbus_register_dev("etraxfs,timer", sizeof (struct etrax_timer),
333: etraxfs_timer_init);
334: }
335:
336: device_init(etraxfs_timer_register)
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