![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to g364fb.c CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [Qemu by Fabrice Bellard] / qemu / hw|
Return to g364fb.c CVS log | Up to [Qemu by Fabrice Bellard] / qemu / hw |
1.1 root 1: /*
2: * QEMU G364 framebuffer Emulator.
3: *
1.1.1.6 root 4: * Copyright (c) 2007-2011 Herve Poussineau
1.1 root 5: *
6: * This program is free software; you can redistribute it and/or
7: * modify it under the terms of the GNU General Public License as
8: * published by the Free Software Foundation; either version 2 of
9: * the License, or (at your option) any later version.
10: *
11: * This program is distributed in the hope that it will be useful,
12: * but WITHOUT ANY WARRANTY; without even the implied warranty of
13: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14: * GNU General Public License for more details.
15: *
16: * You should have received a copy of the GNU General Public License along
1.1.1.2 root 17: * with this program; if not, see <http://www.gnu.org/licenses/>.
1.1 root 18: */
19:
20: #include "hw.h"
21: #include "console.h"
22: #include "pixel_ops.h"
1.1.1.6 root 23: #include "trace.h"
24: #include "sysbus.h"
1.1 root 25:
26: typedef struct G364State {
27: /* hardware */
28: uint8_t *vram;
1.1.1.6 root 29: uint32_t vram_size;
1.1 root 30: qemu_irq irq;
1.1.1.6 root 31: MemoryRegion mem_vram;
32: MemoryRegion mem_ctrl;
1.1 root 33: /* registers */
34: uint8_t color_palette[256][3];
35: uint8_t cursor_palette[3][3];
36: uint16_t cursor[512];
37: uint32_t cursor_position;
38: uint32_t ctla;
39: uint32_t top_of_screen;
40: uint32_t width, height; /* in pixels */
41: /* display refresh support */
42: DisplayState *ds;
43: int depth;
44: int blanked;
45: } G364State;
46:
1.1.1.6 root 47: #define REG_BOOT 0x000000
48: #define REG_DISPLAY 0x000118
49: #define REG_VDISPLAY 0x000150
50: #define REG_CTLA 0x000300
51: #define REG_TOP 0x000400
52: #define REG_CURS_PAL 0x000508
53: #define REG_CURS_POS 0x000638
54: #define REG_CLR_PAL 0x000800
55: #define REG_CURS_PAT 0x001000
56: #define REG_RESET 0x100000
1.1 root 57:
58: #define CTLA_FORCE_BLANK 0x00000400
59: #define CTLA_NO_CURSOR 0x00800000
60:
1.1.1.6 root 61: #define G364_PAGE_SIZE 4096
62:
63: static inline int check_dirty(G364State *s, ram_addr_t page)
1.1 root 64: {
1.1.1.7 ! root 65: return memory_region_get_dirty(&s->mem_vram, page, G364_PAGE_SIZE,
! 66: DIRTY_MEMORY_VGA);
1.1 root 67: }
68:
69: static inline void reset_dirty(G364State *s,
70: ram_addr_t page_min, ram_addr_t page_max)
71: {
1.1.1.6 root 72: memory_region_reset_dirty(&s->mem_vram,
73: page_min,
74: page_max + G364_PAGE_SIZE - page_min - 1,
75: DIRTY_MEMORY_VGA);
1.1 root 76: }
77:
78: static void g364fb_draw_graphic8(G364State *s)
79: {
80: int i, w;
81: uint8_t *vram;
82: uint8_t *data_display, *dd;
83: ram_addr_t page, page_min, page_max;
84: int x, y;
85: int xmin, xmax;
86: int ymin, ymax;
87: int xcursor, ycursor;
88: unsigned int (*rgb_to_pixel)(unsigned int r, unsigned int g, unsigned int b);
89:
90: switch (ds_get_bits_per_pixel(s->ds)) {
91: case 8:
92: rgb_to_pixel = rgb_to_pixel8;
93: w = 1;
94: break;
95: case 15:
96: rgb_to_pixel = rgb_to_pixel15;
97: w = 2;
98: break;
99: case 16:
100: rgb_to_pixel = rgb_to_pixel16;
101: w = 2;
102: break;
103: case 32:
104: rgb_to_pixel = rgb_to_pixel32;
105: w = 4;
106: break;
107: default:
1.1.1.6 root 108: hw_error("g364: unknown host depth %d",
109: ds_get_bits_per_pixel(s->ds));
1.1 root 110: return;
111: }
112:
1.1.1.6 root 113: page = 0;
1.1 root 114: page_min = (ram_addr_t)-1;
115: page_max = 0;
116:
117: x = y = 0;
118: xmin = s->width;
119: xmax = 0;
120: ymin = s->height;
121: ymax = 0;
122:
123: if (!(s->ctla & CTLA_NO_CURSOR)) {
124: xcursor = s->cursor_position >> 12;
125: ycursor = s->cursor_position & 0xfff;
126: } else {
127: xcursor = ycursor = -65;
128: }
129:
130: vram = s->vram + s->top_of_screen;
131: /* XXX: out of range in vram? */
132: data_display = dd = ds_get_data(s->ds);
133: while (y < s->height) {
1.1.1.6 root 134: if (check_dirty(s, page)) {
1.1 root 135: if (y < ymin)
136: ymin = ymax = y;
137: if (page_min == (ram_addr_t)-1)
138: page_min = page;
139: page_max = page;
140: if (x < xmin)
141: xmin = x;
1.1.1.6 root 142: for (i = 0; i < G364_PAGE_SIZE; i++) {
1.1 root 143: uint8_t index;
144: unsigned int color;
145: if (unlikely((y >= ycursor && y < ycursor + 64) &&
146: (x >= xcursor && x < xcursor + 64))) {
147: /* pointer area */
148: int xdiff = x - xcursor;
149: uint16_t curs = s->cursor[(y - ycursor) * 8 + xdiff / 8];
150: int op = (curs >> ((xdiff & 7) * 2)) & 3;
151: if (likely(op == 0)) {
152: /* transparent */
153: index = *vram;
154: color = (*rgb_to_pixel)(
155: s->color_palette[index][0],
156: s->color_palette[index][1],
157: s->color_palette[index][2]);
158: } else {
159: /* get cursor color */
160: index = op - 1;
161: color = (*rgb_to_pixel)(
162: s->cursor_palette[index][0],
163: s->cursor_palette[index][1],
164: s->cursor_palette[index][2]);
165: }
166: } else {
167: /* normal area */
168: index = *vram;
169: color = (*rgb_to_pixel)(
170: s->color_palette[index][0],
171: s->color_palette[index][1],
172: s->color_palette[index][2]);
173: }
174: memcpy(dd, &color, w);
175: dd += w;
176: x++;
177: vram++;
178: if (x == s->width) {
179: xmax = s->width - 1;
180: y++;
181: if (y == s->height) {
182: ymax = s->height - 1;
183: goto done;
184: }
185: data_display = dd = data_display + ds_get_linesize(s->ds);
186: xmin = 0;
187: x = 0;
188: }
189: }
190: if (x > xmax)
191: xmax = x;
192: if (y > ymax)
193: ymax = y;
194: } else {
195: int dy;
196: if (page_min != (ram_addr_t)-1) {
197: reset_dirty(s, page_min, page_max);
198: page_min = (ram_addr_t)-1;
199: page_max = 0;
200: dpy_update(s->ds, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1);
201: xmin = s->width;
202: xmax = 0;
203: ymin = s->height;
204: ymax = 0;
205: }
1.1.1.6 root 206: x += G364_PAGE_SIZE;
1.1 root 207: dy = x / s->width;
208: x = x % s->width;
209: y += dy;
1.1.1.6 root 210: vram += G364_PAGE_SIZE;
1.1 root 211: data_display += dy * ds_get_linesize(s->ds);
212: dd = data_display + x * w;
213: }
1.1.1.6 root 214: page += G364_PAGE_SIZE;
1.1 root 215: }
216:
217: done:
218: if (page_min != (ram_addr_t)-1) {
219: dpy_update(s->ds, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1);
220: reset_dirty(s, page_min, page_max);
221: }
222: }
223:
224: static void g364fb_draw_blank(G364State *s)
225: {
226: int i, w;
227: uint8_t *d;
228:
229: if (s->blanked) {
230: /* Screen is already blank. No need to redraw it */
231: return;
232: }
233:
234: w = s->width * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
235: d = ds_get_data(s->ds);
236: for (i = 0; i < s->height; i++) {
237: memset(d, 0, w);
238: d += ds_get_linesize(s->ds);
239: }
240:
241: dpy_update(s->ds, 0, 0, s->width, s->height);
242: s->blanked = 1;
243: }
244:
245: static void g364fb_update_display(void *opaque)
246: {
247: G364State *s = opaque;
248:
1.1.1.6 root 249: qemu_flush_coalesced_mmio_buffer();
250:
1.1 root 251: if (s->width == 0 || s->height == 0)
252: return;
253:
254: if (s->width != ds_get_width(s->ds) || s->height != ds_get_height(s->ds)) {
255: qemu_console_resize(s->ds, s->width, s->height);
256: }
257:
258: if (s->ctla & CTLA_FORCE_BLANK) {
259: g364fb_draw_blank(s);
260: } else if (s->depth == 8) {
261: g364fb_draw_graphic8(s);
262: } else {
1.1.1.6 root 263: error_report("g364: unknown guest depth %d", s->depth);
1.1 root 264: }
265:
266: qemu_irq_raise(s->irq);
267: }
268:
1.1.1.3 root 269: static inline void g364fb_invalidate_display(void *opaque)
1.1 root 270: {
271: G364State *s = opaque;
272:
273: s->blanked = 0;
1.1.1.7 ! root 274: memory_region_set_dirty(&s->mem_vram, 0, s->vram_size);
1.1 root 275: }
276:
1.1.1.6 root 277: static void g364fb_reset(G364State *s)
1.1 root 278: {
279: qemu_irq_lower(s->irq);
280:
281: memset(s->color_palette, 0, sizeof(s->color_palette));
282: memset(s->cursor_palette, 0, sizeof(s->cursor_palette));
283: memset(s->cursor, 0, sizeof(s->cursor));
284: s->cursor_position = 0;
285: s->ctla = 0;
286: s->top_of_screen = 0;
287: s->width = s->height = 0;
288: memset(s->vram, 0, s->vram_size);
1.1.1.6 root 289: g364fb_invalidate_display(s);
1.1 root 290: }
291:
1.1.1.7 ! root 292: static void g364fb_screen_dump(void *opaque, const char *filename, bool cswitch)
1.1 root 293: {
294: G364State *s = opaque;
295: int y, x;
296: uint8_t index;
297: uint8_t *data_buffer;
298: FILE *f;
299:
1.1.1.6 root 300: qemu_flush_coalesced_mmio_buffer();
301:
1.1 root 302: if (s->depth != 8) {
1.1.1.6 root 303: error_report("g364: unknown guest depth %d", s->depth);
1.1 root 304: return;
305: }
306:
307: f = fopen(filename, "wb");
308: if (!f)
309: return;
310:
311: if (s->ctla & CTLA_FORCE_BLANK) {
312: /* blank screen */
313: fprintf(f, "P4\n%d %d\n",
314: s->width, s->height);
315: for (y = 0; y < s->height; y++)
316: for (x = 0; x < s->width; x++)
317: fputc(0, f);
318: } else {
319: data_buffer = s->vram + s->top_of_screen;
320: fprintf(f, "P6\n%d %d\n%d\n",
321: s->width, s->height, 255);
322: for (y = 0; y < s->height; y++)
323: for (x = 0; x < s->width; x++, data_buffer++) {
324: index = *data_buffer;
325: fputc(s->color_palette[index][0], f);
326: fputc(s->color_palette[index][1], f);
327: fputc(s->color_palette[index][2], f);
328: }
329: }
330:
331: fclose(f);
332: }
333:
334: /* called for accesses to io ports */
1.1.1.6 root 335: static uint64_t g364fb_ctrl_read(void *opaque,
336: target_phys_addr_t addr,
337: unsigned int size)
1.1 root 338: {
339: G364State *s = opaque;
340: uint32_t val;
341:
342: if (addr >= REG_CURS_PAT && addr < REG_CURS_PAT + 0x1000) {
343: /* cursor pattern */
344: int idx = (addr - REG_CURS_PAT) >> 3;
345: val = s->cursor[idx];
346: } else if (addr >= REG_CURS_PAL && addr < REG_CURS_PAL + 0x18) {
347: /* cursor palette */
348: int idx = (addr - REG_CURS_PAL) >> 3;
349: val = ((uint32_t)s->cursor_palette[idx][0] << 16);
350: val |= ((uint32_t)s->cursor_palette[idx][1] << 8);
351: val |= ((uint32_t)s->cursor_palette[idx][2] << 0);
352: } else {
353: switch (addr) {
354: case REG_DISPLAY:
355: val = s->width / 4;
356: break;
357: case REG_VDISPLAY:
358: val = s->height * 2;
359: break;
360: case REG_CTLA:
361: val = s->ctla;
362: break;
363: default:
364: {
1.1.1.6 root 365: error_report("g364: invalid read at [" TARGET_FMT_plx "]",
366: addr);
1.1 root 367: val = 0;
368: break;
369: }
370: }
371: }
372:
1.1.1.6 root 373: trace_g364fb_read(addr, val);
1.1 root 374:
375: return val;
376: }
377:
378: static void g364fb_update_depth(G364State *s)
379: {
1.1.1.3 root 380: static const int depths[8] = { 1, 2, 4, 8, 15, 16, 0 };
1.1 root 381: s->depth = depths[(s->ctla & 0x00700000) >> 20];
382: }
383:
384: static void g364_invalidate_cursor_position(G364State *s)
385: {
1.1.1.7 ! root 386: int ymin, ymax, start, end;
1.1 root 387:
388: /* invalidate only near the cursor */
389: ymin = s->cursor_position & 0xfff;
390: ymax = MIN(s->height, ymin + 64);
391: start = ymin * ds_get_linesize(s->ds);
392: end = (ymax + 1) * ds_get_linesize(s->ds);
393:
1.1.1.7 ! root 394: memory_region_set_dirty(&s->mem_vram, start, end - start);
1.1 root 395: }
396:
1.1.1.6 root 397: static void g364fb_ctrl_write(void *opaque,
398: target_phys_addr_t addr,
399: uint64_t val,
400: unsigned int size)
1.1 root 401: {
402: G364State *s = opaque;
403:
1.1.1.6 root 404: trace_g364fb_write(addr, val);
1.1 root 405:
406: if (addr >= REG_CLR_PAL && addr < REG_CLR_PAL + 0x800) {
407: /* color palette */
408: int idx = (addr - REG_CLR_PAL) >> 3;
409: s->color_palette[idx][0] = (val >> 16) & 0xff;
410: s->color_palette[idx][1] = (val >> 8) & 0xff;
411: s->color_palette[idx][2] = val & 0xff;
412: g364fb_invalidate_display(s);
413: } else if (addr >= REG_CURS_PAT && addr < REG_CURS_PAT + 0x1000) {
414: /* cursor pattern */
415: int idx = (addr - REG_CURS_PAT) >> 3;
416: s->cursor[idx] = val;
417: g364fb_invalidate_display(s);
418: } else if (addr >= REG_CURS_PAL && addr < REG_CURS_PAL + 0x18) {
419: /* cursor palette */
420: int idx = (addr - REG_CURS_PAL) >> 3;
421: s->cursor_palette[idx][0] = (val >> 16) & 0xff;
422: s->cursor_palette[idx][1] = (val >> 8) & 0xff;
423: s->cursor_palette[idx][2] = val & 0xff;
424: g364fb_invalidate_display(s);
425: } else {
426: switch (addr) {
1.1.1.6 root 427: case REG_BOOT: /* Boot timing */
428: case 0x00108: /* Line timing: half sync */
429: case 0x00110: /* Line timing: back porch */
430: case 0x00120: /* Line timing: short display */
431: case 0x00128: /* Frame timing: broad pulse */
432: case 0x00130: /* Frame timing: v sync */
433: case 0x00138: /* Frame timing: v preequalise */
434: case 0x00140: /* Frame timing: v postequalise */
435: case 0x00148: /* Frame timing: v blank */
436: case 0x00158: /* Line timing: line time */
437: case 0x00160: /* Frame store: line start */
438: case 0x00168: /* vram cycle: mem init */
439: case 0x00170: /* vram cycle: transfer delay */
440: case 0x00200: /* vram cycle: mask register */
441: /* ignore */
442: break;
443: case REG_TOP:
444: s->top_of_screen = val;
445: g364fb_invalidate_display(s);
446: break;
447: case REG_DISPLAY:
448: s->width = val * 4;
449: break;
450: case REG_VDISPLAY:
451: s->height = val / 2;
452: break;
453: case REG_CTLA:
454: s->ctla = val;
455: g364fb_update_depth(s);
456: g364fb_invalidate_display(s);
457: break;
458: case REG_CURS_POS:
459: g364_invalidate_cursor_position(s);
460: s->cursor_position = val;
461: g364_invalidate_cursor_position(s);
462: break;
463: case REG_RESET:
464: g364fb_reset(s);
465: break;
466: default:
467: error_report("g364: invalid write of 0x%" PRIx64
468: " at [" TARGET_FMT_plx "]", val, addr);
469: break;
1.1 root 470: }
471: }
472: qemu_irq_lower(s->irq);
473: }
474:
1.1.1.6 root 475: static const MemoryRegionOps g364fb_ctrl_ops = {
476: .read = g364fb_ctrl_read,
477: .write = g364fb_ctrl_write,
478: .endianness = DEVICE_LITTLE_ENDIAN,
479: .impl.min_access_size = 4,
480: .impl.max_access_size = 4,
1.1 root 481: };
482:
1.1.1.6 root 483: static int g364fb_post_load(void *opaque, int version_id)
1.1 root 484: {
485: G364State *s = opaque;
486:
487: /* force refresh */
488: g364fb_update_depth(s);
489: g364fb_invalidate_display(s);
490:
491: return 0;
492: }
493:
1.1.1.6 root 494: static const VMStateDescription vmstate_g364fb = {
495: .name = "g364fb",
496: .version_id = 1,
497: .minimum_version_id = 1,
498: .minimum_version_id_old = 1,
499: .post_load = g364fb_post_load,
500: .fields = (VMStateField[]) {
501: VMSTATE_VBUFFER_UINT32(vram, G364State, 1, NULL, 0, vram_size),
502: VMSTATE_BUFFER_UNSAFE(color_palette, G364State, 0, 256 * 3),
503: VMSTATE_BUFFER_UNSAFE(cursor_palette, G364State, 0, 9),
504: VMSTATE_UINT16_ARRAY(cursor, G364State, 512),
505: VMSTATE_UINT32(cursor_position, G364State),
506: VMSTATE_UINT32(ctla, G364State),
507: VMSTATE_UINT32(top_of_screen, G364State),
508: VMSTATE_UINT32(width, G364State),
509: VMSTATE_UINT32(height, G364State),
510: VMSTATE_END_OF_LIST()
511: }
512: };
1.1 root 513:
1.1.1.6 root 514: static void g364fb_init(DeviceState *dev, G364State *s)
515: {
516: s->vram = g_malloc0(s->vram_size);
1.1 root 517:
518: s->ds = graphic_console_init(g364fb_update_display,
519: g364fb_invalidate_display,
520: g364fb_screen_dump, NULL, s);
521:
1.1.1.6 root 522: memory_region_init_io(&s->mem_ctrl, &g364fb_ctrl_ops, s, "ctrl", 0x180000);
1.1.1.7 ! root 523: memory_region_init_ram_ptr(&s->mem_vram, "vram",
1.1.1.6 root 524: s->vram_size, s->vram);
1.1.1.7 ! root 525: vmstate_register_ram(&s->mem_vram, dev);
1.1.1.6 root 526: memory_region_set_coalescing(&s->mem_vram);
527: }
528:
529: typedef struct {
530: SysBusDevice busdev;
531: G364State g364;
532: } G364SysBusState;
533:
534: static int g364fb_sysbus_init(SysBusDevice *dev)
535: {
536: G364State *s = &FROM_SYSBUS(G364SysBusState, dev)->g364;
1.1 root 537:
1.1.1.6 root 538: g364fb_init(&dev->qdev, s);
539: sysbus_init_irq(dev, &s->irq);
1.1.1.7 ! root 540: sysbus_init_mmio(dev, &s->mem_ctrl);
! 541: sysbus_init_mmio(dev, &s->mem_vram);
1.1 root 542:
543: return 0;
544: }
1.1.1.6 root 545:
546: static void g364fb_sysbus_reset(DeviceState *d)
547: {
548: G364SysBusState *s = DO_UPCAST(G364SysBusState, busdev.qdev, d);
549: g364fb_reset(&s->g364);
550: }
551:
1.1.1.7 ! root 552: static Property g364fb_sysbus_properties[] = {
! 553: DEFINE_PROP_HEX32("vram_size", G364SysBusState, g364.vram_size,
! 554: 8 * 1024 * 1024),
! 555: DEFINE_PROP_END_OF_LIST(),
! 556: };
! 557:
! 558: static void g364fb_sysbus_class_init(ObjectClass *klass, void *data)
! 559: {
! 560: DeviceClass *dc = DEVICE_CLASS(klass);
! 561: SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
! 562:
! 563: k->init = g364fb_sysbus_init;
! 564: dc->desc = "G364 framebuffer";
! 565: dc->reset = g364fb_sysbus_reset;
! 566: dc->vmsd = &vmstate_g364fb;
! 567: dc->props = g364fb_sysbus_properties;
! 568: }
! 569:
! 570: static TypeInfo g364fb_sysbus_info = {
! 571: .name = "sysbus-g364",
! 572: .parent = TYPE_SYS_BUS_DEVICE,
! 573: .instance_size = sizeof(G364SysBusState),
! 574: .class_init = g364fb_sysbus_class_init,
1.1.1.6 root 575: };
576:
1.1.1.7 ! root 577: static void g364fb_register_types(void)
1.1.1.6 root 578: {
1.1.1.7 ! root 579: type_register_static(&g364fb_sysbus_info);
1.1.1.6 root 580: }
581:
1.1.1.7 ! root 582: type_init(g364fb_register_types)
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.