Diff for /qemu/hw/grackle_pci.c between versions 1.1.1.1 and 1.1.1.2

version 1.1.1.1, 2018/04/24 16:43:36 version 1.1.1.2, 2018/04/24 16:45:57
Line 74  static CPUReadMemoryFunc *pci_grackle_re Line 74  static CPUReadMemoryFunc *pci_grackle_re
     &pci_host_data_readl,      &pci_host_data_readl,
 };  };
   
 /* XXX: we do not simulate the hardware - we rely on the BIOS to  /* Don't know if this matches real hardware, but it agrees with OHW.  */
    set correctly for irq line field */  static int pci_grackle_map_irq(PCIDevice *pci_dev, int irq_num)
 static void pci_grackle_set_irq(PCIDevice *d, void *pic, int irq_num, int level)  
 {  {
     heathrow_pic_set_irq(pic, d->config[PCI_INTERRUPT_LINE], level);      return (irq_num + (pci_dev->devfn >> 3)) & 3;
   }
   
   static void pci_grackle_set_irq(void *pic, int irq_num, int level)
   {
       heathrow_pic_set_irq(pic, irq_num + 8, level);
 }  }
   
 PCIBus *pci_grackle_init(uint32_t base, void *pic)  PCIBus *pci_grackle_init(uint32_t base, void *pic)
Line 88  PCIBus *pci_grackle_init(uint32_t base,  Line 92  PCIBus *pci_grackle_init(uint32_t base, 
     int pci_mem_config, pci_mem_data;      int pci_mem_config, pci_mem_data;
   
     s = qemu_mallocz(sizeof(GrackleState));      s = qemu_mallocz(sizeof(GrackleState));
     s->bus = pci_register_bus(pci_grackle_set_irq, pic, 0);      s->bus = pci_register_bus(pci_grackle_set_irq, pci_grackle_map_irq,
                                 pic, 0, 0);
   
     pci_mem_config = cpu_register_io_memory(0, pci_grackle_config_read,       pci_mem_config = cpu_register_io_memory(0, pci_grackle_config_read, 
                                             pci_grackle_config_write, s);                                              pci_grackle_config_write, s);

Removed from v.1.1.1.1  
changed lines
  Added in v.1.1.1.2


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