Diff for /qemu/hw/grackle_pci.c between versions 1.1.1.3 and 1.1.1.4

version 1.1.1.3, 2018/04/24 16:48:43 version 1.1.1.4, 2018/04/24 16:53:20
Line 27 Line 27
 #include "ppc_mac.h"  #include "ppc_mac.h"
 #include "pci.h"  #include "pci.h"
   
   /* debug Grackle */
   //#define DEBUG_GRACKLE
   
   #ifdef DEBUG_GRACKLE
   #define GRACKLE_DPRINTF(fmt, args...) \
   do { printf("GRACKLE: " fmt , ##args); } while (0)
   #else
   #define GRACKLE_DPRINTF(fmt, args...)
   #endif
   
 typedef target_phys_addr_t pci_addr_t;  typedef target_phys_addr_t pci_addr_t;
 #include "pci_host.h"  #include "pci_host.h"
   
Line 36  static void pci_grackle_config_writel (v Line 46  static void pci_grackle_config_writel (v
                                        uint32_t val)                                         uint32_t val)
 {  {
     GrackleState *s = opaque;      GrackleState *s = opaque;
   
       GRACKLE_DPRINTF("config_writel addr " TARGET_FMT_plx " val %x\n", addr,
                       val);
 #ifdef TARGET_WORDS_BIGENDIAN  #ifdef TARGET_WORDS_BIGENDIAN
     val = bswap32(val);      val = bswap32(val);
 #endif  #endif
Line 51  static uint32_t pci_grackle_config_readl Line 64  static uint32_t pci_grackle_config_readl
 #ifdef TARGET_WORDS_BIGENDIAN  #ifdef TARGET_WORDS_BIGENDIAN
     val = bswap32(val);      val = bswap32(val);
 #endif  #endif
       GRACKLE_DPRINTF("config_readl addr " TARGET_FMT_plx " val %x\n", addr,
                       val);
     return val;      return val;
 }  }
   
Line 86  static int pci_grackle_map_irq(PCIDevice Line 101  static int pci_grackle_map_irq(PCIDevice
   
 static void pci_grackle_set_irq(qemu_irq *pic, int irq_num, int level)  static void pci_grackle_set_irq(qemu_irq *pic, int irq_num, int level)
 {  {
       GRACKLE_DPRINTF("set_irq num %d level %d\n", irq_num, level);
     qemu_set_irq(pic[irq_num + 0x15], level);      qemu_set_irq(pic[irq_num + 0x15], level);
 }  }
   
   static void pci_grackle_save(QEMUFile* f, void *opaque)
   {
       PCIDevice *d = opaque;
   
       pci_device_save(d, f);
   }
   
   static int pci_grackle_load(QEMUFile* f, void *opaque, int version_id)
   {
       PCIDevice *d = opaque;
   
       if (version_id != 1)
           return -EINVAL;
   
       return pci_device_load(d, f);
   }
   
   static void pci_grackle_reset(void *opaque)
   {
   }
   
 PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic)  PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic)
 {  {
     GrackleState *s;      GrackleState *s;
Line 107  PCIBus *pci_grackle_init(uint32_t base,  Line 144  PCIBus *pci_grackle_init(uint32_t base, 
     cpu_register_physical_memory(base + 0x00200000, 0x1000, pci_mem_data);      cpu_register_physical_memory(base + 0x00200000, 0x1000, pci_mem_data);
     d = pci_register_device(s->bus, "Grackle host bridge", sizeof(PCIDevice),      d = pci_register_device(s->bus, "Grackle host bridge", sizeof(PCIDevice),
                             0, NULL, NULL);                              0, NULL, NULL);
     d->config[0x00] = 0x57; // vendor_id      pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_MOTOROLA);
     d->config[0x01] = 0x10;      pci_config_set_device_id(d->config, PCI_DEVICE_ID_MOTOROLA_MPC106);
     d->config[0x02] = 0x02; // device_id  
     d->config[0x03] = 0x00;  
     d->config[0x08] = 0x00; // revision      d->config[0x08] = 0x00; // revision
     d->config[0x09] = 0x01;      d->config[0x09] = 0x01;
     d->config[0x0a] = 0x00; // class_sub = host      pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
     d->config[0x0b] = 0x06; // class_base = PCI_bridge  
     d->config[0x0e] = 0x00; // header_type      d->config[0x0e] = 0x00; // header_type
   
 #if 0  #if 0
     /* PCI2PCI bridge same values as PearPC - check this */      /* PCI2PCI bridge same values as PearPC - check this */
     d->config[0x00] = 0x11; // vendor_id      pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_DEC);
     d->config[0x01] = 0x10;      pci_config_set_device_id(d->config, PCI_DEVICE_ID_DEC_21154);
     d->config[0x02] = 0x26; // device_id  
     d->config[0x03] = 0x00;  
     d->config[0x08] = 0x02; // revision      d->config[0x08] = 0x02; // revision
     d->config[0x0a] = 0x04; // class_sub = pci2pci      pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI);
     d->config[0x0b] = 0x06; // class_base = PCI_bridge  
     d->config[0x0e] = 0x01; // header_type      d->config[0x0e] = 0x01; // header_type
   
     d->config[0x18] = 0x0;  // primary_bus      d->config[0x18] = 0x0;  // primary_bus
Line 144  PCIBus *pci_grackle_init(uint32_t base,  Line 175  PCIBus *pci_grackle_init(uint32_t base, 
     d->config[0x26] = 0x00; // prefetchable_memory_limit      d->config[0x26] = 0x00; // prefetchable_memory_limit
     d->config[0x27] = 0x85;      d->config[0x27] = 0x85;
 #endif  #endif
       register_savevm("grackle", 0, 1, pci_grackle_save, pci_grackle_load, d);
       qemu_register_reset(pci_grackle_reset, d);
       pci_grackle_reset(d);
   
     return s->bus;      return s->bus;
 }  }
   

Removed from v.1.1.1.3  
changed lines
  Added in v.1.1.1.4


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