Annotation of qemu/hw/grackle_pci.c, revision 1.1.1.1

1.1       root        1: /*
                      2:  * QEMU Grackle (heathrow PPC) PCI host
                      3:  *
                      4:  * Copyright (c) 2006 Fabrice Bellard
                      5:  * 
                      6:  * Permission is hereby granted, free of charge, to any person obtaining a copy
                      7:  * of this software and associated documentation files (the "Software"), to deal
                      8:  * in the Software without restriction, including without limitation the rights
                      9:  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
                     10:  * copies of the Software, and to permit persons to whom the Software is
                     11:  * furnished to do so, subject to the following conditions:
                     12:  *
                     13:  * The above copyright notice and this permission notice shall be included in
                     14:  * all copies or substantial portions of the Software.
                     15:  *
                     16:  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
                     17:  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
                     18:  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
                     19:  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
                     20:  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
                     21:  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
                     22:  * THE SOFTWARE.
                     23:  */
                     24: 
                     25: #include "vl.h"
                     26: typedef target_phys_addr_t pci_addr_t;
                     27: #include "pci_host.h"
                     28: 
                     29: typedef PCIHostState GrackleState;
                     30: 
                     31: static void pci_grackle_config_writel (void *opaque, target_phys_addr_t addr,
                     32:                                        uint32_t val)
                     33: {
                     34:     GrackleState *s = opaque;
                     35: #ifdef TARGET_WORDS_BIGENDIAN
                     36:     val = bswap32(val);
                     37: #endif
                     38:     s->config_reg = val;
                     39: }
                     40: 
                     41: static uint32_t pci_grackle_config_readl (void *opaque, target_phys_addr_t addr)
                     42: {
                     43:     GrackleState *s = opaque;
                     44:     uint32_t val;
                     45: 
                     46:     val = s->config_reg;
                     47: #ifdef TARGET_WORDS_BIGENDIAN
                     48:     val = bswap32(val);
                     49: #endif
                     50:     return val;
                     51: }
                     52: 
                     53: static CPUWriteMemoryFunc *pci_grackle_config_write[] = {
                     54:     &pci_grackle_config_writel,
                     55:     &pci_grackle_config_writel,
                     56:     &pci_grackle_config_writel,
                     57: };
                     58: 
                     59: static CPUReadMemoryFunc *pci_grackle_config_read[] = {
                     60:     &pci_grackle_config_readl,
                     61:     &pci_grackle_config_readl,
                     62:     &pci_grackle_config_readl,
                     63: };
                     64: 
                     65: static CPUWriteMemoryFunc *pci_grackle_write[] = {
                     66:     &pci_host_data_writeb,
                     67:     &pci_host_data_writew,
                     68:     &pci_host_data_writel,
                     69: };
                     70: 
                     71: static CPUReadMemoryFunc *pci_grackle_read[] = {
                     72:     &pci_host_data_readb,
                     73:     &pci_host_data_readw,
                     74:     &pci_host_data_readl,
                     75: };
                     76: 
                     77: /* XXX: we do not simulate the hardware - we rely on the BIOS to
                     78:    set correctly for irq line field */
                     79: static void pci_grackle_set_irq(PCIDevice *d, void *pic, int irq_num, int level)
                     80: {
                     81:     heathrow_pic_set_irq(pic, d->config[PCI_INTERRUPT_LINE], level);
                     82: }
                     83: 
                     84: PCIBus *pci_grackle_init(uint32_t base, void *pic)
                     85: {
                     86:     GrackleState *s;
                     87:     PCIDevice *d;
                     88:     int pci_mem_config, pci_mem_data;
                     89: 
                     90:     s = qemu_mallocz(sizeof(GrackleState));
                     91:     s->bus = pci_register_bus(pci_grackle_set_irq, pic, 0);
                     92: 
                     93:     pci_mem_config = cpu_register_io_memory(0, pci_grackle_config_read, 
                     94:                                             pci_grackle_config_write, s);
                     95:     pci_mem_data = cpu_register_io_memory(0, pci_grackle_read,
                     96:                                           pci_grackle_write, s);
                     97:     cpu_register_physical_memory(base, 0x1000, pci_mem_config);
                     98:     cpu_register_physical_memory(base + 0x00200000, 0x1000, pci_mem_data);
                     99:     d = pci_register_device(s->bus, "Grackle host bridge", sizeof(PCIDevice), 
                    100:                             0, NULL, NULL);
                    101:     d->config[0x00] = 0x57; // vendor_id
                    102:     d->config[0x01] = 0x10;
                    103:     d->config[0x02] = 0x02; // device_id
                    104:     d->config[0x03] = 0x00;
                    105:     d->config[0x08] = 0x00; // revision
                    106:     d->config[0x09] = 0x01;
                    107:     d->config[0x0a] = 0x00; // class_sub = host
                    108:     d->config[0x0b] = 0x06; // class_base = PCI_bridge
                    109:     d->config[0x0e] = 0x00; // header_type
                    110: 
                    111:     d->config[0x18] = 0x00;  // primary_bus
                    112:     d->config[0x19] = 0x01;  // secondary_bus
                    113:     d->config[0x1a] = 0x00;  // subordinate_bus
                    114:     d->config[0x1c] = 0x00;
                    115:     d->config[0x1d] = 0x00;
                    116:     
                    117:     d->config[0x20] = 0x00; // memory_base
                    118:     d->config[0x21] = 0x00;
                    119:     d->config[0x22] = 0x01; // memory_limit
                    120:     d->config[0x23] = 0x00;
                    121:     
                    122:     d->config[0x24] = 0x00; // prefetchable_memory_base
                    123:     d->config[0x25] = 0x00;
                    124:     d->config[0x26] = 0x00; // prefetchable_memory_limit
                    125:     d->config[0x27] = 0x00;
                    126: 
                    127: #if 0
                    128:     /* PCI2PCI bridge same values as PearPC - check this */
                    129:     d->config[0x00] = 0x11; // vendor_id
                    130:     d->config[0x01] = 0x10;
                    131:     d->config[0x02] = 0x26; // device_id
                    132:     d->config[0x03] = 0x00;
                    133:     d->config[0x08] = 0x02; // revision
                    134:     d->config[0x0a] = 0x04; // class_sub = pci2pci
                    135:     d->config[0x0b] = 0x06; // class_base = PCI_bridge
                    136:     d->config[0x0e] = 0x01; // header_type
                    137: 
                    138:     d->config[0x18] = 0x0;  // primary_bus
                    139:     d->config[0x19] = 0x1;  // secondary_bus
                    140:     d->config[0x1a] = 0x1;  // subordinate_bus
                    141:     d->config[0x1c] = 0x10; // io_base
                    142:     d->config[0x1d] = 0x20; // io_limit
                    143:     
                    144:     d->config[0x20] = 0x80; // memory_base
                    145:     d->config[0x21] = 0x80;
                    146:     d->config[0x22] = 0x90; // memory_limit
                    147:     d->config[0x23] = 0x80;
                    148:     
                    149:     d->config[0x24] = 0x00; // prefetchable_memory_base
                    150:     d->config[0x25] = 0x84;
                    151:     d->config[0x26] = 0x00; // prefetchable_memory_limit
                    152:     d->config[0x27] = 0x85;
                    153: #endif
                    154:     return s->bus;
                    155: }
                    156: 

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