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1.1 root 1: /*
2: * QEMU GRLIB Components
3: *
4: * Copyright (c) 2010-2011 AdaCore
5: *
6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
24:
25: #ifndef _GRLIB_H_
26: #define _GRLIB_H_
27:
28: #include "qdev.h"
29: #include "sysbus.h"
30:
31: /* Emulation of GrLib device is base on the GRLIB IP Core User's Manual:
32: * http://www.gaisler.com/products/grlib/grip.pdf
33: */
34:
35: /* IRQMP */
36:
37: typedef void (*set_pil_in_fn) (void *opaque, uint32_t pil_in);
38:
39: void grlib_irqmp_set_irq(void *opaque, int irq, int level);
40:
41: void grlib_irqmp_ack(DeviceState *dev, int intno);
42:
43: static inline
44: DeviceState *grlib_irqmp_create(target_phys_addr_t base,
1.1.1.2 ! root 45: CPUSPARCState *env,
1.1 root 46: qemu_irq **cpu_irqs,
47: uint32_t nr_irqs,
48: set_pil_in_fn set_pil_in)
49: {
50: DeviceState *dev;
51:
52: assert(cpu_irqs != NULL);
53:
54: dev = qdev_create(NULL, "grlib,irqmp");
55: qdev_prop_set_ptr(dev, "set_pil_in", set_pil_in);
56: qdev_prop_set_ptr(dev, "set_pil_in_opaque", env);
57:
58: if (qdev_init(dev)) {
59: return NULL;
60: }
61:
62: env->irq_manager = dev;
63:
64: sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
65:
66: *cpu_irqs = qemu_allocate_irqs(grlib_irqmp_set_irq,
67: dev,
68: nr_irqs);
69:
70: return dev;
71: }
72:
73: /* GPTimer */
74:
75: static inline
76: DeviceState *grlib_gptimer_create(target_phys_addr_t base,
77: uint32_t nr_timers,
78: uint32_t freq,
79: qemu_irq *cpu_irqs,
80: int base_irq)
81: {
82: DeviceState *dev;
83: int i;
84:
85: dev = qdev_create(NULL, "grlib,gptimer");
86: qdev_prop_set_uint32(dev, "nr-timers", nr_timers);
87: qdev_prop_set_uint32(dev, "frequency", freq);
88: qdev_prop_set_uint32(dev, "irq-line", base_irq);
89:
90: if (qdev_init(dev)) {
91: return NULL;
92: }
93:
94: sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
95:
96: for (i = 0; i < nr_timers; i++) {
97: sysbus_connect_irq(sysbus_from_qdev(dev), i, cpu_irqs[base_irq + i]);
98: }
99:
100: return dev;
101: }
102:
103: /* APB UART */
104:
105: static inline
106: DeviceState *grlib_apbuart_create(target_phys_addr_t base,
107: CharDriverState *serial,
108: qemu_irq irq)
109: {
110: DeviceState *dev;
111:
112: dev = qdev_create(NULL, "grlib,apbuart");
113: qdev_prop_set_chr(dev, "chrdev", serial);
114:
115: if (qdev_init(dev)) {
116: return NULL;
117: }
118:
119: sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
120:
121: sysbus_connect_irq(sysbus_from_qdev(dev), 0, irq);
122:
123: return dev;
124: }
125:
126: #endif /* ! _GRLIB_H_ */
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