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1.1 root 1: /*
1.1.1.3 root 2: * Heathrow PIC support (OldWorld PowerMac)
3: *
4: * Copyright (c) 2005-2007 Fabrice Bellard
5: * Copyright (c) 2007 Jocelyn Mayer
6: *
1.1 root 7: * Permission is hereby granted, free of charge, to any person obtaining a copy
8: * of this software and associated documentation files (the "Software"), to deal
9: * in the Software without restriction, including without limitation the rights
10: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11: * copies of the Software, and to permit persons to whom the Software is
12: * furnished to do so, subject to the following conditions:
13: *
14: * The above copyright notice and this permission notice shall be included in
15: * all copies or substantial portions of the Software.
16: *
17: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23: * THE SOFTWARE.
24: */
1.1.1.3 root 25: #include "hw.h"
26: #include "ppc_mac.h"
1.1 root 27:
1.1.1.4 root 28: /* debug PIC */
29: //#define DEBUG_PIC
30:
31: #ifdef DEBUG_PIC
1.1.1.5 root 32: #define PIC_DPRINTF(fmt, ...) \
33: do { printf("PIC: " fmt , ## __VA_ARGS__); } while (0)
1.1.1.4 root 34: #else
1.1.1.5 root 35: #define PIC_DPRINTF(fmt, ...)
1.1.1.4 root 36: #endif
1.1 root 37:
38: typedef struct HeathrowPIC {
39: uint32_t events;
40: uint32_t mask;
41: uint32_t levels;
42: uint32_t level_triggered;
43: } HeathrowPIC;
44:
1.1.1.3 root 45: typedef struct HeathrowPICS {
1.1 root 46: HeathrowPIC pics[2];
1.1.1.3 root 47: qemu_irq *irqs;
48: } HeathrowPICS;
1.1 root 49:
50: static inline int check_irq(HeathrowPIC *pic)
51: {
52: return (pic->events | (pic->levels & pic->level_triggered)) & pic->mask;
53: }
54:
55: /* update the CPU irq state */
56: static void heathrow_pic_update(HeathrowPICS *s)
57: {
58: if (check_irq(&s->pics[0]) || check_irq(&s->pics[1])) {
1.1.1.3 root 59: qemu_irq_raise(s->irqs[0]);
1.1 root 60: } else {
1.1.1.3 root 61: qemu_irq_lower(s->irqs[0]);
1.1 root 62: }
63: }
64:
65: static void pic_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
66: {
67: HeathrowPICS *s = opaque;
68: HeathrowPIC *pic;
69: unsigned int n;
70:
71: n = ((addr & 0xfff) - 0x10) >> 4;
1.1.1.4 root 72: PIC_DPRINTF("writel: " TARGET_FMT_plx " %u: %08x\n", addr, n, value);
1.1 root 73: if (n >= 2)
74: return;
75: pic = &s->pics[n];
76: switch(addr & 0xf) {
77: case 0x04:
78: pic->mask = value;
79: heathrow_pic_update(s);
80: break;
81: case 0x08:
82: /* do not reset level triggered IRQs */
83: value &= ~pic->level_triggered;
84: pic->events &= ~value;
85: heathrow_pic_update(s);
86: break;
87: default:
88: break;
89: }
90: }
91:
92: static uint32_t pic_readl (void *opaque, target_phys_addr_t addr)
93: {
94: HeathrowPICS *s = opaque;
95: HeathrowPIC *pic;
96: unsigned int n;
97: uint32_t value;
1.1.1.3 root 98:
1.1 root 99: n = ((addr & 0xfff) - 0x10) >> 4;
100: if (n >= 2) {
101: value = 0;
102: } else {
103: pic = &s->pics[n];
104: switch(addr & 0xf) {
105: case 0x0:
106: value = pic->events;
107: break;
108: case 0x4:
109: value = pic->mask;
110: break;
111: case 0xc:
112: value = pic->levels;
113: break;
114: default:
115: value = 0;
116: break;
117: }
118: }
1.1.1.4 root 119: PIC_DPRINTF("readl: " TARGET_FMT_plx " %u: %08x\n", addr, n, value);
1.1 root 120: return value;
121: }
122:
1.1.1.6 root 123: static CPUWriteMemoryFunc * const pic_write[] = {
1.1 root 124: &pic_writel,
125: &pic_writel,
126: &pic_writel,
127: };
128:
1.1.1.6 root 129: static CPUReadMemoryFunc * const pic_read[] = {
1.1 root 130: &pic_readl,
131: &pic_readl,
132: &pic_readl,
133: };
134:
135:
1.1.1.3 root 136: static void heathrow_pic_set_irq(void *opaque, int num, int level)
1.1 root 137: {
138: HeathrowPICS *s = opaque;
139: HeathrowPIC *pic;
140: unsigned int irq_bit;
141:
142: #if defined(DEBUG)
143: {
144: static int last_level[64];
145: if (last_level[num] != level) {
1.1.1.4 root 146: PIC_DPRINTF("set_irq: num=0x%02x level=%d\n", num, level);
1.1 root 147: last_level[num] = level;
148: }
149: }
150: #endif
151: pic = &s->pics[1 - (num >> 5)];
152: irq_bit = 1 << (num & 0x1f);
153: if (level) {
154: pic->events |= irq_bit & ~pic->level_triggered;
155: pic->levels |= irq_bit;
156: } else {
157: pic->levels &= ~irq_bit;
158: }
159: heathrow_pic_update(s);
160: }
161:
1.1.1.4 root 162: static void heathrow_pic_save_one(QEMUFile *f, HeathrowPIC *s)
163: {
164: qemu_put_be32s(f, &s->events);
165: qemu_put_be32s(f, &s->mask);
166: qemu_put_be32s(f, &s->levels);
167: qemu_put_be32s(f, &s->level_triggered);
168: }
169:
170: static void heathrow_pic_save(QEMUFile *f, void *opaque)
171: {
172: HeathrowPICS *s = (HeathrowPICS *)opaque;
173:
174: heathrow_pic_save_one(f, &s->pics[0]);
175: heathrow_pic_save_one(f, &s->pics[1]);
176: }
177:
178: static void heathrow_pic_load_one(QEMUFile *f, HeathrowPIC *s)
179: {
180: qemu_get_be32s(f, &s->events);
181: qemu_get_be32s(f, &s->mask);
182: qemu_get_be32s(f, &s->levels);
183: qemu_get_be32s(f, &s->level_triggered);
184: }
185:
186: static int heathrow_pic_load(QEMUFile *f, void *opaque, int version_id)
187: {
188: HeathrowPICS *s = (HeathrowPICS *)opaque;
189:
190: if (version_id != 1)
191: return -EINVAL;
192:
193: heathrow_pic_load_one(f, &s->pics[0]);
194: heathrow_pic_load_one(f, &s->pics[1]);
195:
196: return 0;
197: }
198:
199: static void heathrow_pic_reset_one(HeathrowPIC *s)
200: {
201: memset(s, '\0', sizeof(HeathrowPIC));
202: }
203:
204: static void heathrow_pic_reset(void *opaque)
205: {
206: HeathrowPICS *s = opaque;
207:
208: heathrow_pic_reset_one(&s->pics[0]);
209: heathrow_pic_reset_one(&s->pics[1]);
210:
211: s->pics[0].level_triggered = 0;
212: s->pics[1].level_triggered = 0x1ff00000;
213: }
214:
1.1.1.3 root 215: qemu_irq *heathrow_pic_init(int *pmem_index,
216: int nb_cpus, qemu_irq **irqs)
1.1 root 217: {
218: HeathrowPICS *s;
1.1.1.3 root 219:
1.1 root 220: s = qemu_mallocz(sizeof(HeathrowPICS));
1.1.1.3 root 221: /* only 1 CPU */
222: s->irqs = irqs[0];
1.1.1.8 ! root 223: *pmem_index = cpu_register_io_memory(pic_read, pic_write, s,
! 224: DEVICE_LITTLE_ENDIAN);
1.1.1.3 root 225:
1.1.1.7 root 226: register_savevm(NULL, "heathrow_pic", -1, 1, heathrow_pic_save,
1.1.1.4 root 227: heathrow_pic_load, s);
228: qemu_register_reset(heathrow_pic_reset, s);
1.1.1.3 root 229: return qemu_allocate_irqs(heathrow_pic_set_irq, s, 64);
1.1 root 230: }
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