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Annotation of qemu/hw/hpet_emul.h, revision 1.1.1.1

1.1       root        1: /*
                      2:  * QEMU Emulated HPET support
                      3:  *
                      4:  * Copyright IBM, Corp. 2008
                      5:  *
                      6:  * Authors:
                      7:  *  Beth Kon   <[email protected]>
                      8:  *
                      9:  * This work is licensed under the terms of the GNU GPL, version 2.  See
                     10:  * the COPYING file in the top-level directory.
                     11:  *
                     12:  */
                     13: #ifndef QEMU_HPET_EMUL_H
                     14: #define QEMU_HPET_EMUL_H
                     15: 
                     16: #define HPET_BASE               0xfed00000
                     17: #define HPET_CLK_PERIOD         10000000ULL /* 10000000 femtoseconds == 10ns*/
                     18: 
                     19: #define FS_PER_NS 1000000
                     20: #define HPET_NUM_TIMERS 3
                     21: #define HPET_TIMER_TYPE_LEVEL 1
                     22: #define HPET_TIMER_TYPE_EDGE 0
                     23: #define HPET_TIMER_DELIVERY_APIC 0
                     24: #define HPET_TIMER_DELIVERY_FSB 1
                     25: #define HPET_TIMER_CAP_FSB_INT_DEL (1 << 15)
                     26: #define HPET_TIMER_CAP_PER_INT (1 << 4)
                     27: 
                     28: #define HPET_CFG_ENABLE 0x001
                     29: #define HPET_CFG_LEGACY 0x002
                     30: 
                     31: #define HPET_ID         0x000
                     32: #define HPET_PERIOD     0x004
                     33: #define HPET_CFG        0x010
                     34: #define HPET_STATUS     0x020
                     35: #define HPET_COUNTER    0x0f0
                     36: #define HPET_TN_CFG     0x000
                     37: #define HPET_TN_CMP     0x008
                     38: #define HPET_TN_ROUTE   0x010
                     39: #define HPET_CFG_WRITE_MASK  0x3
                     40: 
                     41: 
                     42: #define HPET_TN_ENABLE           0x004
                     43: #define HPET_TN_PERIODIC         0x008
                     44: #define HPET_TN_PERIODIC_CAP     0x010
                     45: #define HPET_TN_SIZE_CAP         0x020
                     46: #define HPET_TN_SETVAL           0x040
                     47: #define HPET_TN_32BIT            0x100
                     48: #define HPET_TN_INT_ROUTE_MASK  0x3e00
                     49: #define HPET_TN_CFG_WRITE_MASK  0x3f4e
                     50: #define HPET_TN_INT_ROUTE_SHIFT      9
                     51: #define HPET_TN_INT_ROUTE_CAP_SHIFT 32
                     52: #define HPET_TN_CFG_BITS_READONLY_OR_RESERVED 0xffff80b1U
                     53: 
                     54: struct HPETState;
                     55: typedef struct HPETTimer {  /* timers */
                     56:     uint8_t tn;             /*timer number*/
                     57:     QEMUTimer *qemu_timer;
                     58:     struct HPETState *state;
                     59:     /* Memory-mapped, software visible timer registers */
                     60:     uint64_t config;        /* configuration/cap */
                     61:     uint64_t cmp;           /* comparator */
                     62:     uint64_t fsb;           /* FSB route, not supported now */
                     63:     /* Hidden register state */
                     64:     uint64_t period;        /* Last value written to comparator */
                     65:     uint8_t wrap_flag;      /* timer pop will indicate wrap for one-shot 32-bit
                     66:                              * mode. Next pop will be actual timer expiration.
                     67:                              */
                     68: } HPETTimer;
                     69: 
                     70: typedef struct HPETState {
                     71:     uint64_t hpet_offset;
                     72:     qemu_irq *irqs;
                     73:     HPETTimer timer[HPET_NUM_TIMERS];
                     74: 
                     75:     /* Memory-mapped, software visible registers */
                     76:     uint64_t capability;        /* capabilities */
                     77:     uint64_t config;            /* configuration */
                     78:     uint64_t isr;               /* interrupt status reg */
                     79:     uint64_t hpet_counter;      /* main counter */
                     80: } HPETState;
                     81: 
                     82: #if defined TARGET_I386 || defined TARGET_X86_64
                     83: extern uint32_t hpet_in_legacy_mode(void);
                     84: extern void hpet_init(qemu_irq *irq);
                     85: #endif
                     86: 
                     87: #endif

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