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1.1 root 1: /*
2: * QEMU 8259 interrupt controller emulation
3: *
4: * Copyright (c) 2003-2004 Fabrice Bellard
5: *
6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
24: #include "vl.h"
25:
26: /* debug PIC */
27: //#define DEBUG_PIC
28:
29: //#define DEBUG_IRQ_LATENCY
30: //#define DEBUG_IRQ_COUNT
31:
32: typedef struct PicState {
33: uint8_t last_irr; /* edge detection */
34: uint8_t irr; /* interrupt request register */
35: uint8_t imr; /* interrupt mask register */
36: uint8_t isr; /* interrupt service register */
37: uint8_t priority_add; /* highest irq priority */
38: uint8_t irq_base;
39: uint8_t read_reg_select;
40: uint8_t poll;
41: uint8_t special_mask;
42: uint8_t init_state;
43: uint8_t auto_eoi;
44: uint8_t rotate_on_auto_eoi;
45: uint8_t special_fully_nested_mode;
46: uint8_t init4; /* true if 4 byte init */
47: uint8_t elcr; /* PIIX edge/trigger selection*/
48: uint8_t elcr_mask;
49: PicState2 *pics_state;
50: } PicState;
51:
52: struct PicState2 {
53: /* 0 is master pic, 1 is slave pic */
54: /* XXX: better separation between the two pics */
55: PicState pics[2];
56: IRQRequestFunc *irq_request;
57: void *irq_request_opaque;
58: /* IOAPIC callback support */
59: SetIRQFunc *alt_irq_func;
60: void *alt_irq_opaque;
61: };
62:
63: #if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)
64: static int irq_level[16];
65: #endif
66: #ifdef DEBUG_IRQ_COUNT
67: static uint64_t irq_count[16];
68: #endif
69:
70: /* set irq level. If an edge is detected, then the IRR is set to 1 */
71: static inline void pic_set_irq1(PicState *s, int irq, int level)
72: {
73: int mask;
74: mask = 1 << irq;
75: if (s->elcr & mask) {
76: /* level triggered */
77: if (level) {
78: s->irr |= mask;
79: s->last_irr |= mask;
80: } else {
81: s->irr &= ~mask;
82: s->last_irr &= ~mask;
83: }
84: } else {
85: /* edge triggered */
86: if (level) {
87: if ((s->last_irr & mask) == 0)
88: s->irr |= mask;
89: s->last_irr |= mask;
90: } else {
91: s->last_irr &= ~mask;
92: }
93: }
94: }
95:
96: /* return the highest priority found in mask (highest = smallest
97: number). Return 8 if no irq */
98: static inline int get_priority(PicState *s, int mask)
99: {
100: int priority;
101: if (mask == 0)
102: return 8;
103: priority = 0;
104: while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
105: priority++;
106: return priority;
107: }
108:
109: /* return the pic wanted interrupt. return -1 if none */
110: static int pic_get_irq(PicState *s)
111: {
112: int mask, cur_priority, priority;
113:
114: mask = s->irr & ~s->imr;
115: priority = get_priority(s, mask);
116: if (priority == 8)
117: return -1;
118: /* compute current priority. If special fully nested mode on the
119: master, the IRQ coming from the slave is not taken into account
120: for the priority computation. */
121: mask = s->isr;
122: if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
123: mask &= ~(1 << 2);
124: cur_priority = get_priority(s, mask);
125: if (priority < cur_priority) {
126: /* higher priority found: an irq should be generated */
127: return (priority + s->priority_add) & 7;
128: } else {
129: return -1;
130: }
131: }
132:
133: /* raise irq to CPU if necessary. must be called every time the active
134: irq may change */
135: /* XXX: should not export it, but it is needed for an APIC kludge */
136: void pic_update_irq(PicState2 *s)
137: {
138: int irq2, irq;
139:
140: /* first look at slave pic */
141: irq2 = pic_get_irq(&s->pics[1]);
142: if (irq2 >= 0) {
143: /* if irq request by slave pic, signal master PIC */
144: pic_set_irq1(&s->pics[0], 2, 1);
145: pic_set_irq1(&s->pics[0], 2, 0);
146: }
147: /* look at requested irq */
148: irq = pic_get_irq(&s->pics[0]);
149: if (irq >= 0) {
150: #if defined(DEBUG_PIC)
151: {
152: int i;
153: for(i = 0; i < 2; i++) {
154: printf("pic%d: imr=%x irr=%x padd=%d\n",
155: i, s->pics[i].imr, s->pics[i].irr,
156: s->pics[i].priority_add);
157:
158: }
159: }
160: printf("pic: cpu_interrupt\n");
161: #endif
162: s->irq_request(s->irq_request_opaque, 1);
163: }
1.1.1.4 ! root 164:
! 165: /* all targets should do this rather than acking the IRQ in the cpu */
! 166: #if defined(TARGET_MIPS)
! 167: else {
! 168: s->irq_request(s->irq_request_opaque, 0);
! 169: }
! 170: #endif
1.1 root 171: }
172:
173: #ifdef DEBUG_IRQ_LATENCY
174: int64_t irq_time[16];
175: #endif
176:
177: void pic_set_irq_new(void *opaque, int irq, int level)
178: {
179: PicState2 *s = opaque;
180:
181: #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
182: if (level != irq_level[irq]) {
183: #if defined(DEBUG_PIC)
184: printf("pic_set_irq: irq=%d level=%d\n", irq, level);
185: #endif
186: irq_level[irq] = level;
187: #ifdef DEBUG_IRQ_COUNT
188: if (level == 1)
189: irq_count[irq]++;
190: #endif
191: }
192: #endif
193: #ifdef DEBUG_IRQ_LATENCY
194: if (level) {
195: irq_time[irq] = qemu_get_clock(vm_clock);
196: }
197: #endif
198: pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
199: /* used for IOAPIC irqs */
200: if (s->alt_irq_func)
201: s->alt_irq_func(s->alt_irq_opaque, irq, level);
202: pic_update_irq(s);
203: }
204:
205: /* obsolete function */
206: void pic_set_irq(int irq, int level)
207: {
208: pic_set_irq_new(isa_pic, irq, level);
209: }
210:
211: /* acknowledge interrupt 'irq' */
212: static inline void pic_intack(PicState *s, int irq)
213: {
214: if (s->auto_eoi) {
215: if (s->rotate_on_auto_eoi)
216: s->priority_add = (irq + 1) & 7;
217: } else {
218: s->isr |= (1 << irq);
219: }
220: /* We don't clear a level sensitive interrupt here */
221: if (!(s->elcr & (1 << irq)))
222: s->irr &= ~(1 << irq);
223: }
224:
225: int pic_read_irq(PicState2 *s)
226: {
227: int irq, irq2, intno;
228:
229: irq = pic_get_irq(&s->pics[0]);
230: if (irq >= 0) {
231: pic_intack(&s->pics[0], irq);
232: if (irq == 2) {
233: irq2 = pic_get_irq(&s->pics[1]);
234: if (irq2 >= 0) {
235: pic_intack(&s->pics[1], irq2);
236: } else {
237: /* spurious IRQ on slave controller */
238: irq2 = 7;
239: }
240: intno = s->pics[1].irq_base + irq2;
241: irq = irq2 + 8;
242: } else {
243: intno = s->pics[0].irq_base + irq;
244: }
245: } else {
246: /* spurious IRQ on host controller */
247: irq = 7;
248: intno = s->pics[0].irq_base + irq;
249: }
250: pic_update_irq(s);
251:
252: #ifdef DEBUG_IRQ_LATENCY
253: printf("IRQ%d latency=%0.3fus\n",
254: irq,
255: (double)(qemu_get_clock(vm_clock) - irq_time[irq]) * 1000000.0 / ticks_per_sec);
256: #endif
257: #if defined(DEBUG_PIC)
258: printf("pic_interrupt: irq=%d\n", irq);
259: #endif
260: return intno;
261: }
262:
263: static void pic_reset(void *opaque)
264: {
265: PicState *s = opaque;
266:
267: s->last_irr = 0;
268: s->irr = 0;
269: s->imr = 0;
270: s->isr = 0;
271: s->priority_add = 0;
272: s->irq_base = 0;
273: s->read_reg_select = 0;
274: s->poll = 0;
275: s->special_mask = 0;
276: s->init_state = 0;
277: s->auto_eoi = 0;
278: s->rotate_on_auto_eoi = 0;
279: s->special_fully_nested_mode = 0;
280: s->init4 = 0;
1.1.1.2 root 281: /* Note: ELCR is not reset */
1.1 root 282: }
283:
284: static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
285: {
286: PicState *s = opaque;
287: int priority, cmd, irq;
288:
289: #ifdef DEBUG_PIC
290: printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
291: #endif
292: addr &= 1;
293: if (addr == 0) {
294: if (val & 0x10) {
295: /* init */
296: pic_reset(s);
297: /* deassert a pending interrupt */
298: s->pics_state->irq_request(s->pics_state->irq_request_opaque, 0);
299: s->init_state = 1;
300: s->init4 = val & 1;
301: if (val & 0x02)
302: hw_error("single mode not supported");
303: if (val & 0x08)
304: hw_error("level sensitive irq not supported");
305: } else if (val & 0x08) {
306: if (val & 0x04)
307: s->poll = 1;
308: if (val & 0x02)
309: s->read_reg_select = val & 1;
310: if (val & 0x40)
311: s->special_mask = (val >> 5) & 1;
312: } else {
313: cmd = val >> 5;
314: switch(cmd) {
315: case 0:
316: case 4:
317: s->rotate_on_auto_eoi = cmd >> 2;
318: break;
319: case 1: /* end of interrupt */
320: case 5:
321: priority = get_priority(s, s->isr);
322: if (priority != 8) {
323: irq = (priority + s->priority_add) & 7;
324: s->isr &= ~(1 << irq);
325: if (cmd == 5)
326: s->priority_add = (irq + 1) & 7;
327: pic_update_irq(s->pics_state);
328: }
329: break;
330: case 3:
331: irq = val & 7;
332: s->isr &= ~(1 << irq);
333: pic_update_irq(s->pics_state);
334: break;
335: case 6:
336: s->priority_add = (val + 1) & 7;
337: pic_update_irq(s->pics_state);
338: break;
339: case 7:
340: irq = val & 7;
341: s->isr &= ~(1 << irq);
342: s->priority_add = (irq + 1) & 7;
343: pic_update_irq(s->pics_state);
344: break;
345: default:
346: /* no operation */
347: break;
348: }
349: }
350: } else {
351: switch(s->init_state) {
352: case 0:
353: /* normal mode */
354: s->imr = val;
355: pic_update_irq(s->pics_state);
356: break;
357: case 1:
358: s->irq_base = val & 0xf8;
359: s->init_state = 2;
360: break;
361: case 2:
362: if (s->init4) {
363: s->init_state = 3;
364: } else {
365: s->init_state = 0;
366: }
367: break;
368: case 3:
369: s->special_fully_nested_mode = (val >> 4) & 1;
370: s->auto_eoi = (val >> 1) & 1;
371: s->init_state = 0;
372: break;
373: }
374: }
375: }
376:
377: static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
378: {
379: int ret;
380:
381: ret = pic_get_irq(s);
382: if (ret >= 0) {
383: if (addr1 >> 7) {
384: s->pics_state->pics[0].isr &= ~(1 << 2);
385: s->pics_state->pics[0].irr &= ~(1 << 2);
386: }
387: s->irr &= ~(1 << ret);
388: s->isr &= ~(1 << ret);
389: if (addr1 >> 7 || ret != 2)
390: pic_update_irq(s->pics_state);
391: } else {
392: ret = 0x07;
393: pic_update_irq(s->pics_state);
394: }
395:
396: return ret;
397: }
398:
399: static uint32_t pic_ioport_read(void *opaque, uint32_t addr1)
400: {
401: PicState *s = opaque;
402: unsigned int addr;
403: int ret;
404:
405: addr = addr1;
406: addr &= 1;
407: if (s->poll) {
408: ret = pic_poll_read(s, addr1);
409: s->poll = 0;
410: } else {
411: if (addr == 0) {
412: if (s->read_reg_select)
413: ret = s->isr;
414: else
415: ret = s->irr;
416: } else {
417: ret = s->imr;
418: }
419: }
420: #ifdef DEBUG_PIC
421: printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);
422: #endif
423: return ret;
424: }
425:
426: /* memory mapped interrupt status */
427: /* XXX: may be the same than pic_read_irq() */
428: uint32_t pic_intack_read(PicState2 *s)
429: {
430: int ret;
431:
432: ret = pic_poll_read(&s->pics[0], 0x00);
433: if (ret == 2)
434: ret = pic_poll_read(&s->pics[1], 0x80) + 8;
435: /* Prepare for ISR read */
436: s->pics[0].read_reg_select = 1;
437:
438: return ret;
439: }
440:
441: static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val)
442: {
443: PicState *s = opaque;
444: s->elcr = val & s->elcr_mask;
445: }
446:
447: static uint32_t elcr_ioport_read(void *opaque, uint32_t addr1)
448: {
449: PicState *s = opaque;
450: return s->elcr;
451: }
452:
453: static void pic_save(QEMUFile *f, void *opaque)
454: {
455: PicState *s = opaque;
456:
457: qemu_put_8s(f, &s->last_irr);
458: qemu_put_8s(f, &s->irr);
459: qemu_put_8s(f, &s->imr);
460: qemu_put_8s(f, &s->isr);
461: qemu_put_8s(f, &s->priority_add);
462: qemu_put_8s(f, &s->irq_base);
463: qemu_put_8s(f, &s->read_reg_select);
464: qemu_put_8s(f, &s->poll);
465: qemu_put_8s(f, &s->special_mask);
466: qemu_put_8s(f, &s->init_state);
467: qemu_put_8s(f, &s->auto_eoi);
468: qemu_put_8s(f, &s->rotate_on_auto_eoi);
469: qemu_put_8s(f, &s->special_fully_nested_mode);
470: qemu_put_8s(f, &s->init4);
471: qemu_put_8s(f, &s->elcr);
472: }
473:
474: static int pic_load(QEMUFile *f, void *opaque, int version_id)
475: {
476: PicState *s = opaque;
477:
478: if (version_id != 1)
479: return -EINVAL;
480:
481: qemu_get_8s(f, &s->last_irr);
482: qemu_get_8s(f, &s->irr);
483: qemu_get_8s(f, &s->imr);
484: qemu_get_8s(f, &s->isr);
485: qemu_get_8s(f, &s->priority_add);
486: qemu_get_8s(f, &s->irq_base);
487: qemu_get_8s(f, &s->read_reg_select);
488: qemu_get_8s(f, &s->poll);
489: qemu_get_8s(f, &s->special_mask);
490: qemu_get_8s(f, &s->init_state);
491: qemu_get_8s(f, &s->auto_eoi);
492: qemu_get_8s(f, &s->rotate_on_auto_eoi);
493: qemu_get_8s(f, &s->special_fully_nested_mode);
494: qemu_get_8s(f, &s->init4);
495: qemu_get_8s(f, &s->elcr);
496: return 0;
497: }
498:
499: /* XXX: add generic master/slave system */
500: static void pic_init1(int io_addr, int elcr_addr, PicState *s)
501: {
502: register_ioport_write(io_addr, 2, 1, pic_ioport_write, s);
503: register_ioport_read(io_addr, 2, 1, pic_ioport_read, s);
504: if (elcr_addr >= 0) {
505: register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s);
506: register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);
507: }
508: register_savevm("i8259", io_addr, 1, pic_save, pic_load, s);
509: qemu_register_reset(pic_reset, s);
510: }
511:
512: void pic_info(void)
513: {
514: int i;
515: PicState *s;
516:
517: if (!isa_pic)
518: return;
519:
520: for(i=0;i<2;i++) {
521: s = &isa_pic->pics[i];
522: term_printf("pic%d: irr=%02x imr=%02x isr=%02x hprio=%d irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
523: i, s->irr, s->imr, s->isr, s->priority_add,
524: s->irq_base, s->read_reg_select, s->elcr,
525: s->special_fully_nested_mode);
526: }
527: }
528:
529: void irq_info(void)
530: {
531: #ifndef DEBUG_IRQ_COUNT
532: term_printf("irq statistic code not compiled.\n");
533: #else
534: int i;
535: int64_t count;
536:
537: term_printf("IRQ statistics:\n");
538: for (i = 0; i < 16; i++) {
539: count = irq_count[i];
540: if (count > 0)
1.1.1.3 root 541: term_printf("%2d: %" PRId64 "\n", i, count);
1.1 root 542: }
543: #endif
544: }
545:
546: PicState2 *pic_init(IRQRequestFunc *irq_request, void *irq_request_opaque)
547: {
548: PicState2 *s;
549: s = qemu_mallocz(sizeof(PicState2));
550: if (!s)
551: return NULL;
552: pic_init1(0x20, 0x4d0, &s->pics[0]);
553: pic_init1(0xa0, 0x4d1, &s->pics[1]);
554: s->pics[0].elcr_mask = 0xf8;
555: s->pics[1].elcr_mask = 0xde;
556: s->irq_request = irq_request;
557: s->irq_request_opaque = irq_request_opaque;
558: s->pics[0].pics_state = s;
559: s->pics[1].pics_state = s;
560: return s;
561: }
562:
563: void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
564: void *alt_irq_opaque)
565: {
566: s->alt_irq_func = alt_irq_func;
567: s->alt_irq_opaque = alt_irq_opaque;
568: }
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