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1.1 root 1: /*
2: * QEMU 8259 interrupt controller emulation
1.1.1.5 root 3: *
1.1 root 4: * Copyright (c) 2003-2004 Fabrice Bellard
1.1.1.5 root 5: *
1.1 root 6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
1.1.1.5 root 24: #include "hw.h"
25: #include "pc.h"
26: #include "isa.h"
1.1.1.7 root 27: #include "monitor.h"
28: #include "qemu-timer.h"
1.1 root 29:
30: /* debug PIC */
31: //#define DEBUG_PIC
32:
33: //#define DEBUG_IRQ_LATENCY
34: //#define DEBUG_IRQ_COUNT
35:
36: typedef struct PicState {
37: uint8_t last_irr; /* edge detection */
38: uint8_t irr; /* interrupt request register */
39: uint8_t imr; /* interrupt mask register */
40: uint8_t isr; /* interrupt service register */
41: uint8_t priority_add; /* highest irq priority */
42: uint8_t irq_base;
43: uint8_t read_reg_select;
44: uint8_t poll;
45: uint8_t special_mask;
46: uint8_t init_state;
47: uint8_t auto_eoi;
48: uint8_t rotate_on_auto_eoi;
49: uint8_t special_fully_nested_mode;
50: uint8_t init4; /* true if 4 byte init */
1.1.1.5 root 51: uint8_t single_mode; /* true if slave pic is not initialized */
1.1 root 52: uint8_t elcr; /* PIIX edge/trigger selection*/
53: uint8_t elcr_mask;
54: PicState2 *pics_state;
55: } PicState;
56:
57: struct PicState2 {
58: /* 0 is master pic, 1 is slave pic */
59: /* XXX: better separation between the two pics */
60: PicState pics[2];
1.1.1.5 root 61: qemu_irq parent_irq;
1.1 root 62: void *irq_request_opaque;
63: };
64:
65: #if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)
66: static int irq_level[16];
67: #endif
68: #ifdef DEBUG_IRQ_COUNT
69: static uint64_t irq_count[16];
70: #endif
71:
72: /* set irq level. If an edge is detected, then the IRR is set to 1 */
73: static inline void pic_set_irq1(PicState *s, int irq, int level)
74: {
75: int mask;
76: mask = 1 << irq;
77: if (s->elcr & mask) {
78: /* level triggered */
79: if (level) {
80: s->irr |= mask;
81: s->last_irr |= mask;
82: } else {
83: s->irr &= ~mask;
84: s->last_irr &= ~mask;
85: }
86: } else {
87: /* edge triggered */
88: if (level) {
89: if ((s->last_irr & mask) == 0)
90: s->irr |= mask;
91: s->last_irr |= mask;
92: } else {
93: s->last_irr &= ~mask;
94: }
95: }
96: }
97:
98: /* return the highest priority found in mask (highest = smallest
99: number). Return 8 if no irq */
100: static inline int get_priority(PicState *s, int mask)
101: {
102: int priority;
103: if (mask == 0)
104: return 8;
105: priority = 0;
106: while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
107: priority++;
108: return priority;
109: }
110:
111: /* return the pic wanted interrupt. return -1 if none */
112: static int pic_get_irq(PicState *s)
113: {
114: int mask, cur_priority, priority;
115:
116: mask = s->irr & ~s->imr;
117: priority = get_priority(s, mask);
118: if (priority == 8)
119: return -1;
120: /* compute current priority. If special fully nested mode on the
121: master, the IRQ coming from the slave is not taken into account
122: for the priority computation. */
123: mask = s->isr;
1.1.1.6 root 124: if (s->special_mask)
125: mask &= ~s->imr;
1.1 root 126: if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
127: mask &= ~(1 << 2);
128: cur_priority = get_priority(s, mask);
129: if (priority < cur_priority) {
130: /* higher priority found: an irq should be generated */
131: return (priority + s->priority_add) & 7;
132: } else {
133: return -1;
134: }
135: }
136:
137: /* raise irq to CPU if necessary. must be called every time the active
138: irq may change */
139: /* XXX: should not export it, but it is needed for an APIC kludge */
140: void pic_update_irq(PicState2 *s)
141: {
142: int irq2, irq;
143:
144: /* first look at slave pic */
145: irq2 = pic_get_irq(&s->pics[1]);
146: if (irq2 >= 0) {
147: /* if irq request by slave pic, signal master PIC */
148: pic_set_irq1(&s->pics[0], 2, 1);
149: pic_set_irq1(&s->pics[0], 2, 0);
150: }
151: /* look at requested irq */
152: irq = pic_get_irq(&s->pics[0]);
153: if (irq >= 0) {
154: #if defined(DEBUG_PIC)
155: {
156: int i;
157: for(i = 0; i < 2; i++) {
1.1.1.5 root 158: printf("pic%d: imr=%x irr=%x padd=%d\n",
159: i, s->pics[i].imr, s->pics[i].irr,
1.1 root 160: s->pics[i].priority_add);
1.1.1.5 root 161:
1.1 root 162: }
163: }
164: printf("pic: cpu_interrupt\n");
165: #endif
1.1.1.5 root 166: qemu_irq_raise(s->parent_irq);
1.1 root 167: }
1.1.1.4 root 168:
169: /* all targets should do this rather than acking the IRQ in the cpu */
1.1.1.7 root 170: #if defined(TARGET_MIPS) || defined(TARGET_PPC) || defined(TARGET_ALPHA)
1.1.1.4 root 171: else {
1.1.1.5 root 172: qemu_irq_lower(s->parent_irq);
1.1.1.4 root 173: }
174: #endif
1.1 root 175: }
176:
177: #ifdef DEBUG_IRQ_LATENCY
178: int64_t irq_time[16];
179: #endif
180:
1.1.1.5 root 181: static void i8259_set_irq(void *opaque, int irq, int level)
1.1 root 182: {
183: PicState2 *s = opaque;
184:
185: #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
186: if (level != irq_level[irq]) {
187: #if defined(DEBUG_PIC)
1.1.1.5 root 188: printf("i8259_set_irq: irq=%d level=%d\n", irq, level);
1.1 root 189: #endif
190: irq_level[irq] = level;
191: #ifdef DEBUG_IRQ_COUNT
192: if (level == 1)
193: irq_count[irq]++;
194: #endif
195: }
196: #endif
197: #ifdef DEBUG_IRQ_LATENCY
198: if (level) {
199: irq_time[irq] = qemu_get_clock(vm_clock);
200: }
201: #endif
202: pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
203: pic_update_irq(s);
204: }
205:
206: /* acknowledge interrupt 'irq' */
207: static inline void pic_intack(PicState *s, int irq)
208: {
209: if (s->auto_eoi) {
210: if (s->rotate_on_auto_eoi)
211: s->priority_add = (irq + 1) & 7;
212: } else {
213: s->isr |= (1 << irq);
214: }
215: /* We don't clear a level sensitive interrupt here */
216: if (!(s->elcr & (1 << irq)))
217: s->irr &= ~(1 << irq);
218: }
219:
220: int pic_read_irq(PicState2 *s)
221: {
222: int irq, irq2, intno;
223:
224: irq = pic_get_irq(&s->pics[0]);
225: if (irq >= 0) {
226: pic_intack(&s->pics[0], irq);
227: if (irq == 2) {
228: irq2 = pic_get_irq(&s->pics[1]);
229: if (irq2 >= 0) {
230: pic_intack(&s->pics[1], irq2);
231: } else {
232: /* spurious IRQ on slave controller */
233: irq2 = 7;
234: }
235: intno = s->pics[1].irq_base + irq2;
236: irq = irq2 + 8;
237: } else {
238: intno = s->pics[0].irq_base + irq;
239: }
240: } else {
241: /* spurious IRQ on host controller */
242: irq = 7;
243: intno = s->pics[0].irq_base + irq;
244: }
245: pic_update_irq(s);
1.1.1.5 root 246:
1.1 root 247: #ifdef DEBUG_IRQ_LATENCY
1.1.1.5 root 248: printf("IRQ%d latency=%0.3fus\n",
249: irq,
1.1.1.8 ! root 250: (double)(qemu_get_clock(vm_clock) -
! 251: irq_time[irq]) * 1000000.0 / get_ticks_per_sec());
1.1 root 252: #endif
253: #if defined(DEBUG_PIC)
254: printf("pic_interrupt: irq=%d\n", irq);
255: #endif
256: return intno;
257: }
258:
259: static void pic_reset(void *opaque)
260: {
261: PicState *s = opaque;
262:
263: s->last_irr = 0;
264: s->irr = 0;
265: s->imr = 0;
266: s->isr = 0;
267: s->priority_add = 0;
268: s->irq_base = 0;
269: s->read_reg_select = 0;
270: s->poll = 0;
271: s->special_mask = 0;
272: s->init_state = 0;
273: s->auto_eoi = 0;
274: s->rotate_on_auto_eoi = 0;
275: s->special_fully_nested_mode = 0;
276: s->init4 = 0;
1.1.1.5 root 277: s->single_mode = 0;
1.1.1.2 root 278: /* Note: ELCR is not reset */
1.1 root 279: }
280:
281: static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
282: {
283: PicState *s = opaque;
284: int priority, cmd, irq;
285:
286: #ifdef DEBUG_PIC
287: printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
288: #endif
289: addr &= 1;
290: if (addr == 0) {
291: if (val & 0x10) {
292: /* init */
293: pic_reset(s);
294: /* deassert a pending interrupt */
1.1.1.5 root 295: qemu_irq_lower(s->pics_state->parent_irq);
1.1 root 296: s->init_state = 1;
297: s->init4 = val & 1;
1.1.1.5 root 298: s->single_mode = val & 2;
1.1 root 299: if (val & 0x08)
300: hw_error("level sensitive irq not supported");
301: } else if (val & 0x08) {
302: if (val & 0x04)
303: s->poll = 1;
304: if (val & 0x02)
305: s->read_reg_select = val & 1;
306: if (val & 0x40)
307: s->special_mask = (val >> 5) & 1;
308: } else {
309: cmd = val >> 5;
310: switch(cmd) {
311: case 0:
312: case 4:
313: s->rotate_on_auto_eoi = cmd >> 2;
314: break;
315: case 1: /* end of interrupt */
316: case 5:
317: priority = get_priority(s, s->isr);
318: if (priority != 8) {
319: irq = (priority + s->priority_add) & 7;
320: s->isr &= ~(1 << irq);
321: if (cmd == 5)
322: s->priority_add = (irq + 1) & 7;
323: pic_update_irq(s->pics_state);
324: }
325: break;
326: case 3:
327: irq = val & 7;
328: s->isr &= ~(1 << irq);
329: pic_update_irq(s->pics_state);
330: break;
331: case 6:
332: s->priority_add = (val + 1) & 7;
333: pic_update_irq(s->pics_state);
334: break;
335: case 7:
336: irq = val & 7;
337: s->isr &= ~(1 << irq);
338: s->priority_add = (irq + 1) & 7;
339: pic_update_irq(s->pics_state);
340: break;
341: default:
342: /* no operation */
343: break;
344: }
345: }
346: } else {
347: switch(s->init_state) {
348: case 0:
349: /* normal mode */
350: s->imr = val;
351: pic_update_irq(s->pics_state);
352: break;
353: case 1:
354: s->irq_base = val & 0xf8;
1.1.1.5 root 355: s->init_state = s->single_mode ? (s->init4 ? 3 : 0) : 2;
1.1 root 356: break;
357: case 2:
358: if (s->init4) {
359: s->init_state = 3;
360: } else {
361: s->init_state = 0;
362: }
363: break;
364: case 3:
365: s->special_fully_nested_mode = (val >> 4) & 1;
366: s->auto_eoi = (val >> 1) & 1;
367: s->init_state = 0;
368: break;
369: }
370: }
371: }
372:
373: static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
374: {
375: int ret;
376:
377: ret = pic_get_irq(s);
378: if (ret >= 0) {
379: if (addr1 >> 7) {
380: s->pics_state->pics[0].isr &= ~(1 << 2);
381: s->pics_state->pics[0].irr &= ~(1 << 2);
382: }
383: s->irr &= ~(1 << ret);
384: s->isr &= ~(1 << ret);
385: if (addr1 >> 7 || ret != 2)
386: pic_update_irq(s->pics_state);
387: } else {
388: ret = 0x07;
389: pic_update_irq(s->pics_state);
390: }
391:
392: return ret;
393: }
394:
395: static uint32_t pic_ioport_read(void *opaque, uint32_t addr1)
396: {
397: PicState *s = opaque;
398: unsigned int addr;
399: int ret;
400:
401: addr = addr1;
402: addr &= 1;
403: if (s->poll) {
404: ret = pic_poll_read(s, addr1);
405: s->poll = 0;
406: } else {
407: if (addr == 0) {
408: if (s->read_reg_select)
409: ret = s->isr;
410: else
411: ret = s->irr;
412: } else {
413: ret = s->imr;
414: }
415: }
416: #ifdef DEBUG_PIC
417: printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);
418: #endif
419: return ret;
420: }
421:
422: /* memory mapped interrupt status */
423: /* XXX: may be the same than pic_read_irq() */
424: uint32_t pic_intack_read(PicState2 *s)
425: {
426: int ret;
427:
428: ret = pic_poll_read(&s->pics[0], 0x00);
429: if (ret == 2)
430: ret = pic_poll_read(&s->pics[1], 0x80) + 8;
431: /* Prepare for ISR read */
432: s->pics[0].read_reg_select = 1;
1.1.1.5 root 433:
1.1 root 434: return ret;
435: }
436:
437: static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val)
438: {
439: PicState *s = opaque;
440: s->elcr = val & s->elcr_mask;
441: }
442:
443: static uint32_t elcr_ioport_read(void *opaque, uint32_t addr1)
444: {
445: PicState *s = opaque;
446: return s->elcr;
447: }
448:
1.1.1.8 ! root 449: static const VMStateDescription vmstate_pic = {
! 450: .name = "i8259",
! 451: .version_id = 1,
! 452: .minimum_version_id = 1,
! 453: .minimum_version_id_old = 1,
! 454: .fields = (VMStateField []) {
! 455: VMSTATE_UINT8(last_irr, PicState),
! 456: VMSTATE_UINT8(irr, PicState),
! 457: VMSTATE_UINT8(imr, PicState),
! 458: VMSTATE_UINT8(isr, PicState),
! 459: VMSTATE_UINT8(priority_add, PicState),
! 460: VMSTATE_UINT8(irq_base, PicState),
! 461: VMSTATE_UINT8(read_reg_select, PicState),
! 462: VMSTATE_UINT8(poll, PicState),
! 463: VMSTATE_UINT8(special_mask, PicState),
! 464: VMSTATE_UINT8(init_state, PicState),
! 465: VMSTATE_UINT8(auto_eoi, PicState),
! 466: VMSTATE_UINT8(rotate_on_auto_eoi, PicState),
! 467: VMSTATE_UINT8(special_fully_nested_mode, PicState),
! 468: VMSTATE_UINT8(init4, PicState),
! 469: VMSTATE_UINT8(single_mode, PicState),
! 470: VMSTATE_UINT8(elcr, PicState),
! 471: VMSTATE_END_OF_LIST()
! 472: }
! 473: };
1.1 root 474:
475: /* XXX: add generic master/slave system */
476: static void pic_init1(int io_addr, int elcr_addr, PicState *s)
477: {
478: register_ioport_write(io_addr, 2, 1, pic_ioport_write, s);
479: register_ioport_read(io_addr, 2, 1, pic_ioport_read, s);
480: if (elcr_addr >= 0) {
481: register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s);
482: register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);
483: }
1.1.1.8 ! root 484: vmstate_register(io_addr, &vmstate_pic, s);
1.1 root 485: qemu_register_reset(pic_reset, s);
486: }
487:
1.1.1.7 root 488: void pic_info(Monitor *mon)
1.1 root 489: {
490: int i;
491: PicState *s;
1.1.1.5 root 492:
1.1 root 493: if (!isa_pic)
494: return;
495:
496: for(i=0;i<2;i++) {
497: s = &isa_pic->pics[i];
1.1.1.7 root 498: monitor_printf(mon, "pic%d: irr=%02x imr=%02x isr=%02x hprio=%d "
499: "irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
500: i, s->irr, s->imr, s->isr, s->priority_add,
501: s->irq_base, s->read_reg_select, s->elcr,
502: s->special_fully_nested_mode);
1.1 root 503: }
504: }
505:
1.1.1.7 root 506: void irq_info(Monitor *mon)
1.1 root 507: {
508: #ifndef DEBUG_IRQ_COUNT
1.1.1.7 root 509: monitor_printf(mon, "irq statistic code not compiled.\n");
1.1 root 510: #else
511: int i;
512: int64_t count;
513:
1.1.1.7 root 514: monitor_printf(mon, "IRQ statistics:\n");
1.1 root 515: for (i = 0; i < 16; i++) {
516: count = irq_count[i];
517: if (count > 0)
1.1.1.7 root 518: monitor_printf(mon, "%2d: %" PRId64 "\n", i, count);
1.1 root 519: }
520: #endif
521: }
522:
1.1.1.5 root 523: qemu_irq *i8259_init(qemu_irq parent_irq)
1.1 root 524: {
525: PicState2 *s;
1.1.1.5 root 526:
1.1 root 527: s = qemu_mallocz(sizeof(PicState2));
528: pic_init1(0x20, 0x4d0, &s->pics[0]);
529: pic_init1(0xa0, 0x4d1, &s->pics[1]);
530: s->pics[0].elcr_mask = 0xf8;
531: s->pics[1].elcr_mask = 0xde;
1.1.1.5 root 532: s->parent_irq = parent_irq;
1.1 root 533: s->pics[0].pics_state = s;
534: s->pics[1].pics_state = s;
1.1.1.5 root 535: isa_pic = s;
536: return qemu_allocate_irqs(i8259_set_irq, s, 16);
1.1 root 537: }
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