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1.1 root 1: /*
2: * QEMU ICH Emulation
3: *
4: * Copyright (c) 2010 Sebastian Herbszt <[email protected]>
5: * Copyright (c) 2010 Alexander Graf <[email protected]>
6: *
7: * This library is free software; you can redistribute it and/or
8: * modify it under the terms of the GNU Lesser General Public
9: * License as published by the Free Software Foundation; either
10: * version 2 of the License, or (at your option) any later version.
11: *
12: * This library is distributed in the hope that it will be useful,
13: * but WITHOUT ANY WARRANTY; without even the implied warranty of
14: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15: * Lesser General Public License for more details.
16: *
17: * You should have received a copy of the GNU Lesser General Public
18: * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19: *
20: *
21: * lspci dump of a ICH-9 real device
22: *
23: * 00:1f.2 SATA controller [0106]: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller [8086:2922] (rev 02) (prog-if 01 [AHCI 1.0])
24: * Subsystem: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller [8086:2922]
25: * Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+
26: * Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
27: * Latency: 0
28: * Interrupt: pin B routed to IRQ 222
29: * Region 0: I/O ports at d000 [size=8]
30: * Region 1: I/O ports at cc00 [size=4]
31: * Region 2: I/O ports at c880 [size=8]
32: * Region 3: I/O ports at c800 [size=4]
33: * Region 4: I/O ports at c480 [size=32]
34: * Region 5: Memory at febf9000 (32-bit, non-prefetchable) [size=2K]
35: * Capabilities: [80] Message Signalled Interrupts: Mask- 64bit- Count=1/16 Enable+
36: * Address: fee0f00c Data: 41d9
37: * Capabilities: [70] Power Management version 3
38: * Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold-)
39: * Status: D0 PME-Enable- DSel=0 DScale=0 PME-
40: * Capabilities: [a8] SATA HBA <?>
41: * Capabilities: [b0] Vendor Specific Information <?>
42: * Kernel driver in use: ahci
43: * Kernel modules: ahci
44: * 00: 86 80 22 29 07 04 b0 02 02 01 06 01 00 00 00 00
45: * 10: 01 d0 00 00 01 cc 00 00 81 c8 00 00 01 c8 00 00
46: * 20: 81 c4 00 00 00 90 bf fe 00 00 00 00 86 80 22 29
47: * 30: 00 00 00 00 80 00 00 00 00 00 00 00 0f 02 00 00
48: * 40: 00 80 00 80 00 00 00 00 00 00 00 00 00 00 00 00
49: * 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: * 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
51: * 70: 01 a8 03 40 08 00 00 00 00 00 00 00 00 00 00 00
52: * 80: 05 70 09 00 0c f0 e0 fe d9 41 00 00 00 00 00 00
53: * 90: 40 00 0f 82 93 01 00 00 00 00 00 00 00 00 00 00
54: * a0: ac 00 00 00 0a 00 12 00 12 b0 10 00 48 00 00 00
55: * b0: 09 00 06 20 00 00 00 00 00 00 00 00 00 00 00 00
56: * c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
57: * d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
58: * e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
59: * f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00
60: *
61: */
62:
63: #include <hw/hw.h>
64: #include <hw/msi.h>
65: #include <hw/pc.h>
66: #include <hw/pci.h>
67: #include <hw/isa.h>
68: #include "block.h"
69: #include "block_int.h"
70: #include "sysemu.h"
71: #include "dma.h"
72:
73: #include <hw/ide/pci.h>
74: #include <hw/ide/ahci.h>
75:
76: static int pci_ich9_ahci_init(PCIDevice *dev)
77: {
78: struct AHCIPCIState *d;
79: d = DO_UPCAST(struct AHCIPCIState, card, dev);
80:
81: pci_config_set_vendor_id(d->card.config, PCI_VENDOR_ID_INTEL);
82: pci_config_set_device_id(d->card.config, PCI_DEVICE_ID_INTEL_82801IR);
83:
84: pci_config_set_class(d->card.config, PCI_CLASS_STORAGE_SATA);
85: pci_config_set_revision(d->card.config, 0x02);
86: pci_config_set_prog_interface(d->card.config, AHCI_PROGMODE_MAJOR_REV_1);
87:
88: d->card.config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */
89: d->card.config[PCI_LATENCY_TIMER] = 0x00; /* Latency timer */
90: pci_config_set_interrupt_pin(d->card.config, 1);
91:
92: /* XXX Software should program this register */
93: d->card.config[0x90] = 1 << 6; /* Address Map Register - AHCI mode */
94:
95: qemu_register_reset(ahci_reset, d);
96:
97: /* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */
98: pci_register_bar(&d->card, 5, 0x1000, PCI_BASE_ADDRESS_SPACE_MEMORY,
99: ahci_pci_map);
100:
101: msi_init(dev, 0x50, 1, true, false);
102:
103: ahci_init(&d->ahci, &dev->qdev, 6);
104: d->ahci.irq = d->card.irq[0];
105:
106: return 0;
107: }
108:
109: static int pci_ich9_uninit(PCIDevice *dev)
110: {
111: struct AHCIPCIState *d;
112: d = DO_UPCAST(struct AHCIPCIState, card, dev);
113:
114: if (msi_enabled(dev)) {
115: msi_uninit(dev);
116: }
117:
118: qemu_unregister_reset(ahci_reset, d);
119: ahci_uninit(&d->ahci);
120:
121: return 0;
122: }
123:
124: static void pci_ich9_write_config(PCIDevice *pci, uint32_t addr,
125: uint32_t val, int len)
126: {
127: pci_default_write_config(pci, addr, val, len);
128: msi_write_config(pci, addr, val, len);
129: }
130:
131: static PCIDeviceInfo ich_ahci_info[] = {
132: {
133: .qdev.name = "ich9-ahci",
134: .qdev.alias = "ahci",
135: .qdev.size = sizeof(AHCIPCIState),
136: .init = pci_ich9_ahci_init,
137: .exit = pci_ich9_uninit,
138: .config_write = pci_ich9_write_config,
139: },{
140: /* end of list */
141: }
142: };
143:
144: static void ich_ahci_register(void)
145: {
146: pci_qdev_register_many(ich_ahci_info);
147: }
148: device_init(ich_ahci_register);
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