![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to piix.c CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [Qemu by Fabrice Bellard] / qemu / hw / ide|
Return to piix.c CVS log | Up to [Qemu by Fabrice Bellard] / qemu / hw / ide |
1.1 root 1: /*
2: * QEMU IDE Emulation: PCI PIIX3/4 support.
3: *
4: * Copyright (c) 2003 Fabrice Bellard
5: * Copyright (c) 2006 Openedhand Ltd.
6: *
7: * Permission is hereby granted, free of charge, to any person obtaining a copy
8: * of this software and associated documentation files (the "Software"), to deal
9: * in the Software without restriction, including without limitation the rights
10: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11: * copies of the Software, and to permit persons to whom the Software is
12: * furnished to do so, subject to the following conditions:
13: *
14: * The above copyright notice and this permission notice shall be included in
15: * all copies or substantial portions of the Software.
16: *
17: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23: * THE SOFTWARE.
24: */
25: #include <hw/hw.h>
26: #include <hw/pc.h>
27: #include <hw/pci.h>
28: #include <hw/isa.h>
29: #include "block.h"
30: #include "block_int.h"
31: #include "sysemu.h"
32: #include "dma.h"
33:
34: #include <hw/ide/pci.h>
35:
36: static uint32_t bmdma_readb(void *opaque, uint32_t addr)
37: {
38: BMDMAState *bm = opaque;
39: uint32_t val;
40:
41: switch(addr & 3) {
42: case 0:
43: val = bm->cmd;
44: break;
45: case 2:
46: val = bm->status;
47: break;
48: default:
49: val = 0xff;
50: break;
51: }
52: #ifdef DEBUG_IDE
53: printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val);
54: #endif
55: return val;
56: }
57:
58: static void bmdma_writeb(void *opaque, uint32_t addr, uint32_t val)
59: {
60: BMDMAState *bm = opaque;
61: #ifdef DEBUG_IDE
62: printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val);
63: #endif
64: switch(addr & 3) {
65: case 2:
66: bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
67: break;
68: }
69: }
70:
71: static void bmdma_map(PCIDevice *pci_dev, int region_num,
72: pcibus_t addr, pcibus_t size, int type)
73: {
74: PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, pci_dev);
75: int i;
76:
77: for(i = 0;i < 2; i++) {
78: BMDMAState *bm = &d->bmdma[i];
79: d->bus[i].bmdma = bm;
80: bm->bus = d->bus+i;
81: qemu_add_vm_change_state_handler(ide_dma_restart_cb, bm);
82:
83: register_ioport_write(addr, 1, 1, bmdma_cmd_writeb, bm);
84:
85: register_ioport_write(addr + 1, 3, 1, bmdma_writeb, bm);
86: register_ioport_read(addr, 4, 1, bmdma_readb, bm);
87:
88: register_ioport_write(addr + 4, 4, 1, bmdma_addr_writeb, bm);
89: register_ioport_read(addr + 4, 4, 1, bmdma_addr_readb, bm);
90: register_ioport_write(addr + 4, 4, 2, bmdma_addr_writew, bm);
91: register_ioport_read(addr + 4, 4, 2, bmdma_addr_readw, bm);
92: register_ioport_write(addr + 4, 4, 4, bmdma_addr_writel, bm);
93: register_ioport_read(addr + 4, 4, 4, bmdma_addr_readl, bm);
94: addr += 8;
95: }
96: }
97:
98: static void piix3_reset(void *opaque)
99: {
100: PCIIDEState *d = opaque;
101: uint8_t *pci_conf = d->dev.config;
102: int i;
103:
104: for (i = 0; i < 2; i++) {
105: ide_bus_reset(&d->bus[i]);
106: ide_dma_reset(&d->bmdma[i]);
107: }
108:
1.1.1.3 ! root 109: /* TODO: this is the default. do not override. */
! 110: pci_conf[PCI_COMMAND] = 0x00;
! 111: /* TODO: this is the default. do not override. */
! 112: pci_conf[PCI_COMMAND + 1] = 0x00;
! 113: /* TODO: use pci_set_word */
! 114: pci_conf[PCI_STATUS] = PCI_STATUS_FAST_BACK;
! 115: pci_conf[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_MEDIUM >> 8;
1.1 root 116: pci_conf[0x20] = 0x01; /* BMIBA: 20-23h */
117: }
118:
119: static int pci_piix_ide_initfn(PCIIDEState *d)
120: {
121: uint8_t *pci_conf = d->dev.config;
122:
1.1.1.3 ! root 123: pci_conf[PCI_CLASS_PROG] = 0x80; // legacy ATA mode
1.1 root 124: pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
125:
126: qemu_register_reset(piix3_reset, d);
127:
128: pci_register_bar(&d->dev, 4, 0x10, PCI_BASE_ADDRESS_SPACE_IO, bmdma_map);
129:
1.1.1.3 ! root 130: vmstate_register(&d->dev.qdev, 0, &vmstate_ide_pci, d);
1.1 root 131:
132: ide_bus_new(&d->bus[0], &d->dev.qdev);
133: ide_bus_new(&d->bus[1], &d->dev.qdev);
134: ide_init_ioport(&d->bus[0], 0x1f0, 0x3f6);
135: ide_init_ioport(&d->bus[1], 0x170, 0x376);
136:
1.1.1.3 ! root 137: ide_init2(&d->bus[0], isa_reserve_irq(14));
! 138: ide_init2(&d->bus[1], isa_reserve_irq(15));
1.1 root 139: return 0;
140: }
141:
142: static int pci_piix3_ide_initfn(PCIDevice *dev)
143: {
144: PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
145:
146: pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL);
147: pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82371SB_1);
148: return pci_piix_ide_initfn(d);
149: }
150:
151: static int pci_piix4_ide_initfn(PCIDevice *dev)
152: {
153: PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
154:
155: pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL);
156: pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82371AB);
157: return pci_piix_ide_initfn(d);
158: }
159:
160: /* hd_table must contain 4 block drivers */
161: /* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
1.1.1.3 ! root 162: PCIDevice *pci_piix3_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
1.1 root 163: {
164: PCIDevice *dev;
165:
166: dev = pci_create_simple(bus, devfn, "piix3-ide");
167: pci_ide_create_devs(dev, hd_table);
1.1.1.3 ! root 168: return dev;
1.1 root 169: }
170:
171: /* hd_table must contain 4 block drivers */
172: /* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */
1.1.1.3 ! root 173: PCIDevice *pci_piix4_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
1.1 root 174: {
175: PCIDevice *dev;
176:
177: dev = pci_create_simple(bus, devfn, "piix4-ide");
178: pci_ide_create_devs(dev, hd_table);
1.1.1.3 ! root 179: return dev;
1.1 root 180: }
181:
182: static PCIDeviceInfo piix_ide_info[] = {
183: {
184: .qdev.name = "piix3-ide",
185: .qdev.size = sizeof(PCIIDEState),
186: .qdev.no_user = 1,
187: .init = pci_piix3_ide_initfn,
188: },{
189: .qdev.name = "piix4-ide",
190: .qdev.size = sizeof(PCIIDEState),
191: .qdev.no_user = 1,
192: .init = pci_piix4_ide_initfn,
193: },{
194: /* end of list */
195: }
196: };
197:
198: static void piix_ide_register(void)
199: {
200: pci_qdev_register_many(piix_ide_info);
201: }
202: device_init(piix_ide_register);
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.