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1.1 root 1: /*
2: * QEMU IDE Emulation: PCI PIIX3/4 support.
3: *
4: * Copyright (c) 2003 Fabrice Bellard
5: * Copyright (c) 2006 Openedhand Ltd.
6: *
7: * Permission is hereby granted, free of charge, to any person obtaining a copy
8: * of this software and associated documentation files (the "Software"), to deal
9: * in the Software without restriction, including without limitation the rights
10: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11: * copies of the Software, and to permit persons to whom the Software is
12: * furnished to do so, subject to the following conditions:
13: *
14: * The above copyright notice and this permission notice shall be included in
15: * all copies or substantial portions of the Software.
16: *
17: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23: * THE SOFTWARE.
24: */
25: #include <hw/hw.h>
26: #include <hw/pc.h>
27: #include <hw/pci.h>
28: #include <hw/isa.h>
29: #include "block.h"
30: #include "sysemu.h"
31: #include "dma.h"
32:
33: #include <hw/ide/pci.h>
34:
1.1.1.7 root 35: static uint64_t bmdma_read(void *opaque, target_phys_addr_t addr, unsigned size)
1.1 root 36: {
37: BMDMAState *bm = opaque;
38: uint32_t val;
39:
1.1.1.7 root 40: if (size != 1) {
41: return ((uint64_t)1 << (size * 8)) - 1;
42: }
43:
1.1 root 44: switch(addr & 3) {
45: case 0:
46: val = bm->cmd;
47: break;
48: case 2:
49: val = bm->status;
50: break;
51: default:
52: val = 0xff;
53: break;
54: }
55: #ifdef DEBUG_IDE
1.1.1.8 ! root 56: printf("bmdma: readb 0x%02x : 0x%02x\n", (uint8_t)addr, val);
1.1 root 57: #endif
58: return val;
59: }
60:
1.1.1.7 root 61: static void bmdma_write(void *opaque, target_phys_addr_t addr,
62: uint64_t val, unsigned size)
1.1 root 63: {
64: BMDMAState *bm = opaque;
1.1.1.7 root 65:
66: if (size != 1) {
67: return;
68: }
69:
1.1 root 70: #ifdef DEBUG_IDE
1.1.1.8 ! root 71: printf("bmdma: writeb 0x%02x : 0x%02x\n", (uint8_t)addr, (uint8_t)val);
1.1 root 72: #endif
73: switch(addr & 3) {
1.1.1.7 root 74: case 0:
75: return bmdma_cmd_writeb(bm, val);
1.1 root 76: case 2:
77: bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
78: break;
79: }
80: }
81:
1.1.1.8 ! root 82: static const MemoryRegionOps piix_bmdma_ops = {
1.1.1.7 root 83: .read = bmdma_read,
84: .write = bmdma_write,
85: };
86:
87: static void bmdma_setup_bar(PCIIDEState *d)
1.1 root 88: {
89: int i;
90:
1.1.1.7 root 91: memory_region_init(&d->bmdma_bar, "piix-bmdma-container", 16);
1.1 root 92: for(i = 0;i < 2; i++) {
93: BMDMAState *bm = &d->bmdma[i];
94:
1.1.1.7 root 95: memory_region_init_io(&bm->extra_io, &piix_bmdma_ops, bm,
96: "piix-bmdma", 4);
97: memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
98: memory_region_init_io(&bm->addr_ioport, &bmdma_addr_ioport_ops, bm,
99: "bmdma", 4);
100: memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
1.1 root 101: }
102: }
103:
104: static void piix3_reset(void *opaque)
105: {
106: PCIIDEState *d = opaque;
107: uint8_t *pci_conf = d->dev.config;
108: int i;
109:
110: for (i = 0; i < 2; i++) {
111: ide_bus_reset(&d->bus[i]);
112: }
113:
1.1.1.3 root 114: /* TODO: this is the default. do not override. */
115: pci_conf[PCI_COMMAND] = 0x00;
116: /* TODO: this is the default. do not override. */
117: pci_conf[PCI_COMMAND + 1] = 0x00;
118: /* TODO: use pci_set_word */
119: pci_conf[PCI_STATUS] = PCI_STATUS_FAST_BACK;
120: pci_conf[PCI_STATUS + 1] = PCI_STATUS_DEVSEL_MEDIUM >> 8;
1.1 root 121: pci_conf[0x20] = 0x01; /* BMIBA: 20-23h */
122: }
123:
1.1.1.4 root 124: static void pci_piix_init_ports(PCIIDEState *d) {
1.1.1.7 root 125: static const struct {
1.1.1.4 root 126: int iobase;
127: int iobase2;
128: int isairq;
129: } port_info[] = {
130: {0x1f0, 0x3f6, 14},
131: {0x170, 0x376, 15},
132: };
1.1.1.7 root 133: int i;
1.1.1.4 root 134:
135: for (i = 0; i < 2; i++) {
136: ide_bus_new(&d->bus[i], &d->dev.qdev, i);
1.1.1.7 root 137: ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase,
138: port_info[i].iobase2);
1.1.1.8 ! root 139: ide_init2(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq));
1.1.1.4 root 140:
1.1.1.7 root 141: bmdma_init(&d->bus[i], &d->bmdma[i], d);
1.1.1.4 root 142: d->bmdma[i].bus = &d->bus[i];
143: qemu_add_vm_change_state_handler(d->bus[i].dma->ops->restart_cb,
144: &d->bmdma[i].dma);
145: }
146: }
147:
1.1.1.6 root 148: static int pci_piix_ide_initfn(PCIDevice *dev)
1.1 root 149: {
1.1.1.6 root 150: PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
1.1 root 151: uint8_t *pci_conf = d->dev.config;
152:
1.1.1.3 root 153: pci_conf[PCI_CLASS_PROG] = 0x80; // legacy ATA mode
1.1 root 154:
155: qemu_register_reset(piix3_reset, d);
156:
1.1.1.7 root 157: bmdma_setup_bar(d);
158: pci_register_bar(&d->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
1.1 root 159:
1.1.1.3 root 160: vmstate_register(&d->dev.qdev, 0, &vmstate_ide_pci, d);
1.1 root 161:
1.1.1.4 root 162: pci_piix_init_ports(d);
1.1 root 163:
164: return 0;
165: }
166:
1.1.1.7 root 167: static int pci_piix3_xen_ide_unplug(DeviceState *dev)
168: {
169: PCIDevice *pci_dev;
170: PCIIDEState *pci_ide;
171: DriveInfo *di;
172: int i = 0;
173:
174: pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
175: pci_ide = DO_UPCAST(PCIIDEState, dev, pci_dev);
176:
177: for (; i < 3; i++) {
178: di = drive_get_by_index(IF_IDE, i);
179: if (di != NULL && !di->media_cd) {
180: DeviceState *ds = bdrv_get_attached_dev(di->bdrv);
181: if (ds) {
182: bdrv_detach_dev(di->bdrv, ds);
183: }
184: bdrv_close(di->bdrv);
185: pci_ide->bus[di->bus].ifs[di->unit].bs = NULL;
186: drive_put_ref(di);
187: }
188: }
189: qdev_reset_all(&(pci_ide->dev.qdev));
190: return 0;
191: }
192:
193: PCIDevice *pci_piix3_xen_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
194: {
195: PCIDevice *dev;
196:
197: dev = pci_create_simple(bus, devfn, "piix3-ide-xen");
198: pci_ide_create_devs(dev, hd_table);
199: return dev;
200: }
201:
202: static int pci_piix_ide_exitfn(PCIDevice *dev)
203: {
204: PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);
205: unsigned i;
206:
207: for (i = 0; i < 2; ++i) {
208: memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
209: memory_region_destroy(&d->bmdma[i].extra_io);
210: memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
211: memory_region_destroy(&d->bmdma[i].addr_ioport);
212: }
213: memory_region_destroy(&d->bmdma_bar);
214:
215: return 0;
216: }
217:
1.1 root 218: /* hd_table must contain 4 block drivers */
219: /* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
1.1.1.3 root 220: PCIDevice *pci_piix3_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
1.1 root 221: {
222: PCIDevice *dev;
223:
224: dev = pci_create_simple(bus, devfn, "piix3-ide");
225: pci_ide_create_devs(dev, hd_table);
1.1.1.3 root 226: return dev;
1.1 root 227: }
228:
229: /* hd_table must contain 4 block drivers */
230: /* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */
1.1.1.3 root 231: PCIDevice *pci_piix4_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
1.1 root 232: {
233: PCIDevice *dev;
234:
235: dev = pci_create_simple(bus, devfn, "piix4-ide");
236: pci_ide_create_devs(dev, hd_table);
1.1.1.3 root 237: return dev;
1.1 root 238: }
239:
1.1.1.8 ! root 240: static void piix3_ide_class_init(ObjectClass *klass, void *data)
! 241: {
! 242: DeviceClass *dc = DEVICE_CLASS(klass);
! 243: PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
! 244:
! 245: k->no_hotplug = 1;
! 246: k->init = pci_piix_ide_initfn;
! 247: k->exit = pci_piix_ide_exitfn;
! 248: k->vendor_id = PCI_VENDOR_ID_INTEL;
! 249: k->device_id = PCI_DEVICE_ID_INTEL_82371SB_1;
! 250: k->class_id = PCI_CLASS_STORAGE_IDE;
! 251: dc->no_user = 1;
! 252: }
! 253:
! 254: static TypeInfo piix3_ide_info = {
! 255: .name = "piix3-ide",
! 256: .parent = TYPE_PCI_DEVICE,
! 257: .instance_size = sizeof(PCIIDEState),
! 258: .class_init = piix3_ide_class_init,
! 259: };
! 260:
! 261: static void piix3_ide_xen_class_init(ObjectClass *klass, void *data)
! 262: {
! 263: DeviceClass *dc = DEVICE_CLASS(klass);
! 264: PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
! 265:
! 266: k->init = pci_piix_ide_initfn;
! 267: k->vendor_id = PCI_VENDOR_ID_INTEL;
! 268: k->device_id = PCI_DEVICE_ID_INTEL_82371SB_1;
! 269: k->class_id = PCI_CLASS_STORAGE_IDE;
! 270: dc->no_user = 1;
! 271: dc->unplug = pci_piix3_xen_ide_unplug;
! 272: }
! 273:
! 274: static TypeInfo piix3_ide_xen_info = {
! 275: .name = "piix3-ide-xen",
! 276: .parent = TYPE_PCI_DEVICE,
! 277: .instance_size = sizeof(PCIIDEState),
! 278: .class_init = piix3_ide_xen_class_init,
! 279: };
! 280:
! 281: static void piix4_ide_class_init(ObjectClass *klass, void *data)
! 282: {
! 283: DeviceClass *dc = DEVICE_CLASS(klass);
! 284: PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
! 285:
! 286: k->no_hotplug = 1;
! 287: k->init = pci_piix_ide_initfn;
! 288: k->exit = pci_piix_ide_exitfn;
! 289: k->vendor_id = PCI_VENDOR_ID_INTEL;
! 290: k->device_id = PCI_DEVICE_ID_INTEL_82371AB;
! 291: k->class_id = PCI_CLASS_STORAGE_IDE;
! 292: dc->no_user = 1;
! 293: }
! 294:
! 295: static TypeInfo piix4_ide_info = {
! 296: .name = "piix4-ide",
! 297: .parent = TYPE_PCI_DEVICE,
! 298: .instance_size = sizeof(PCIIDEState),
! 299: .class_init = piix4_ide_class_init,
1.1 root 300: };
301:
1.1.1.8 ! root 302: static void piix_ide_register_types(void)
1.1 root 303: {
1.1.1.8 ! root 304: type_register_static(&piix3_ide_info);
! 305: type_register_static(&piix3_ide_xen_info);
! 306: type_register_static(&piix4_ide_info);
1.1 root 307: }
1.1.1.8 ! root 308:
! 309: type_init(piix_ide_register_types)
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