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1.1.1.4 root 1: /*
1.1 root 2: * ARM Integrator CP System emulation.
3: *
1.1.1.4 root 4: * Copyright (c) 2005-2007 CodeSourcery.
1.1 root 5: * Written by Paul Brook
6: *
1.1.1.10 root 7: * This code is licensed under the GPL
1.1 root 8: */
9:
1.1.1.6 root 10: #include "sysbus.h"
1.1.1.4 root 11: #include "devices.h"
12: #include "boards.h"
13: #include "arm-misc.h"
14: #include "net.h"
1.1.1.11 root 15: #include "exec-memory.h"
16: #include "sysemu.h"
1.1 root 17:
18: typedef struct {
1.1.1.6 root 19: SysBusDevice busdev;
1.1.1.12! root 20: MemoryRegion iomem;
1.1.1.6 root 21: uint32_t memsz;
1.1.1.11 root 22: MemoryRegion flash;
1.1 root 23: uint32_t cm_osc;
24: uint32_t cm_ctrl;
25: uint32_t cm_lock;
26: uint32_t cm_auxosc;
27: uint32_t cm_sdram;
28: uint32_t cm_init;
29: uint32_t cm_flags;
30: uint32_t cm_nvflags;
31: uint32_t int_level;
32: uint32_t irq_enabled;
33: uint32_t fiq_enabled;
34: } integratorcm_state;
35:
36: static uint8_t integrator_spd[128] = {
37: 128, 8, 4, 11, 9, 1, 64, 0, 2, 0xa0, 0xa0, 0, 0, 8, 0, 1,
38: 0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
39: };
40:
1.1.1.12! root 41: static uint64_t integratorcm_read(void *opaque, target_phys_addr_t offset,
! 42: unsigned size)
1.1 root 43: {
44: integratorcm_state *s = (integratorcm_state *)opaque;
45: if (offset >= 0x100 && offset < 0x200) {
46: /* CM_SPD */
47: if (offset >= 0x180)
48: return 0;
49: return integrator_spd[offset >> 2];
50: }
51: switch (offset >> 2) {
52: case 0: /* CM_ID */
53: return 0x411a3001;
54: case 1: /* CM_PROC */
55: return 0;
56: case 2: /* CM_OSC */
57: return s->cm_osc;
58: case 3: /* CM_CTRL */
59: return s->cm_ctrl;
60: case 4: /* CM_STAT */
61: return 0x00100000;
62: case 5: /* CM_LOCK */
63: if (s->cm_lock == 0xa05f) {
64: return 0x1a05f;
65: } else {
66: return s->cm_lock;
67: }
68: case 6: /* CM_LMBUSCNT */
69: /* ??? High frequency timer. */
1.1.1.6 root 70: hw_error("integratorcm_read: CM_LMBUSCNT");
1.1 root 71: case 7: /* CM_AUXOSC */
72: return s->cm_auxosc;
73: case 8: /* CM_SDRAM */
74: return s->cm_sdram;
75: case 9: /* CM_INIT */
76: return s->cm_init;
77: case 10: /* CM_REFCT */
78: /* ??? High frequency timer. */
1.1.1.6 root 79: hw_error("integratorcm_read: CM_REFCT");
1.1 root 80: case 12: /* CM_FLAGS */
81: return s->cm_flags;
82: case 14: /* CM_NVFLAGS */
83: return s->cm_nvflags;
84: case 16: /* CM_IRQ_STAT */
85: return s->int_level & s->irq_enabled;
86: case 17: /* CM_IRQ_RSTAT */
87: return s->int_level;
88: case 18: /* CM_IRQ_ENSET */
89: return s->irq_enabled;
90: case 20: /* CM_SOFT_INTSET */
91: return s->int_level & 1;
92: case 24: /* CM_FIQ_STAT */
93: return s->int_level & s->fiq_enabled;
94: case 25: /* CM_FIQ_RSTAT */
95: return s->int_level;
96: case 26: /* CM_FIQ_ENSET */
97: return s->fiq_enabled;
98: case 32: /* CM_VOLTAGE_CTL0 */
99: case 33: /* CM_VOLTAGE_CTL1 */
100: case 34: /* CM_VOLTAGE_CTL2 */
101: case 35: /* CM_VOLTAGE_CTL3 */
102: /* ??? Voltage control unimplemented. */
103: return 0;
104: default:
1.1.1.6 root 105: hw_error("integratorcm_read: Unimplemented offset 0x%x\n",
106: (int)offset);
1.1 root 107: return 0;
108: }
109: }
110:
1.1.1.12! root 111: static void integratorcm_do_remap(integratorcm_state *s)
1.1 root 112: {
1.1.1.12! root 113: /* Sync memory region state with CM_CTRL REMAP bit:
! 114: * bit 0 => flash at address 0; bit 1 => RAM
! 115: */
! 116: memory_region_set_enabled(&s->flash, !(s->cm_ctrl & 4));
1.1 root 117: }
118:
119: static void integratorcm_set_ctrl(integratorcm_state *s, uint32_t value)
120: {
121: if (value & 8) {
1.1.1.11 root 122: qemu_system_reset_request();
1.1 root 123: }
1.1.1.11 root 124: if ((s->cm_ctrl ^ value) & 1) {
125: /* (value & 1) != 0 means the green "MISC LED" is lit.
126: * We don't have any nice place to display LEDs. printf is a bad
127: * idea because Linux uses the LED as a heartbeat and the output
128: * will swamp anything else on the terminal.
129: */
1.1 root 130: }
1.1.1.11 root 131: /* Note that the RESET bit [3] always reads as zero */
132: s->cm_ctrl = (s->cm_ctrl & ~5) | (value & 5);
1.1.1.12! root 133: integratorcm_do_remap(s);
1.1 root 134: }
135:
136: static void integratorcm_update(integratorcm_state *s)
137: {
138: /* ??? The CPU irq/fiq is raised when either the core module or base PIC
139: are active. */
140: if (s->int_level & (s->irq_enabled | s->fiq_enabled))
1.1.1.6 root 141: hw_error("Core module interrupt\n");
1.1 root 142: }
143:
144: static void integratorcm_write(void *opaque, target_phys_addr_t offset,
1.1.1.12! root 145: uint64_t value, unsigned size)
1.1 root 146: {
147: integratorcm_state *s = (integratorcm_state *)opaque;
148: switch (offset >> 2) {
149: case 2: /* CM_OSC */
150: if (s->cm_lock == 0xa05f)
151: s->cm_osc = value;
152: break;
153: case 3: /* CM_CTRL */
154: integratorcm_set_ctrl(s, value);
155: break;
156: case 5: /* CM_LOCK */
157: s->cm_lock = value & 0xffff;
158: break;
159: case 7: /* CM_AUXOSC */
160: if (s->cm_lock == 0xa05f)
161: s->cm_auxosc = value;
162: break;
163: case 8: /* CM_SDRAM */
164: s->cm_sdram = value;
165: break;
166: case 9: /* CM_INIT */
167: /* ??? This can change the memory bus frequency. */
168: s->cm_init = value;
169: break;
170: case 12: /* CM_FLAGSS */
171: s->cm_flags |= value;
172: break;
173: case 13: /* CM_FLAGSC */
174: s->cm_flags &= ~value;
175: break;
176: case 14: /* CM_NVFLAGSS */
177: s->cm_nvflags |= value;
178: break;
179: case 15: /* CM_NVFLAGSS */
180: s->cm_nvflags &= ~value;
181: break;
182: case 18: /* CM_IRQ_ENSET */
183: s->irq_enabled |= value;
184: integratorcm_update(s);
185: break;
186: case 19: /* CM_IRQ_ENCLR */
187: s->irq_enabled &= ~value;
188: integratorcm_update(s);
189: break;
190: case 20: /* CM_SOFT_INTSET */
191: s->int_level |= (value & 1);
192: integratorcm_update(s);
193: break;
194: case 21: /* CM_SOFT_INTCLR */
195: s->int_level &= ~(value & 1);
196: integratorcm_update(s);
197: break;
198: case 26: /* CM_FIQ_ENSET */
199: s->fiq_enabled |= value;
200: integratorcm_update(s);
201: break;
202: case 27: /* CM_FIQ_ENCLR */
203: s->fiq_enabled &= ~value;
204: integratorcm_update(s);
205: break;
206: case 32: /* CM_VOLTAGE_CTL0 */
207: case 33: /* CM_VOLTAGE_CTL1 */
208: case 34: /* CM_VOLTAGE_CTL2 */
209: case 35: /* CM_VOLTAGE_CTL3 */
210: /* ??? Voltage control unimplemented. */
211: break;
212: default:
1.1.1.6 root 213: hw_error("integratorcm_write: Unimplemented offset 0x%x\n",
214: (int)offset);
1.1 root 215: break;
216: }
217: }
218:
219: /* Integrator/CM control registers. */
220:
1.1.1.12! root 221: static const MemoryRegionOps integratorcm_ops = {
! 222: .read = integratorcm_read,
! 223: .write = integratorcm_write,
! 224: .endianness = DEVICE_NATIVE_ENDIAN,
1.1 root 225: };
226:
1.1.1.7 root 227: static int integratorcm_init(SysBusDevice *dev)
1.1 root 228: {
1.1.1.6 root 229: integratorcm_state *s = FROM_SYSBUS(integratorcm_state, dev);
1.1 root 230:
231: s->cm_osc = 0x01000048;
232: /* ??? What should the high bits of this value be? */
233: s->cm_auxosc = 0x0007feff;
234: s->cm_sdram = 0x00011122;
1.1.1.6 root 235: if (s->memsz >= 256) {
1.1 root 236: integrator_spd[31] = 64;
237: s->cm_sdram |= 0x10;
1.1.1.6 root 238: } else if (s->memsz >= 128) {
1.1 root 239: integrator_spd[31] = 32;
240: s->cm_sdram |= 0x0c;
1.1.1.6 root 241: } else if (s->memsz >= 64) {
1.1 root 242: integrator_spd[31] = 16;
243: s->cm_sdram |= 0x08;
1.1.1.6 root 244: } else if (s->memsz >= 32) {
1.1 root 245: integrator_spd[31] = 4;
246: s->cm_sdram |= 0x04;
247: } else {
248: integrator_spd[31] = 2;
249: }
250: memcpy(integrator_spd + 73, "QEMU-MEMORY", 11);
251: s->cm_init = 0x00000112;
1.1.1.12! root 252: memory_region_init_ram(&s->flash, "integrator.flash", 0x100000);
! 253: vmstate_register_ram_global(&s->flash);
1.1 root 254:
1.1.1.12! root 255: memory_region_init_io(&s->iomem, &integratorcm_ops, s,
! 256: "integratorcm", 0x00800000);
! 257: sysbus_init_mmio(dev, &s->iomem);
! 258:
! 259: integratorcm_do_remap(s);
1.1 root 260: /* ??? Save/restore. */
1.1.1.7 root 261: return 0;
1.1 root 262: }
263:
264: /* Integrator/CP hardware emulation. */
265: /* Primary interrupt controller. */
266:
267: typedef struct icp_pic_state
268: {
1.1.1.6 root 269: SysBusDevice busdev;
1.1.1.12! root 270: MemoryRegion iomem;
1.1 root 271: uint32_t level;
272: uint32_t irq_enabled;
273: uint32_t fiq_enabled;
1.1.1.4 root 274: qemu_irq parent_irq;
275: qemu_irq parent_fiq;
1.1 root 276: } icp_pic_state;
277:
278: static void icp_pic_update(icp_pic_state *s)
279: {
1.1.1.2 root 280: uint32_t flags;
1.1 root 281:
1.1.1.4 root 282: flags = (s->level & s->irq_enabled);
283: qemu_set_irq(s->parent_irq, flags != 0);
284: flags = (s->level & s->fiq_enabled);
285: qemu_set_irq(s->parent_fiq, flags != 0);
1.1 root 286: }
287:
1.1.1.2 root 288: static void icp_pic_set_irq(void *opaque, int irq, int level)
1.1 root 289: {
290: icp_pic_state *s = (icp_pic_state *)opaque;
291: if (level)
292: s->level |= 1 << irq;
293: else
294: s->level &= ~(1 << irq);
295: icp_pic_update(s);
296: }
297:
1.1.1.12! root 298: static uint64_t icp_pic_read(void *opaque, target_phys_addr_t offset,
! 299: unsigned size)
1.1 root 300: {
301: icp_pic_state *s = (icp_pic_state *)opaque;
302:
303: switch (offset >> 2) {
304: case 0: /* IRQ_STATUS */
305: return s->level & s->irq_enabled;
306: case 1: /* IRQ_RAWSTAT */
307: return s->level;
308: case 2: /* IRQ_ENABLESET */
309: return s->irq_enabled;
310: case 4: /* INT_SOFTSET */
311: return s->level & 1;
312: case 8: /* FRQ_STATUS */
313: return s->level & s->fiq_enabled;
314: case 9: /* FRQ_RAWSTAT */
315: return s->level;
316: case 10: /* FRQ_ENABLESET */
317: return s->fiq_enabled;
318: case 3: /* IRQ_ENABLECLR */
319: case 5: /* INT_SOFTCLR */
320: case 11: /* FRQ_ENABLECLR */
321: default:
1.1.1.3 root 322: printf ("icp_pic_read: Bad register offset 0x%x\n", (int)offset);
1.1 root 323: return 0;
324: }
325: }
326:
327: static void icp_pic_write(void *opaque, target_phys_addr_t offset,
1.1.1.12! root 328: uint64_t value, unsigned size)
1.1 root 329: {
330: icp_pic_state *s = (icp_pic_state *)opaque;
331:
332: switch (offset >> 2) {
333: case 2: /* IRQ_ENABLESET */
334: s->irq_enabled |= value;
335: break;
336: case 3: /* IRQ_ENABLECLR */
337: s->irq_enabled &= ~value;
338: break;
339: case 4: /* INT_SOFTSET */
340: if (value & 1)
1.1.1.4 root 341: icp_pic_set_irq(s, 0, 1);
1.1 root 342: break;
343: case 5: /* INT_SOFTCLR */
344: if (value & 1)
1.1.1.4 root 345: icp_pic_set_irq(s, 0, 0);
1.1 root 346: break;
347: case 10: /* FRQ_ENABLESET */
348: s->fiq_enabled |= value;
349: break;
350: case 11: /* FRQ_ENABLECLR */
351: s->fiq_enabled &= ~value;
352: break;
353: case 0: /* IRQ_STATUS */
354: case 1: /* IRQ_RAWSTAT */
355: case 8: /* FRQ_STATUS */
356: case 9: /* FRQ_RAWSTAT */
357: default:
1.1.1.3 root 358: printf ("icp_pic_write: Bad register offset 0x%x\n", (int)offset);
1.1 root 359: return;
360: }
361: icp_pic_update(s);
362: }
363:
1.1.1.12! root 364: static const MemoryRegionOps icp_pic_ops = {
! 365: .read = icp_pic_read,
! 366: .write = icp_pic_write,
! 367: .endianness = DEVICE_NATIVE_ENDIAN,
1.1 root 368: };
369:
1.1.1.7 root 370: static int icp_pic_init(SysBusDevice *dev)
1.1 root 371: {
1.1.1.6 root 372: icp_pic_state *s = FROM_SYSBUS(icp_pic_state, dev);
1.1 root 373:
1.1.1.6 root 374: qdev_init_gpio_in(&dev->qdev, icp_pic_set_irq, 32);
375: sysbus_init_irq(dev, &s->parent_irq);
376: sysbus_init_irq(dev, &s->parent_fiq);
1.1.1.12! root 377: memory_region_init_io(&s->iomem, &icp_pic_ops, s, "icp-pic", 0x00800000);
! 378: sysbus_init_mmio(dev, &s->iomem);
1.1.1.7 root 379: return 0;
1.1 root 380: }
381:
382: /* CP control registers. */
1.1.1.12! root 383:
! 384: static uint64_t icp_control_read(void *opaque, target_phys_addr_t offset,
! 385: unsigned size)
1.1 root 386: {
387: switch (offset >> 2) {
388: case 0: /* CP_IDFIELD */
389: return 0x41034003;
390: case 1: /* CP_FLASHPROG */
391: return 0;
392: case 2: /* CP_INTREG */
393: return 0;
394: case 3: /* CP_DECODE */
395: return 0x11;
396: default:
1.1.1.6 root 397: hw_error("icp_control_read: Bad offset %x\n", (int)offset);
1.1 root 398: return 0;
399: }
400: }
401:
402: static void icp_control_write(void *opaque, target_phys_addr_t offset,
1.1.1.12! root 403: uint64_t value, unsigned size)
1.1 root 404: {
405: switch (offset >> 2) {
406: case 1: /* CP_FLASHPROG */
407: case 2: /* CP_INTREG */
408: case 3: /* CP_DECODE */
409: /* Nothing interesting implemented yet. */
410: break;
411: default:
1.1.1.6 root 412: hw_error("icp_control_write: Bad offset %x\n", (int)offset);
1.1 root 413: }
414: }
415:
1.1.1.12! root 416: static const MemoryRegionOps icp_control_ops = {
! 417: .read = icp_control_read,
! 418: .write = icp_control_write,
! 419: .endianness = DEVICE_NATIVE_ENDIAN,
1.1 root 420: };
421:
1.1.1.12! root 422: static void icp_control_init(target_phys_addr_t base)
1.1 root 423: {
1.1.1.12! root 424: MemoryRegion *io;
1.1 root 425:
1.1.1.12! root 426: io = (MemoryRegion *)g_malloc0(sizeof(MemoryRegion));
! 427: memory_region_init_io(io, &icp_control_ops, NULL,
! 428: "control", 0x00800000);
! 429: memory_region_add_subregion(get_system_memory(), base, io);
1.1 root 430: /* ??? Save/restore. */
431: }
432:
433:
434: /* Board init. */
435:
1.1.1.5 root 436: static struct arm_boot_info integrator_binfo = {
437: .loader_start = 0x0,
438: .board_id = 0x113,
439: };
440:
1.1.1.6 root 441: static void integratorcp_init(ram_addr_t ram_size,
1.1.1.5 root 442: const char *boot_device,
1.1 root 443: const char *kernel_filename, const char *kernel_cmdline,
1.1.1.4 root 444: const char *initrd_filename, const char *cpu_model)
1.1 root 445: {
1.1.1.12! root 446: CPUARMState *env;
1.1.1.11 root 447: MemoryRegion *address_space_mem = get_system_memory();
448: MemoryRegion *ram = g_new(MemoryRegion, 1);
449: MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
1.1.1.6 root 450: qemu_irq pic[32];
1.1.1.4 root 451: qemu_irq *cpu_pic;
1.1.1.6 root 452: DeviceState *dev;
453: int i;
1.1.1.4 root 454:
455: if (!cpu_model)
456: cpu_model = "arm926";
457: env = cpu_init(cpu_model);
458: if (!env) {
459: fprintf(stderr, "Unable to find CPU definition\n");
460: exit(1);
461: }
1.1.1.12! root 462: memory_region_init_ram(ram, "integrator.ram", ram_size);
! 463: vmstate_register_ram_global(ram);
1.1 root 464: /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */
1.1.1.5 root 465: /* ??? RAM should repeat to fill physical memory space. */
1.1 root 466: /* SDRAM at address zero*/
1.1.1.11 root 467: memory_region_add_subregion(address_space_mem, 0, ram);
1.1 root 468: /* And again at address 0x80000000 */
1.1.1.11 root 469: memory_region_init_alias(ram_alias, "ram.alias", ram, 0, ram_size);
470: memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias);
1.1 root 471:
1.1.1.6 root 472: dev = qdev_create(NULL, "integrator_core");
473: qdev_prop_set_uint32(dev, "memsz", ram_size >> 20);
1.1.1.7 root 474: qdev_init_nofail(dev);
1.1.1.6 root 475: sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000);
476:
1.1.1.2 root 477: cpu_pic = arm_pic_init_cpu(env);
1.1.1.6 root 478: dev = sysbus_create_varargs("integrator_pic", 0x14000000,
479: cpu_pic[ARM_PIC_CPU_IRQ],
480: cpu_pic[ARM_PIC_CPU_FIQ], NULL);
481: for (i = 0; i < 32; i++) {
482: pic[i] = qdev_get_gpio_in(dev, i);
483: }
484: sysbus_create_simple("integrator_pic", 0xca000000, pic[26]);
485: sysbus_create_varargs("integrator_pit", 0x13000000,
486: pic[5], pic[6], pic[7], NULL);
487: sysbus_create_simple("pl031", 0x15000000, pic[8]);
488: sysbus_create_simple("pl011", 0x16000000, pic[1]);
489: sysbus_create_simple("pl011", 0x17000000, pic[2]);
1.1 root 490: icp_control_init(0xcb000000);
1.1.1.6 root 491: sysbus_create_simple("pl050_keyboard", 0x18000000, pic[3]);
492: sysbus_create_simple("pl050_mouse", 0x19000000, pic[4]);
493: sysbus_create_varargs("pl181", 0x1c000000, pic[23], pic[24], NULL);
1.1.1.5 root 494: if (nd_table[0].vlan)
495: smc91c111_init(&nd_table[0], 0xc8000000, pic[27]);
1.1.1.6 root 496:
497: sysbus_create_simple("pl110", 0xc0000000, pic[22]);
1.1.1.5 root 498:
499: integrator_binfo.ram_size = ram_size;
500: integrator_binfo.kernel_filename = kernel_filename;
501: integrator_binfo.kernel_cmdline = kernel_cmdline;
502: integrator_binfo.initrd_filename = initrd_filename;
503: arm_load_kernel(env, &integrator_binfo);
1.1.1.2 root 504: }
505:
1.1.1.6 root 506: static QEMUMachine integratorcp_machine = {
1.1.1.5 root 507: .name = "integratorcp",
508: .desc = "ARM Integrator/CP (ARM926EJ-S)",
509: .init = integratorcp_init,
1.1.1.6 root 510: .is_default = 1,
1.1 root 511: };
1.1.1.6 root 512:
513: static void integratorcp_machine_init(void)
514: {
515: qemu_register_machine(&integratorcp_machine);
516: }
517:
518: machine_init(integratorcp_machine_init);
519:
1.1.1.12! root 520: static Property core_properties[] = {
! 521: DEFINE_PROP_UINT32("memsz", integratorcm_state, memsz, 0),
! 522: DEFINE_PROP_END_OF_LIST(),
! 523: };
! 524:
! 525: static void core_class_init(ObjectClass *klass, void *data)
! 526: {
! 527: DeviceClass *dc = DEVICE_CLASS(klass);
! 528: SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
! 529:
! 530: k->init = integratorcm_init;
! 531: dc->props = core_properties;
! 532: }
! 533:
! 534: static TypeInfo core_info = {
! 535: .name = "integrator_core",
! 536: .parent = TYPE_SYS_BUS_DEVICE,
! 537: .instance_size = sizeof(integratorcm_state),
! 538: .class_init = core_class_init,
! 539: };
! 540:
! 541: static void icp_pic_class_init(ObjectClass *klass, void *data)
! 542: {
! 543: SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
! 544:
! 545: sdc->init = icp_pic_init;
! 546: }
! 547:
! 548: static TypeInfo icp_pic_info = {
! 549: .name = "integrator_pic",
! 550: .parent = TYPE_SYS_BUS_DEVICE,
! 551: .instance_size = sizeof(icp_pic_state),
! 552: .class_init = icp_pic_class_init,
1.1.1.6 root 553: };
554:
1.1.1.12! root 555: static void integratorcp_register_types(void)
1.1.1.6 root 556: {
1.1.1.12! root 557: type_register_static(&icp_pic_info);
! 558: type_register_static(&core_info);
1.1.1.6 root 559: }
560:
1.1.1.12! root 561: type_init(integratorcp_register_types)
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