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1.1.1.4 root 1: /*
1.1 root 2: * ARM Integrator CP System emulation.
3: *
1.1.1.4 root 4: * Copyright (c) 2005-2007 CodeSourcery.
1.1 root 5: * Written by Paul Brook
6: *
7: * This code is licenced under the GPL
8: */
9:
1.1.1.6 root 10: #include "sysbus.h"
1.1.1.4 root 11: #include "primecell.h"
12: #include "devices.h"
13: #include "sysemu.h"
14: #include "boards.h"
15: #include "arm-misc.h"
16: #include "net.h"
1.1 root 17:
18: typedef struct {
1.1.1.6 root 19: SysBusDevice busdev;
20: uint32_t memsz;
1.1 root 21: uint32_t flash_offset;
22: uint32_t cm_osc;
23: uint32_t cm_ctrl;
24: uint32_t cm_lock;
25: uint32_t cm_auxosc;
26: uint32_t cm_sdram;
27: uint32_t cm_init;
28: uint32_t cm_flags;
29: uint32_t cm_nvflags;
30: uint32_t int_level;
31: uint32_t irq_enabled;
32: uint32_t fiq_enabled;
33: } integratorcm_state;
34:
35: static uint8_t integrator_spd[128] = {
36: 128, 8, 4, 11, 9, 1, 64, 0, 2, 0xa0, 0xa0, 0, 0, 8, 0, 1,
37: 0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
38: };
39:
40: static uint32_t integratorcm_read(void *opaque, target_phys_addr_t offset)
41: {
42: integratorcm_state *s = (integratorcm_state *)opaque;
43: if (offset >= 0x100 && offset < 0x200) {
44: /* CM_SPD */
45: if (offset >= 0x180)
46: return 0;
47: return integrator_spd[offset >> 2];
48: }
49: switch (offset >> 2) {
50: case 0: /* CM_ID */
51: return 0x411a3001;
52: case 1: /* CM_PROC */
53: return 0;
54: case 2: /* CM_OSC */
55: return s->cm_osc;
56: case 3: /* CM_CTRL */
57: return s->cm_ctrl;
58: case 4: /* CM_STAT */
59: return 0x00100000;
60: case 5: /* CM_LOCK */
61: if (s->cm_lock == 0xa05f) {
62: return 0x1a05f;
63: } else {
64: return s->cm_lock;
65: }
66: case 6: /* CM_LMBUSCNT */
67: /* ??? High frequency timer. */
1.1.1.6 root 68: hw_error("integratorcm_read: CM_LMBUSCNT");
1.1 root 69: case 7: /* CM_AUXOSC */
70: return s->cm_auxosc;
71: case 8: /* CM_SDRAM */
72: return s->cm_sdram;
73: case 9: /* CM_INIT */
74: return s->cm_init;
75: case 10: /* CM_REFCT */
76: /* ??? High frequency timer. */
1.1.1.6 root 77: hw_error("integratorcm_read: CM_REFCT");
1.1 root 78: case 12: /* CM_FLAGS */
79: return s->cm_flags;
80: case 14: /* CM_NVFLAGS */
81: return s->cm_nvflags;
82: case 16: /* CM_IRQ_STAT */
83: return s->int_level & s->irq_enabled;
84: case 17: /* CM_IRQ_RSTAT */
85: return s->int_level;
86: case 18: /* CM_IRQ_ENSET */
87: return s->irq_enabled;
88: case 20: /* CM_SOFT_INTSET */
89: return s->int_level & 1;
90: case 24: /* CM_FIQ_STAT */
91: return s->int_level & s->fiq_enabled;
92: case 25: /* CM_FIQ_RSTAT */
93: return s->int_level;
94: case 26: /* CM_FIQ_ENSET */
95: return s->fiq_enabled;
96: case 32: /* CM_VOLTAGE_CTL0 */
97: case 33: /* CM_VOLTAGE_CTL1 */
98: case 34: /* CM_VOLTAGE_CTL2 */
99: case 35: /* CM_VOLTAGE_CTL3 */
100: /* ??? Voltage control unimplemented. */
101: return 0;
102: default:
1.1.1.6 root 103: hw_error("integratorcm_read: Unimplemented offset 0x%x\n",
104: (int)offset);
1.1 root 105: return 0;
106: }
107: }
108:
109: static void integratorcm_do_remap(integratorcm_state *s, int flash)
110: {
111: if (flash) {
112: cpu_register_physical_memory(0, 0x100000, IO_MEM_RAM);
113: } else {
114: cpu_register_physical_memory(0, 0x100000, s->flash_offset | IO_MEM_RAM);
115: }
116: //??? tlb_flush (cpu_single_env, 1);
117: }
118:
119: static void integratorcm_set_ctrl(integratorcm_state *s, uint32_t value)
120: {
121: if (value & 8) {
1.1.1.6 root 122: hw_error("Board reset\n");
1.1 root 123: }
124: if ((s->cm_init ^ value) & 4) {
125: integratorcm_do_remap(s, (value & 4) == 0);
126: }
127: if ((s->cm_init ^ value) & 1) {
128: printf("Green LED %s\n", (value & 1) ? "on" : "off");
129: }
130: s->cm_init = (s->cm_init & ~ 5) | (value ^ 5);
131: }
132:
133: static void integratorcm_update(integratorcm_state *s)
134: {
135: /* ??? The CPU irq/fiq is raised when either the core module or base PIC
136: are active. */
137: if (s->int_level & (s->irq_enabled | s->fiq_enabled))
1.1.1.6 root 138: hw_error("Core module interrupt\n");
1.1 root 139: }
140:
141: static void integratorcm_write(void *opaque, target_phys_addr_t offset,
142: uint32_t value)
143: {
144: integratorcm_state *s = (integratorcm_state *)opaque;
145: switch (offset >> 2) {
146: case 2: /* CM_OSC */
147: if (s->cm_lock == 0xa05f)
148: s->cm_osc = value;
149: break;
150: case 3: /* CM_CTRL */
151: integratorcm_set_ctrl(s, value);
152: break;
153: case 5: /* CM_LOCK */
154: s->cm_lock = value & 0xffff;
155: break;
156: case 7: /* CM_AUXOSC */
157: if (s->cm_lock == 0xa05f)
158: s->cm_auxosc = value;
159: break;
160: case 8: /* CM_SDRAM */
161: s->cm_sdram = value;
162: break;
163: case 9: /* CM_INIT */
164: /* ??? This can change the memory bus frequency. */
165: s->cm_init = value;
166: break;
167: case 12: /* CM_FLAGSS */
168: s->cm_flags |= value;
169: break;
170: case 13: /* CM_FLAGSC */
171: s->cm_flags &= ~value;
172: break;
173: case 14: /* CM_NVFLAGSS */
174: s->cm_nvflags |= value;
175: break;
176: case 15: /* CM_NVFLAGSS */
177: s->cm_nvflags &= ~value;
178: break;
179: case 18: /* CM_IRQ_ENSET */
180: s->irq_enabled |= value;
181: integratorcm_update(s);
182: break;
183: case 19: /* CM_IRQ_ENCLR */
184: s->irq_enabled &= ~value;
185: integratorcm_update(s);
186: break;
187: case 20: /* CM_SOFT_INTSET */
188: s->int_level |= (value & 1);
189: integratorcm_update(s);
190: break;
191: case 21: /* CM_SOFT_INTCLR */
192: s->int_level &= ~(value & 1);
193: integratorcm_update(s);
194: break;
195: case 26: /* CM_FIQ_ENSET */
196: s->fiq_enabled |= value;
197: integratorcm_update(s);
198: break;
199: case 27: /* CM_FIQ_ENCLR */
200: s->fiq_enabled &= ~value;
201: integratorcm_update(s);
202: break;
203: case 32: /* CM_VOLTAGE_CTL0 */
204: case 33: /* CM_VOLTAGE_CTL1 */
205: case 34: /* CM_VOLTAGE_CTL2 */
206: case 35: /* CM_VOLTAGE_CTL3 */
207: /* ??? Voltage control unimplemented. */
208: break;
209: default:
1.1.1.6 root 210: hw_error("integratorcm_write: Unimplemented offset 0x%x\n",
211: (int)offset);
1.1 root 212: break;
213: }
214: }
215:
216: /* Integrator/CM control registers. */
217:
1.1.1.7 root 218: static CPUReadMemoryFunc * const integratorcm_readfn[] = {
1.1 root 219: integratorcm_read,
220: integratorcm_read,
221: integratorcm_read
222: };
223:
1.1.1.7 root 224: static CPUWriteMemoryFunc * const integratorcm_writefn[] = {
1.1 root 225: integratorcm_write,
226: integratorcm_write,
227: integratorcm_write
228: };
229:
1.1.1.7 root 230: static int integratorcm_init(SysBusDevice *dev)
1.1 root 231: {
232: int iomemtype;
1.1.1.6 root 233: integratorcm_state *s = FROM_SYSBUS(integratorcm_state, dev);
1.1 root 234:
235: s->cm_osc = 0x01000048;
236: /* ??? What should the high bits of this value be? */
237: s->cm_auxosc = 0x0007feff;
238: s->cm_sdram = 0x00011122;
1.1.1.6 root 239: if (s->memsz >= 256) {
1.1 root 240: integrator_spd[31] = 64;
241: s->cm_sdram |= 0x10;
1.1.1.6 root 242: } else if (s->memsz >= 128) {
1.1 root 243: integrator_spd[31] = 32;
244: s->cm_sdram |= 0x0c;
1.1.1.6 root 245: } else if (s->memsz >= 64) {
1.1 root 246: integrator_spd[31] = 16;
247: s->cm_sdram |= 0x08;
1.1.1.6 root 248: } else if (s->memsz >= 32) {
1.1 root 249: integrator_spd[31] = 4;
250: s->cm_sdram |= 0x04;
251: } else {
252: integrator_spd[31] = 2;
253: }
254: memcpy(integrator_spd + 73, "QEMU-MEMORY", 11);
255: s->cm_init = 0x00000112;
1.1.1.8 root 256: s->flash_offset = qemu_ram_alloc(NULL, "integrator.flash", 0x100000);
1.1 root 257:
1.1.1.6 root 258: iomemtype = cpu_register_io_memory(integratorcm_readfn,
1.1.1.9 ! root 259: integratorcm_writefn, s,
! 260: DEVICE_NATIVE_ENDIAN);
1.1.1.6 root 261: sysbus_init_mmio(dev, 0x00800000, iomemtype);
1.1 root 262: integratorcm_do_remap(s, 1);
263: /* ??? Save/restore. */
1.1.1.7 root 264: return 0;
1.1 root 265: }
266:
267: /* Integrator/CP hardware emulation. */
268: /* Primary interrupt controller. */
269:
270: typedef struct icp_pic_state
271: {
1.1.1.6 root 272: SysBusDevice busdev;
1.1 root 273: uint32_t level;
274: uint32_t irq_enabled;
275: uint32_t fiq_enabled;
1.1.1.4 root 276: qemu_irq parent_irq;
277: qemu_irq parent_fiq;
1.1 root 278: } icp_pic_state;
279:
280: static void icp_pic_update(icp_pic_state *s)
281: {
1.1.1.2 root 282: uint32_t flags;
1.1 root 283:
1.1.1.4 root 284: flags = (s->level & s->irq_enabled);
285: qemu_set_irq(s->parent_irq, flags != 0);
286: flags = (s->level & s->fiq_enabled);
287: qemu_set_irq(s->parent_fiq, flags != 0);
1.1 root 288: }
289:
1.1.1.2 root 290: static void icp_pic_set_irq(void *opaque, int irq, int level)
1.1 root 291: {
292: icp_pic_state *s = (icp_pic_state *)opaque;
293: if (level)
294: s->level |= 1 << irq;
295: else
296: s->level &= ~(1 << irq);
297: icp_pic_update(s);
298: }
299:
300: static uint32_t icp_pic_read(void *opaque, target_phys_addr_t offset)
301: {
302: icp_pic_state *s = (icp_pic_state *)opaque;
303:
304: switch (offset >> 2) {
305: case 0: /* IRQ_STATUS */
306: return s->level & s->irq_enabled;
307: case 1: /* IRQ_RAWSTAT */
308: return s->level;
309: case 2: /* IRQ_ENABLESET */
310: return s->irq_enabled;
311: case 4: /* INT_SOFTSET */
312: return s->level & 1;
313: case 8: /* FRQ_STATUS */
314: return s->level & s->fiq_enabled;
315: case 9: /* FRQ_RAWSTAT */
316: return s->level;
317: case 10: /* FRQ_ENABLESET */
318: return s->fiq_enabled;
319: case 3: /* IRQ_ENABLECLR */
320: case 5: /* INT_SOFTCLR */
321: case 11: /* FRQ_ENABLECLR */
322: default:
1.1.1.3 root 323: printf ("icp_pic_read: Bad register offset 0x%x\n", (int)offset);
1.1 root 324: return 0;
325: }
326: }
327:
328: static void icp_pic_write(void *opaque, target_phys_addr_t offset,
329: uint32_t value)
330: {
331: icp_pic_state *s = (icp_pic_state *)opaque;
332:
333: switch (offset >> 2) {
334: case 2: /* IRQ_ENABLESET */
335: s->irq_enabled |= value;
336: break;
337: case 3: /* IRQ_ENABLECLR */
338: s->irq_enabled &= ~value;
339: break;
340: case 4: /* INT_SOFTSET */
341: if (value & 1)
1.1.1.4 root 342: icp_pic_set_irq(s, 0, 1);
1.1 root 343: break;
344: case 5: /* INT_SOFTCLR */
345: if (value & 1)
1.1.1.4 root 346: icp_pic_set_irq(s, 0, 0);
1.1 root 347: break;
348: case 10: /* FRQ_ENABLESET */
349: s->fiq_enabled |= value;
350: break;
351: case 11: /* FRQ_ENABLECLR */
352: s->fiq_enabled &= ~value;
353: break;
354: case 0: /* IRQ_STATUS */
355: case 1: /* IRQ_RAWSTAT */
356: case 8: /* FRQ_STATUS */
357: case 9: /* FRQ_RAWSTAT */
358: default:
1.1.1.3 root 359: printf ("icp_pic_write: Bad register offset 0x%x\n", (int)offset);
1.1 root 360: return;
361: }
362: icp_pic_update(s);
363: }
364:
1.1.1.7 root 365: static CPUReadMemoryFunc * const icp_pic_readfn[] = {
1.1 root 366: icp_pic_read,
367: icp_pic_read,
368: icp_pic_read
369: };
370:
1.1.1.7 root 371: static CPUWriteMemoryFunc * const icp_pic_writefn[] = {
1.1 root 372: icp_pic_write,
373: icp_pic_write,
374: icp_pic_write
375: };
376:
1.1.1.7 root 377: static int icp_pic_init(SysBusDevice *dev)
1.1 root 378: {
1.1.1.6 root 379: icp_pic_state *s = FROM_SYSBUS(icp_pic_state, dev);
1.1 root 380: int iomemtype;
381:
1.1.1.6 root 382: qdev_init_gpio_in(&dev->qdev, icp_pic_set_irq, 32);
383: sysbus_init_irq(dev, &s->parent_irq);
384: sysbus_init_irq(dev, &s->parent_fiq);
385: iomemtype = cpu_register_io_memory(icp_pic_readfn,
1.1.1.9 ! root 386: icp_pic_writefn, s,
! 387: DEVICE_NATIVE_ENDIAN);
1.1.1.6 root 388: sysbus_init_mmio(dev, 0x00800000, iomemtype);
1.1.1.7 root 389: return 0;
1.1 root 390: }
391:
392: /* CP control registers. */
393: static uint32_t icp_control_read(void *opaque, target_phys_addr_t offset)
394: {
395: switch (offset >> 2) {
396: case 0: /* CP_IDFIELD */
397: return 0x41034003;
398: case 1: /* CP_FLASHPROG */
399: return 0;
400: case 2: /* CP_INTREG */
401: return 0;
402: case 3: /* CP_DECODE */
403: return 0x11;
404: default:
1.1.1.6 root 405: hw_error("icp_control_read: Bad offset %x\n", (int)offset);
1.1 root 406: return 0;
407: }
408: }
409:
410: static void icp_control_write(void *opaque, target_phys_addr_t offset,
411: uint32_t value)
412: {
413: switch (offset >> 2) {
414: case 1: /* CP_FLASHPROG */
415: case 2: /* CP_INTREG */
416: case 3: /* CP_DECODE */
417: /* Nothing interesting implemented yet. */
418: break;
419: default:
1.1.1.6 root 420: hw_error("icp_control_write: Bad offset %x\n", (int)offset);
1.1 root 421: }
422: }
1.1.1.7 root 423: static CPUReadMemoryFunc * const icp_control_readfn[] = {
1.1 root 424: icp_control_read,
425: icp_control_read,
426: icp_control_read
427: };
428:
1.1.1.7 root 429: static CPUWriteMemoryFunc * const icp_control_writefn[] = {
1.1 root 430: icp_control_write,
431: icp_control_write,
432: icp_control_write
433: };
434:
435: static void icp_control_init(uint32_t base)
436: {
437: int iomemtype;
438:
1.1.1.6 root 439: iomemtype = cpu_register_io_memory(icp_control_readfn,
1.1.1.9 ! root 440: icp_control_writefn, NULL,
! 441: DEVICE_NATIVE_ENDIAN);
1.1.1.4 root 442: cpu_register_physical_memory(base, 0x00800000, iomemtype);
1.1 root 443: /* ??? Save/restore. */
444: }
445:
446:
447: /* Board init. */
448:
1.1.1.5 root 449: static struct arm_boot_info integrator_binfo = {
450: .loader_start = 0x0,
451: .board_id = 0x113,
452: };
453:
1.1.1.6 root 454: static void integratorcp_init(ram_addr_t ram_size,
1.1.1.5 root 455: const char *boot_device,
1.1 root 456: const char *kernel_filename, const char *kernel_cmdline,
1.1.1.4 root 457: const char *initrd_filename, const char *cpu_model)
1.1 root 458: {
459: CPUState *env;
1.1.1.6 root 460: ram_addr_t ram_offset;
461: qemu_irq pic[32];
1.1.1.4 root 462: qemu_irq *cpu_pic;
1.1.1.6 root 463: DeviceState *dev;
464: int i;
1.1.1.4 root 465:
466: if (!cpu_model)
467: cpu_model = "arm926";
468: env = cpu_init(cpu_model);
469: if (!env) {
470: fprintf(stderr, "Unable to find CPU definition\n");
471: exit(1);
472: }
1.1.1.8 root 473: ram_offset = qemu_ram_alloc(NULL, "integrator.ram", ram_size);
1.1 root 474: /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */
1.1.1.5 root 475: /* ??? RAM should repeat to fill physical memory space. */
1.1 root 476: /* SDRAM at address zero*/
1.1.1.5 root 477: cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
1.1 root 478: /* And again at address 0x80000000 */
1.1.1.5 root 479: cpu_register_physical_memory(0x80000000, ram_size, ram_offset | IO_MEM_RAM);
1.1 root 480:
1.1.1.6 root 481: dev = qdev_create(NULL, "integrator_core");
482: qdev_prop_set_uint32(dev, "memsz", ram_size >> 20);
1.1.1.7 root 483: qdev_init_nofail(dev);
1.1.1.6 root 484: sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000);
485:
1.1.1.2 root 486: cpu_pic = arm_pic_init_cpu(env);
1.1.1.6 root 487: dev = sysbus_create_varargs("integrator_pic", 0x14000000,
488: cpu_pic[ARM_PIC_CPU_IRQ],
489: cpu_pic[ARM_PIC_CPU_FIQ], NULL);
490: for (i = 0; i < 32; i++) {
491: pic[i] = qdev_get_gpio_in(dev, i);
492: }
493: sysbus_create_simple("integrator_pic", 0xca000000, pic[26]);
494: sysbus_create_varargs("integrator_pit", 0x13000000,
495: pic[5], pic[6], pic[7], NULL);
496: sysbus_create_simple("pl031", 0x15000000, pic[8]);
497: sysbus_create_simple("pl011", 0x16000000, pic[1]);
498: sysbus_create_simple("pl011", 0x17000000, pic[2]);
1.1 root 499: icp_control_init(0xcb000000);
1.1.1.6 root 500: sysbus_create_simple("pl050_keyboard", 0x18000000, pic[3]);
501: sysbus_create_simple("pl050_mouse", 0x19000000, pic[4]);
502: sysbus_create_varargs("pl181", 0x1c000000, pic[23], pic[24], NULL);
1.1.1.5 root 503: if (nd_table[0].vlan)
504: smc91c111_init(&nd_table[0], 0xc8000000, pic[27]);
1.1.1.6 root 505:
506: sysbus_create_simple("pl110", 0xc0000000, pic[22]);
1.1.1.5 root 507:
508: integrator_binfo.ram_size = ram_size;
509: integrator_binfo.kernel_filename = kernel_filename;
510: integrator_binfo.kernel_cmdline = kernel_cmdline;
511: integrator_binfo.initrd_filename = initrd_filename;
512: arm_load_kernel(env, &integrator_binfo);
1.1.1.2 root 513: }
514:
1.1.1.6 root 515: static QEMUMachine integratorcp_machine = {
1.1.1.5 root 516: .name = "integratorcp",
517: .desc = "ARM Integrator/CP (ARM926EJ-S)",
518: .init = integratorcp_init,
1.1.1.6 root 519: .is_default = 1,
1.1 root 520: };
1.1.1.6 root 521:
522: static void integratorcp_machine_init(void)
523: {
524: qemu_register_machine(&integratorcp_machine);
525: }
526:
527: machine_init(integratorcp_machine_init);
528:
529: static SysBusDeviceInfo core_info = {
530: .init = integratorcm_init,
531: .qdev.name = "integrator_core",
532: .qdev.size = sizeof(integratorcm_state),
533: .qdev.props = (Property[]) {
1.1.1.7 root 534: DEFINE_PROP_UINT32("memsz", integratorcm_state, memsz, 0),
535: DEFINE_PROP_END_OF_LIST(),
1.1.1.6 root 536: }
537: };
538:
539: static void integratorcp_register_devices(void)
540: {
541: sysbus_register_dev("integrator_pic", sizeof(icp_pic_state), icp_pic_init);
542: sysbus_register_withprop(&core_info);
543: }
544:
545: device_init(integratorcp_register_devices)
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