![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to iommu.c CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [Qemu by Fabrice Bellard] / qemu / hw|
Return to iommu.c CVS log | Up to [Qemu by Fabrice Bellard] / qemu / hw |
1.1 root 1: /*
2: * QEMU SPARC iommu emulation
3: *
4: * Copyright (c) 2003-2005 Fabrice Bellard
1.1.1.4 root 5: *
1.1 root 6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
1.1.1.6 root 24:
1.1.1.4 root 25: #include "sun4m.h"
1.1.1.6 root 26: #include "sysbus.h"
1.1 root 27:
28: /* debug iommu */
29: //#define DEBUG_IOMMU
30:
31: #ifdef DEBUG_IOMMU
1.1.1.6 root 32: #define DPRINTF(fmt, ...) \
33: do { printf("IOMMU: " fmt , ## __VA_ARGS__); } while (0)
1.1 root 34: #else
1.1.1.6 root 35: #define DPRINTF(fmt, ...)
1.1 root 36: #endif
37:
1.1.1.5 root 38: #define IOMMU_NREGS (4*4096/4)
1.1.1.2 root 39: #define IOMMU_CTRL (0x0000 >> 2)
1.1 root 40: #define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */
41: #define IOMMU_CTRL_VERS 0x0f000000 /* Version */
42: #define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */
43: #define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */
44: #define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */
45: #define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */
46: #define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */
47: #define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */
48: #define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */
49: #define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */
50: #define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */
51: #define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */
1.1.1.2 root 52: #define IOMMU_CTRL_MASK 0x0000001d
53:
54: #define IOMMU_BASE (0x0004 >> 2)
55: #define IOMMU_BASE_MASK 0x07fffc00
56:
57: #define IOMMU_TLBFLUSH (0x0014 >> 2)
58: #define IOMMU_TLBFLUSH_MASK 0xffffffff
59:
60: #define IOMMU_PGFLUSH (0x0018 >> 2)
61: #define IOMMU_PGFLUSH_MASK 0xffffffff
62:
1.1.1.4 root 63: #define IOMMU_AFSR (0x1000 >> 2)
64: #define IOMMU_AFSR_ERR 0x80000000 /* LE, TO, or BE asserted */
65: #define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after
66: transaction */
67: #define IOMMU_AFSR_TO 0x20000000 /* Write access took more than
68: 12.8 us. */
69: #define IOMMU_AFSR_BE 0x10000000 /* Write access received error
70: acknowledge */
71: #define IOMMU_AFSR_SIZE 0x0e000000 /* Size of transaction causing error */
72: #define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */
73: #define IOMMU_AFSR_RESV 0x00800000 /* Reserved, forced to 0x8 by
74: hardware */
75: #define IOMMU_AFSR_ME 0x00080000 /* Multiple errors occurred */
76: #define IOMMU_AFSR_RD 0x00040000 /* A read operation was in progress */
77: #define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */
78: #define IOMMU_AFSR_MASK 0xff0fffff
79:
80: #define IOMMU_AFAR (0x1004 >> 2)
81:
1.1.1.5 root 82: #define IOMMU_AER (0x1008 >> 2) /* Arbiter Enable Register */
83: #define IOMMU_AER_EN_P0_ARB 0x00000001 /* MBus master 0x8 (Always 1) */
84: #define IOMMU_AER_EN_P1_ARB 0x00000002 /* MBus master 0x9 */
85: #define IOMMU_AER_EN_P2_ARB 0x00000004 /* MBus master 0xa */
86: #define IOMMU_AER_EN_P3_ARB 0x00000008 /* MBus master 0xb */
87: #define IOMMU_AER_EN_0 0x00010000 /* SBus slot 0 */
88: #define IOMMU_AER_EN_1 0x00020000 /* SBus slot 1 */
89: #define IOMMU_AER_EN_2 0x00040000 /* SBus slot 2 */
90: #define IOMMU_AER_EN_3 0x00080000 /* SBus slot 3 */
91: #define IOMMU_AER_EN_F 0x00100000 /* SBus on-board */
92: #define IOMMU_AER_SBW 0x80000000 /* S-to-M asynchronous writes */
93: #define IOMMU_AER_MASK 0x801f000f
94:
1.1.1.2 root 95: #define IOMMU_SBCFG0 (0x1010 >> 2) /* SBUS configration per-slot */
96: #define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configration per-slot */
97: #define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configration per-slot */
98: #define IOMMU_SBCFG3 (0x101c >> 2) /* SBUS configration per-slot */
1.1.1.4 root 99: #define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when
100: bypass enabled */
1.1.1.2 root 101: #define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */
102: #define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */
103: #define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses
1.1.1.4 root 104: produced by this device as pure
1.1.1.2 root 105: physical. */
106: #define IOMMU_SBCFG_MASK 0x00010003
107:
108: #define IOMMU_ARBEN (0x2000 >> 2) /* SBUS arbitration enable */
109: #define IOMMU_ARBEN_MASK 0x001f0000
110: #define IOMMU_MID 0x00000008
1.1 root 111:
1.1.1.5 root 112: #define IOMMU_MASK_ID (0x3018 >> 2) /* Mask ID */
113: #define IOMMU_MASK_ID_MASK 0x00ffffff
114:
115: #define IOMMU_MSII_MASK 0x26000000 /* microSPARC II mask number */
116: #define IOMMU_TS_MASK 0x23000000 /* turboSPARC mask number */
117:
1.1 root 118: /* The format of an iopte in the page tables */
1.1.1.4 root 119: #define IOPTE_PAGE 0xffffff00 /* Physical page number (PA[35:12]) */
120: #define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or
121: Viking/MXCC) */
1.1 root 122: #define IOPTE_WRITE 0x00000004 /* Writeable */
123: #define IOPTE_VALID 0x00000002 /* IOPTE is valid */
124: #define IOPTE_WAZ 0x00000001 /* Write as zeros */
125:
1.1.1.5 root 126: #define IOMMU_PAGE_SHIFT 12
127: #define IOMMU_PAGE_SIZE (1 << IOMMU_PAGE_SHIFT)
128: #define IOMMU_PAGE_MASK ~(IOMMU_PAGE_SIZE - 1)
1.1 root 129:
130: typedef struct IOMMUState {
1.1.1.6 root 131: SysBusDevice busdev;
1.1 root 132: uint32_t regs[IOMMU_NREGS];
1.1.1.4 root 133: target_phys_addr_t iostart;
134: uint32_t version;
135: qemu_irq irq;
1.1 root 136: } IOMMUState;
137:
1.1.1.4 root 138: static uint32_t iommu_mem_readl(void *opaque, target_phys_addr_t addr)
1.1 root 139: {
140: IOMMUState *s = opaque;
1.1.1.4 root 141: target_phys_addr_t saddr;
142: uint32_t ret;
1.1 root 143:
1.1.1.5 root 144: saddr = addr >> 2;
1.1 root 145: switch (saddr) {
146: default:
1.1.1.4 root 147: ret = s->regs[saddr];
148: break;
149: case IOMMU_AFAR:
150: case IOMMU_AFSR:
151: ret = s->regs[saddr];
152: qemu_irq_lower(s->irq);
153: break;
1.1 root 154: }
1.1.1.4 root 155: DPRINTF("read reg[%d] = %x\n", (int)saddr, ret);
156: return ret;
1.1 root 157: }
158:
1.1.1.4 root 159: static void iommu_mem_writel(void *opaque, target_phys_addr_t addr,
160: uint32_t val)
1.1 root 161: {
162: IOMMUState *s = opaque;
1.1.1.4 root 163: target_phys_addr_t saddr;
1.1 root 164:
1.1.1.5 root 165: saddr = addr >> 2;
1.1.1.4 root 166: DPRINTF("write reg[%d] = %x\n", (int)saddr, val);
1.1 root 167: switch (saddr) {
1.1.1.2 root 168: case IOMMU_CTRL:
1.1.1.4 root 169: switch (val & IOMMU_CTRL_RNGE) {
170: case IOMMU_RNGE_16MB:
171: s->iostart = 0xffffffffff000000ULL;
172: break;
173: case IOMMU_RNGE_32MB:
174: s->iostart = 0xfffffffffe000000ULL;
175: break;
176: case IOMMU_RNGE_64MB:
177: s->iostart = 0xfffffffffc000000ULL;
178: break;
179: case IOMMU_RNGE_128MB:
180: s->iostart = 0xfffffffff8000000ULL;
181: break;
182: case IOMMU_RNGE_256MB:
183: s->iostart = 0xfffffffff0000000ULL;
184: break;
185: case IOMMU_RNGE_512MB:
186: s->iostart = 0xffffffffe0000000ULL;
187: break;
188: case IOMMU_RNGE_1GB:
189: s->iostart = 0xffffffffc0000000ULL;
190: break;
191: default:
192: case IOMMU_RNGE_2GB:
193: s->iostart = 0xffffffff80000000ULL;
194: break;
195: }
196: DPRINTF("iostart = " TARGET_FMT_plx "\n", s->iostart);
197: s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | s->version);
198: break;
1.1.1.2 root 199: case IOMMU_BASE:
1.1.1.4 root 200: s->regs[saddr] = val & IOMMU_BASE_MASK;
201: break;
1.1.1.2 root 202: case IOMMU_TLBFLUSH:
1.1.1.4 root 203: DPRINTF("tlb flush %x\n", val);
204: s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK;
205: break;
1.1.1.2 root 206: case IOMMU_PGFLUSH:
1.1.1.4 root 207: DPRINTF("page flush %x\n", val);
208: s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
209: break;
210: case IOMMU_AFAR:
211: s->regs[saddr] = val;
212: qemu_irq_lower(s->irq);
213: break;
1.1.1.5 root 214: case IOMMU_AER:
215: s->regs[saddr] = (val & IOMMU_AER_MASK) | IOMMU_AER_EN_P0_ARB;
216: break;
1.1.1.4 root 217: case IOMMU_AFSR:
218: s->regs[saddr] = (val & IOMMU_AFSR_MASK) | IOMMU_AFSR_RESV;
219: qemu_irq_lower(s->irq);
220: break;
1.1.1.2 root 221: case IOMMU_SBCFG0:
222: case IOMMU_SBCFG1:
223: case IOMMU_SBCFG2:
224: case IOMMU_SBCFG3:
1.1.1.4 root 225: s->regs[saddr] = val & IOMMU_SBCFG_MASK;
226: break;
1.1.1.2 root 227: case IOMMU_ARBEN:
228: // XXX implement SBus probing: fault when reading unmapped
229: // addresses, fault cause and address stored to MMU/IOMMU
1.1.1.4 root 230: s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID;
231: break;
1.1.1.5 root 232: case IOMMU_MASK_ID:
233: s->regs[saddr] |= val & IOMMU_MASK_ID_MASK;
234: break;
1.1 root 235: default:
1.1.1.4 root 236: s->regs[saddr] = val;
237: break;
1.1 root 238: }
239: }
240:
1.1.1.7 ! root 241: static CPUReadMemoryFunc * const iommu_mem_read[3] = {
1.1.1.4 root 242: NULL,
243: NULL,
244: iommu_mem_readl,
1.1 root 245: };
246:
1.1.1.7 ! root 247: static CPUWriteMemoryFunc * const iommu_mem_write[3] = {
1.1.1.4 root 248: NULL,
249: NULL,
250: iommu_mem_writel,
1.1 root 251: };
252:
1.1.1.4 root 253: static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr)
1.1 root 254: {
1.1.1.4 root 255: uint32_t ret;
256: target_phys_addr_t iopte;
257: #ifdef DEBUG_IOMMU
258: target_phys_addr_t pa = addr;
259: #endif
1.1 root 260:
1.1.1.4 root 261: iopte = s->regs[IOMMU_BASE] << 4;
1.1 root 262: addr &= ~s->iostart;
1.1.1.5 root 263: iopte += (addr >> (IOMMU_PAGE_SHIFT - 2)) & ~3;
1.1.1.4 root 264: cpu_physical_memory_read(iopte, (uint8_t *)&ret, 4);
265: tswap32s(&ret);
266: DPRINTF("get flags addr " TARGET_FMT_plx " => pte " TARGET_FMT_plx
267: ", *pte = %x\n", pa, iopte, ret);
268:
269: return ret;
1.1.1.3 root 270: }
271:
1.1.1.5 root 272: static target_phys_addr_t iommu_translate_pa(target_phys_addr_t addr,
1.1.1.4 root 273: uint32_t pte)
1.1.1.3 root 274: {
275: uint32_t tmppte;
1.1.1.4 root 276: target_phys_addr_t pa;
277:
278: tmppte = pte;
1.1.1.5 root 279: pa = ((pte & IOPTE_PAGE) << 4) + (addr & ~IOMMU_PAGE_MASK);
1.1.1.4 root 280: DPRINTF("xlate dva " TARGET_FMT_plx " => pa " TARGET_FMT_plx
281: " (iopte = %x)\n", addr, pa, tmppte);
1.1.1.3 root 282:
1.1 root 283: return pa;
284: }
285:
1.1.1.4 root 286: static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr,
287: int is_write)
288: {
289: DPRINTF("bad addr " TARGET_FMT_plx "\n", addr);
290: s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR | IOMMU_AFSR_LE | IOMMU_AFSR_RESV |
291: IOMMU_AFSR_FAV;
292: if (!is_write)
293: s->regs[IOMMU_AFSR] |= IOMMU_AFSR_RD;
294: s->regs[IOMMU_AFAR] = addr;
295: qemu_irq_raise(s->irq);
296: }
297:
1.1.1.3 root 298: void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
299: uint8_t *buf, int len, int is_write)
300: {
1.1.1.4 root 301: int l;
302: uint32_t flags;
303: target_phys_addr_t page, phys_addr;
1.1.1.3 root 304:
305: while (len > 0) {
1.1.1.5 root 306: page = addr & IOMMU_PAGE_MASK;
307: l = (page + IOMMU_PAGE_SIZE) - addr;
1.1.1.3 root 308: if (l > len)
309: l = len;
310: flags = iommu_page_get_flags(opaque, page);
1.1.1.4 root 311: if (!(flags & IOPTE_VALID)) {
312: iommu_bad_addr(opaque, page, is_write);
1.1.1.3 root 313: return;
1.1.1.4 root 314: }
1.1.1.5 root 315: phys_addr = iommu_translate_pa(addr, flags);
1.1.1.3 root 316: if (is_write) {
1.1.1.4 root 317: if (!(flags & IOPTE_WRITE)) {
318: iommu_bad_addr(opaque, page, is_write);
1.1.1.3 root 319: return;
1.1.1.4 root 320: }
1.1.1.5 root 321: cpu_physical_memory_write(phys_addr, buf, l);
1.1.1.3 root 322: } else {
1.1.1.5 root 323: cpu_physical_memory_read(phys_addr, buf, l);
1.1.1.3 root 324: }
325: len -= l;
326: buf += l;
327: addr += l;
328: }
329: }
330:
1.1.1.7 ! root 331: static const VMStateDescription vmstate_iommu = {
! 332: .name ="iommu",
! 333: .version_id = 2,
! 334: .minimum_version_id = 2,
! 335: .minimum_version_id_old = 2,
! 336: .fields = (VMStateField []) {
! 337: VMSTATE_UINT32_ARRAY(regs, IOMMUState, IOMMU_NREGS),
! 338: VMSTATE_UINT64(iostart, IOMMUState),
! 339: VMSTATE_END_OF_LIST()
! 340: }
! 341: };
1.1 root 342:
1.1.1.7 ! root 343: static void iommu_reset(DeviceState *d)
1.1 root 344: {
1.1.1.7 ! root 345: IOMMUState *s = container_of(d, IOMMUState, busdev.qdev);
1.1 root 346:
347: memset(s->regs, 0, IOMMU_NREGS * 4);
348: s->iostart = 0;
1.1.1.4 root 349: s->regs[IOMMU_CTRL] = s->version;
350: s->regs[IOMMU_ARBEN] = IOMMU_MID;
351: s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV;
1.1.1.5 root 352: s->regs[IOMMU_AER] = IOMMU_AER_EN_P0_ARB | IOMMU_AER_EN_P1_ARB;
353: s->regs[IOMMU_MASK_ID] = IOMMU_TS_MASK;
1.1 root 354: }
355:
1.1.1.7 ! root 356: static int iommu_init1(SysBusDevice *dev)
1.1.1.6 root 357: {
358: IOMMUState *s = FROM_SYSBUS(IOMMUState, dev);
359: int io;
1.1 root 360:
1.1.1.6 root 361: sysbus_init_irq(dev, &s->irq);
1.1 root 362:
1.1.1.6 root 363: io = cpu_register_io_memory(iommu_mem_read, iommu_mem_write, s);
364: sysbus_init_mmio(dev, IOMMU_NREGS * sizeof(uint32_t), io);
1.1.1.4 root 365:
1.1.1.7 ! root 366: return 0;
1.1 root 367: }
1.1.1.6 root 368:
369: static SysBusDeviceInfo iommu_info = {
370: .init = iommu_init1,
371: .qdev.name = "iommu",
372: .qdev.size = sizeof(IOMMUState),
1.1.1.7 ! root 373: .qdev.vmsd = &vmstate_iommu,
! 374: .qdev.reset = iommu_reset,
1.1.1.6 root 375: .qdev.props = (Property[]) {
1.1.1.7 ! root 376: DEFINE_PROP_HEX32("version", IOMMUState, version, 0),
! 377: DEFINE_PROP_END_OF_LIST(),
1.1.1.6 root 378: }
379: };
380:
381: static void iommu_register_devices(void)
382: {
383: sysbus_register_withprop(&iommu_info);
384: }
385:
386: device_init(iommu_register_devices)
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.