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1.1 root 1: /* 1.1.1.4 ! root 2: * QEMU AMD PC-Net II (Am79C970A) emulation ! 3: * ! 4: * Copyright (c) 2004 Antony T Curtis ! 5: * 1.1 root 6: * Permission is hereby granted, free of charge, to any person obtaining a copy 7: * of this software and associated documentation files (the "Software"), to deal 8: * in the Software without restriction, including without limitation the rights 9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10: * copies of the Software, and to permit persons to whom the Software is 11: * furnished to do so, subject to the following conditions: 12: * 13: * The above copyright notice and this permission notice shall be included in 14: * all copies or substantial portions of the Software. 15: * 16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22: * THE SOFTWARE. 23: */ 24: 1.1.1.4 ! root 25: /* This software was written to be compatible with the specification: ! 26: * AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet ! 27: * AMD Publication# 19436 Rev:E Amendment/0 Issue Date: June 2000 ! 28: */ 1.1 root 29: 1.1.1.4 ! root 30: /* ! 31: * On Sparc32, this is the Lance (Am7990) part of chip STP2000 (Master I/O), also ! 32: * produced as NCR89C100. See ! 33: * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt ! 34: * and ! 35: * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR92C990.txt ! 36: */ 1.1 root 37: 1.1.1.4 ! root 38: #include "sysbus.h" ! 39: #include "net.h" ! 40: #include "qemu-timer.h" ! 41: #include "qemu_socket.h" ! 42: #include "sun4m.h" 1.1 root 43: 1.1.1.4 ! root 44: #include "pcnet.h" 1.1 root 45: 1.1.1.4 ! root 46: typedef struct { ! 47: SysBusDevice busdev; ! 48: PCNetState state; ! 49: } SysBusPCNetState; 1.1 root 50: 1.1.1.4 ! root 51: static void parent_lance_reset(void *opaque, int irq, int level) ! 52: { ! 53: SysBusPCNetState *d = opaque; ! 54: if (level) ! 55: pcnet_h_reset(&d->state); ! 56: } 1.1 root 57: 1.1.1.4 ! root 58: static void lance_mem_writew(void *opaque, target_phys_addr_t addr, ! 59: uint32_t val) 1.1 root 60: { 1.1.1.4 ! root 61: SysBusPCNetState *d = opaque; ! 62: #ifdef PCNET_DEBUG_IO ! 63: printf("lance_mem_writew addr=" TARGET_FMT_plx " val=0x%04x\n", addr, ! 64: val & 0xffff); ! 65: #endif ! 66: pcnet_ioport_writew(&d->state, addr, val & 0xffff); 1.1 root 67: } 68: 69: static uint32_t lance_mem_readw(void *opaque, target_phys_addr_t addr) 70: { 1.1.1.4 ! root 71: SysBusPCNetState *d = opaque; ! 72: uint32_t val; 1.1 root 73: 1.1.1.4 ! root 74: val = pcnet_ioport_readw(&d->state, addr); ! 75: #ifdef PCNET_DEBUG_IO ! 76: printf("lance_mem_readw addr=" TARGET_FMT_plx " val = 0x%04x\n", addr, ! 77: val & 0xffff); ! 78: #endif 1.1 root 79: 1.1.1.4 ! root 80: return val & 0xffff; 1.1 root 81: } 82: 1.1.1.4 ! root 83: static CPUReadMemoryFunc * const lance_mem_read[3] = { ! 84: NULL, 1.1 root 85: lance_mem_readw, 1.1.1.4 ! root 86: NULL, 1.1 root 87: }; 88: 1.1.1.4 ! root 89: static CPUWriteMemoryFunc * const lance_mem_write[3] = { ! 90: NULL, 1.1 root 91: lance_mem_writew, 1.1.1.4 ! root 92: NULL, 1.1 root 93: }; 94: 1.1.1.4 ! root 95: static void lance_cleanup(VLANClientState *nc) 1.1.1.3 root 96: { 1.1.1.4 ! root 97: PCNetState *d = DO_UPCAST(NICState, nc, nc)->opaque; 1.1.1.3 root 98: 1.1.1.4 ! root 99: pcnet_common_cleanup(d); 1.1 root 100: } 101: 1.1.1.4 ! root 102: static NetClientInfo net_lance_info = { ! 103: .type = NET_CLIENT_TYPE_NIC, ! 104: .size = sizeof(NICState), ! 105: .can_receive = pcnet_can_receive, ! 106: .receive = pcnet_receive, ! 107: .cleanup = lance_cleanup, 1.1 root 108: }; 109: 1.1.1.4 ! root 110: static const VMStateDescription vmstate_lance = { ! 111: .name = "pcnet", ! 112: .version_id = 3, ! 113: .minimum_version_id = 2, ! 114: .minimum_version_id_old = 2, ! 115: .fields = (VMStateField []) { ! 116: VMSTATE_STRUCT(state, SysBusPCNetState, 0, vmstate_pcnet, PCNetState), ! 117: VMSTATE_END_OF_LIST() ! 118: } 1.1 root 119: }; 120: 1.1.1.4 ! root 121: static int lance_init(SysBusDevice *dev) 1.1 root 122: { 1.1.1.4 ! root 123: SysBusPCNetState *d = FROM_SYSBUS(SysBusPCNetState, dev); ! 124: PCNetState *s = &d->state; 1.1 root 125: 1.1.1.4 ! root 126: s->mmio_index = ! 127: cpu_register_io_memory(lance_mem_read, lance_mem_write, d); 1.1 root 128: 1.1.1.4 ! root 129: qdev_init_gpio_in(&dev->qdev, parent_lance_reset, 1); 1.1 root 130: 1.1.1.4 ! root 131: sysbus_init_mmio(dev, 4, s->mmio_index); 1.1 root 132: 1.1.1.4 ! root 133: sysbus_init_irq(dev, &s->irq); 1.1 root 134: 1.1.1.4 ! root 135: s->phys_mem_read = ledma_memory_read; ! 136: s->phys_mem_write = ledma_memory_write; ! 137: return pcnet_common_init(&dev->qdev, s, &net_lance_info); ! 138: } 1.1.1.2 root 139: 1.1.1.4 ! root 140: static void lance_reset(DeviceState *dev) ! 141: { ! 142: SysBusPCNetState *d = DO_UPCAST(SysBusPCNetState, busdev.qdev, dev); 1.1.1.2 root 143: 1.1.1.4 ! root 144: pcnet_h_reset(&d->state); ! 145: } 1.1.1.2 root 146: 1.1.1.4 ! root 147: static SysBusDeviceInfo lance_info = { ! 148: .init = lance_init, ! 149: .qdev.name = "lance", ! 150: .qdev.size = sizeof(SysBusPCNetState), ! 151: .qdev.reset = lance_reset, ! 152: .qdev.vmsd = &vmstate_lance, ! 153: .qdev.props = (Property[]) { ! 154: DEFINE_PROP_PTR("dma", SysBusPCNetState, state.dma_opaque), ! 155: DEFINE_NIC_PROPERTIES(SysBusPCNetState, state.conf), ! 156: DEFINE_PROP_END_OF_LIST(), ! 157: } ! 158: }; 1.1.1.2 root 159: 1.1.1.4 ! root 160: static void lance_register_devices(void) ! 161: { ! 162: sysbus_register_withprop(&lance_info); 1.1 root 163: } 1.1.1.4 ! root 164: device_init(lance_register_devices)
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