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1.1 root 1: /*
1.1.1.4 root 2: * QEMU AMD PC-Net II (Am79C970A) emulation
3: *
4: * Copyright (c) 2004 Antony T Curtis
5: *
1.1 root 6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
24:
1.1.1.4 root 25: /* This software was written to be compatible with the specification:
26: * AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet
27: * AMD Publication# 19436 Rev:E Amendment/0 Issue Date: June 2000
28: */
1.1 root 29:
1.1.1.4 root 30: /*
31: * On Sparc32, this is the Lance (Am7990) part of chip STP2000 (Master I/O), also
32: * produced as NCR89C100. See
33: * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
34: * and
35: * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR92C990.txt
36: */
1.1 root 37:
1.1.1.4 root 38: #include "sysbus.h"
39: #include "net.h"
40: #include "qemu-timer.h"
41: #include "qemu_socket.h"
42: #include "sun4m.h"
43: #include "pcnet.h"
1.1.1.5 ! root 44: #include "trace.h"
1.1 root 45:
1.1.1.4 root 46: typedef struct {
47: SysBusDevice busdev;
48: PCNetState state;
49: } SysBusPCNetState;
1.1 root 50:
1.1.1.4 root 51: static void parent_lance_reset(void *opaque, int irq, int level)
52: {
53: SysBusPCNetState *d = opaque;
54: if (level)
55: pcnet_h_reset(&d->state);
56: }
1.1 root 57:
1.1.1.4 root 58: static void lance_mem_writew(void *opaque, target_phys_addr_t addr,
59: uint32_t val)
1.1 root 60: {
1.1.1.4 root 61: SysBusPCNetState *d = opaque;
1.1.1.5 ! root 62:
! 63: trace_lance_mem_writew(addr, val & 0xffff);
1.1.1.4 root 64: pcnet_ioport_writew(&d->state, addr, val & 0xffff);
1.1 root 65: }
66:
67: static uint32_t lance_mem_readw(void *opaque, target_phys_addr_t addr)
68: {
1.1.1.4 root 69: SysBusPCNetState *d = opaque;
70: uint32_t val;
1.1 root 71:
1.1.1.4 root 72: val = pcnet_ioport_readw(&d->state, addr);
1.1.1.5 ! root 73: trace_lance_mem_readw(addr, val & 0xffff);
1.1.1.4 root 74: return val & 0xffff;
1.1 root 75: }
76:
1.1.1.4 root 77: static CPUReadMemoryFunc * const lance_mem_read[3] = {
78: NULL,
1.1 root 79: lance_mem_readw,
1.1.1.4 root 80: NULL,
1.1 root 81: };
82:
1.1.1.4 root 83: static CPUWriteMemoryFunc * const lance_mem_write[3] = {
84: NULL,
1.1 root 85: lance_mem_writew,
1.1.1.4 root 86: NULL,
1.1 root 87: };
88:
1.1.1.4 root 89: static void lance_cleanup(VLANClientState *nc)
1.1.1.3 root 90: {
1.1.1.4 root 91: PCNetState *d = DO_UPCAST(NICState, nc, nc)->opaque;
1.1.1.3 root 92:
1.1.1.4 root 93: pcnet_common_cleanup(d);
1.1 root 94: }
95:
1.1.1.4 root 96: static NetClientInfo net_lance_info = {
97: .type = NET_CLIENT_TYPE_NIC,
98: .size = sizeof(NICState),
99: .can_receive = pcnet_can_receive,
100: .receive = pcnet_receive,
101: .cleanup = lance_cleanup,
1.1 root 102: };
103:
1.1.1.4 root 104: static const VMStateDescription vmstate_lance = {
105: .name = "pcnet",
106: .version_id = 3,
107: .minimum_version_id = 2,
108: .minimum_version_id_old = 2,
109: .fields = (VMStateField []) {
110: VMSTATE_STRUCT(state, SysBusPCNetState, 0, vmstate_pcnet, PCNetState),
111: VMSTATE_END_OF_LIST()
112: }
1.1 root 113: };
114:
1.1.1.4 root 115: static int lance_init(SysBusDevice *dev)
1.1 root 116: {
1.1.1.4 root 117: SysBusPCNetState *d = FROM_SYSBUS(SysBusPCNetState, dev);
118: PCNetState *s = &d->state;
1.1 root 119:
1.1.1.4 root 120: s->mmio_index =
1.1.1.5 ! root 121: cpu_register_io_memory(lance_mem_read, lance_mem_write, d,
! 122: DEVICE_NATIVE_ENDIAN);
1.1 root 123:
1.1.1.4 root 124: qdev_init_gpio_in(&dev->qdev, parent_lance_reset, 1);
1.1 root 125:
1.1.1.4 root 126: sysbus_init_mmio(dev, 4, s->mmio_index);
1.1 root 127:
1.1.1.4 root 128: sysbus_init_irq(dev, &s->irq);
1.1 root 129:
1.1.1.4 root 130: s->phys_mem_read = ledma_memory_read;
131: s->phys_mem_write = ledma_memory_write;
132: return pcnet_common_init(&dev->qdev, s, &net_lance_info);
133: }
1.1.1.2 root 134:
1.1.1.4 root 135: static void lance_reset(DeviceState *dev)
136: {
137: SysBusPCNetState *d = DO_UPCAST(SysBusPCNetState, busdev.qdev, dev);
1.1.1.2 root 138:
1.1.1.4 root 139: pcnet_h_reset(&d->state);
140: }
1.1.1.2 root 141:
1.1.1.4 root 142: static SysBusDeviceInfo lance_info = {
143: .init = lance_init,
144: .qdev.name = "lance",
1.1.1.5 ! root 145: .qdev.fw_name = "ethernet",
1.1.1.4 root 146: .qdev.size = sizeof(SysBusPCNetState),
147: .qdev.reset = lance_reset,
148: .qdev.vmsd = &vmstate_lance,
149: .qdev.props = (Property[]) {
150: DEFINE_PROP_PTR("dma", SysBusPCNetState, state.dma_opaque),
151: DEFINE_NIC_PROPERTIES(SysBusPCNetState, state.conf),
152: DEFINE_PROP_END_OF_LIST(),
153: }
154: };
1.1.1.2 root 155:
1.1.1.4 root 156: static void lance_register_devices(void)
157: {
158: sysbus_register_withprop(&lance_info);
1.1 root 159: }
1.1.1.4 root 160: device_init(lance_register_devices)
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