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1.1 root 1: /*
2: * PowerMac MacIO device emulation
3: *
4: * Copyright (c) 2005-2007 Fabrice Bellard
5: * Copyright (c) 2007 Jocelyn Mayer
6: *
7: * Permission is hereby granted, free of charge, to any person obtaining a copy
8: * of this software and associated documentation files (the "Software"), to deal
9: * in the Software without restriction, including without limitation the rights
10: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11: * copies of the Software, and to permit persons to whom the Software is
12: * furnished to do so, subject to the following conditions:
13: *
14: * The above copyright notice and this permission notice shall be included in
15: * all copies or substantial portions of the Software.
16: *
17: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23: * THE SOFTWARE.
24: */
25: #include "hw.h"
26: #include "ppc_mac.h"
27: #include "pci.h"
1.1.1.2 root 28: #include "escc.h"
1.1 root 29:
30: typedef struct macio_state_t macio_state_t;
31: struct macio_state_t {
32: int is_oldworld;
33: int pic_mem_index;
34: int dbdma_mem_index;
35: int cuda_mem_index;
1.1.1.2 root 36: int escc_mem_index;
1.1 root 37: void *nvram;
38: int nb_ide;
39: int ide_mem_index[4];
40: };
41:
42: static void macio_map (PCIDevice *pci_dev, int region_num,
1.1.1.4 root 43: pcibus_t addr, pcibus_t size, int type)
1.1 root 44: {
45: macio_state_t *macio_state;
46: int i;
47:
48: macio_state = (macio_state_t *)(pci_dev + 1);
49: if (macio_state->pic_mem_index >= 0) {
50: if (macio_state->is_oldworld) {
51: /* Heathrow PIC */
52: cpu_register_physical_memory(addr + 0x00000, 0x1000,
53: macio_state->pic_mem_index);
54: } else {
55: /* OpenPIC */
56: cpu_register_physical_memory(addr + 0x40000, 0x40000,
57: macio_state->pic_mem_index);
58: }
59: }
60: if (macio_state->dbdma_mem_index >= 0) {
61: cpu_register_physical_memory(addr + 0x08000, 0x1000,
62: macio_state->dbdma_mem_index);
63: }
1.1.1.2 root 64: if (macio_state->escc_mem_index >= 0) {
65: cpu_register_physical_memory(addr + 0x13000, ESCC_SIZE << 4,
66: macio_state->escc_mem_index);
67: }
1.1 root 68: if (macio_state->cuda_mem_index >= 0) {
69: cpu_register_physical_memory(addr + 0x16000, 0x2000,
70: macio_state->cuda_mem_index);
71: }
72: for (i = 0; i < macio_state->nb_ide; i++) {
73: if (macio_state->ide_mem_index[i] >= 0) {
74: cpu_register_physical_memory(addr + 0x1f000 + (i * 0x1000), 0x1000,
75: macio_state->ide_mem_index[i]);
76: }
77: }
78: if (macio_state->nvram != NULL)
79: macio_nvram_map(macio_state->nvram, addr + 0x60000);
80: }
81:
82: void macio_init (PCIBus *bus, int device_id, int is_oldworld, int pic_mem_index,
83: int dbdma_mem_index, int cuda_mem_index, void *nvram,
1.1.1.2 root 84: int nb_ide, int *ide_mem_index, int escc_mem_index)
1.1 root 85: {
86: PCIDevice *d;
87: macio_state_t *macio_state;
88: int i;
89:
90: d = pci_register_device(bus, "macio",
91: sizeof(PCIDevice) + sizeof(macio_state_t),
92: -1, NULL, NULL);
93: macio_state = (macio_state_t *)(d + 1);
94: macio_state->is_oldworld = is_oldworld;
95: macio_state->pic_mem_index = pic_mem_index;
96: macio_state->dbdma_mem_index = dbdma_mem_index;
97: macio_state->cuda_mem_index = cuda_mem_index;
1.1.1.2 root 98: macio_state->escc_mem_index = escc_mem_index;
1.1 root 99: macio_state->nvram = nvram;
100: if (nb_ide > 4)
101: nb_ide = 4;
102: macio_state->nb_ide = nb_ide;
103: for (i = 0; i < nb_ide; i++)
104: macio_state->ide_mem_index[i] = ide_mem_index[i];
105: for (; i < 4; i++)
106: macio_state->ide_mem_index[i] = -1;
107: /* Note: this code is strongly inspirated from the corresponding code
108: in PearPC */
109:
1.1.1.2 root 110: pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
111: pci_config_set_device_id(d->config, device_id);
112: pci_config_set_class(d->config, PCI_CLASS_OTHERS << 8);
1.1 root 113:
114: d->config[0x3d] = 0x01; // interrupt on pin 1
115:
1.1.1.3 root 116: pci_register_bar(d, 0, 0x80000,
1.1.1.4 root 117: PCI_BASE_ADDRESS_SPACE_MEMORY, macio_map);
1.1 root 118: }
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