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1.1 root 1: /*
2: * PowerMac MacIO device emulation
3: *
4: * Copyright (c) 2005-2007 Fabrice Bellard
5: * Copyright (c) 2007 Jocelyn Mayer
6: *
7: * Permission is hereby granted, free of charge, to any person obtaining a copy
8: * of this software and associated documentation files (the "Software"), to deal
9: * in the Software without restriction, including without limitation the rights
10: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11: * copies of the Software, and to permit persons to whom the Software is
12: * furnished to do so, subject to the following conditions:
13: *
14: * The above copyright notice and this permission notice shall be included in
15: * all copies or substantial portions of the Software.
16: *
17: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23: * THE SOFTWARE.
24: */
25: #include "hw.h"
26: #include "ppc_mac.h"
27: #include "pci.h"
1.1.1.2 root 28: #include "escc.h"
1.1 root 29:
30: typedef struct macio_state_t macio_state_t;
31: struct macio_state_t {
32: int is_oldworld;
1.1.1.6 ! root 33: MemoryRegion bar;
! 34: MemoryRegion *pic_mem;
! 35: MemoryRegion *dbdma_mem;
! 36: MemoryRegion *cuda_mem;
! 37: MemoryRegion *escc_mem;
1.1 root 38: void *nvram;
39: int nb_ide;
1.1.1.6 ! root 40: MemoryRegion *ide_mem[4];
1.1 root 41: };
42:
1.1.1.6 ! root 43: static void macio_bar_setup(macio_state_t *macio_state)
1.1 root 44: {
45: int i;
1.1.1.6 ! root 46: MemoryRegion *bar = &macio_state->bar;
1.1 root 47:
1.1.1.6 ! root 48: memory_region_init(bar, "macio", 0x80000);
! 49: if (macio_state->pic_mem) {
1.1 root 50: if (macio_state->is_oldworld) {
51: /* Heathrow PIC */
1.1.1.6 ! root 52: memory_region_add_subregion(bar, 0x00000, macio_state->pic_mem);
1.1 root 53: } else {
54: /* OpenPIC */
1.1.1.6 ! root 55: memory_region_add_subregion(bar, 0x40000, macio_state->pic_mem);
1.1 root 56: }
57: }
1.1.1.6 ! root 58: if (macio_state->dbdma_mem) {
! 59: memory_region_add_subregion(bar, 0x08000, macio_state->dbdma_mem);
1.1 root 60: }
1.1.1.6 ! root 61: if (macio_state->escc_mem) {
! 62: memory_region_add_subregion(bar, 0x13000, macio_state->escc_mem);
1.1.1.2 root 63: }
1.1.1.6 ! root 64: if (macio_state->cuda_mem) {
! 65: memory_region_add_subregion(bar, 0x16000, macio_state->cuda_mem);
1.1 root 66: }
67: for (i = 0; i < macio_state->nb_ide; i++) {
1.1.1.6 ! root 68: if (macio_state->ide_mem[i]) {
! 69: memory_region_add_subregion(bar, 0x1f000 + (i * 0x1000),
! 70: macio_state->ide_mem[i]);
1.1 root 71: }
72: }
73: if (macio_state->nvram != NULL)
1.1.1.6 ! root 74: macio_nvram_setup_bar(macio_state->nvram, bar, 0x60000);
1.1 root 75: }
76:
1.1.1.6 ! root 77: void macio_init (PCIBus *bus, int device_id, int is_oldworld,
! 78: MemoryRegion *pic_mem, MemoryRegion *dbdma_mem,
! 79: MemoryRegion *cuda_mem, void *nvram,
! 80: int nb_ide, MemoryRegion **ide_mem,
! 81: MemoryRegion *escc_mem)
1.1 root 82: {
83: PCIDevice *d;
84: macio_state_t *macio_state;
85: int i;
86:
87: d = pci_register_device(bus, "macio",
88: sizeof(PCIDevice) + sizeof(macio_state_t),
89: -1, NULL, NULL);
90: macio_state = (macio_state_t *)(d + 1);
91: macio_state->is_oldworld = is_oldworld;
1.1.1.6 ! root 92: macio_state->pic_mem = pic_mem;
! 93: macio_state->dbdma_mem = dbdma_mem;
! 94: macio_state->cuda_mem = cuda_mem;
! 95: macio_state->escc_mem = escc_mem;
1.1 root 96: macio_state->nvram = nvram;
97: if (nb_ide > 4)
98: nb_ide = 4;
99: macio_state->nb_ide = nb_ide;
100: for (i = 0; i < nb_ide; i++)
1.1.1.6 ! root 101: macio_state->ide_mem[i] = ide_mem[i];
1.1 root 102: for (; i < 4; i++)
1.1.1.6 ! root 103: macio_state->ide_mem[i] = NULL;
1.1 root 104: /* Note: this code is strongly inspirated from the corresponding code
105: in PearPC */
106:
1.1.1.2 root 107: pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
108: pci_config_set_device_id(d->config, device_id);
109: pci_config_set_class(d->config, PCI_CLASS_OTHERS << 8);
1.1 root 110:
111: d->config[0x3d] = 0x01; // interrupt on pin 1
112:
1.1.1.6 ! root 113: macio_bar_setup(macio_state);
! 114: pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &macio_state->bar);
1.1 root 115: }
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