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1.1 root 1: /*
2: * QEMU MIPS Jazz support
3: *
4: * Copyright (c) 2007-2008 Hervé Poussineau
5: *
6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
24:
25: #include "hw.h"
26: #include "mips.h"
1.1.1.4 root 27: #include "mips_cpudevs.h"
1.1 root 28: #include "pc.h"
29: #include "isa.h"
30: #include "fdc.h"
31: #include "sysemu.h"
1.1.1.5 root 32: #include "arch_init.h"
1.1 root 33: #include "boards.h"
34: #include "net.h"
1.1.1.3 root 35: #include "esp.h"
1.1.1.2 root 36: #include "mips-bios.h"
1.1.1.3 root 37: #include "loader.h"
1.1.1.4 root 38: #include "mc146818rtc.h"
1.1.1.5 root 39: #include "blockdev.h"
1.1.1.6 root 40: #include "sysbus.h"
1.1.1.7 ! root 41: #include "exec-memory.h"
1.1 root 42:
43: enum jazz_model_e
44: {
45: JAZZ_MAGNUM,
46: JAZZ_PICA61,
47: };
48:
49: static void main_cpu_reset(void *opaque)
50: {
51: CPUState *env = opaque;
52: cpu_reset(env);
53: }
54:
1.1.1.7 ! root 55: static uint64_t rtc_read(void *opaque, target_phys_addr_t addr, unsigned size)
1.1 root 56: {
1.1.1.3 root 57: return cpu_inw(0x71);
1.1 root 58: }
59:
1.1.1.7 ! root 60: static void rtc_write(void *opaque, target_phys_addr_t addr,
! 61: uint64_t val, unsigned size)
1.1 root 62: {
1.1.1.3 root 63: cpu_outw(0x71, val & 0xff);
1.1 root 64: }
65:
1.1.1.7 ! root 66: static const MemoryRegionOps rtc_ops = {
! 67: .read = rtc_read,
! 68: .write = rtc_write,
! 69: .endianness = DEVICE_NATIVE_ENDIAN,
1.1 root 70: };
71:
1.1.1.7 ! root 72: static uint64_t dma_dummy_read(void *opaque, target_phys_addr_t addr,
! 73: unsigned size)
1.1 root 74: {
75: /* Nothing to do. That is only to ensure that
76: * the current DMA acknowledge cycle is completed. */
1.1.1.7 ! root 77: return 0xff;
1.1 root 78: }
79:
1.1.1.7 ! root 80: static void dma_dummy_write(void *opaque, target_phys_addr_t addr,
! 81: uint64_t val, unsigned size)
! 82: {
! 83: /* Nothing to do. That is only to ensure that
! 84: * the current DMA acknowledge cycle is completed. */
! 85: }
1.1 root 86:
1.1.1.7 ! root 87: static const MemoryRegionOps dma_dummy_ops = {
! 88: .read = dma_dummy_read,
! 89: .write = dma_dummy_write,
! 90: .endianness = DEVICE_NATIVE_ENDIAN,
1.1 root 91: };
92:
93: #define MAGNUM_BIOS_SIZE_MAX 0x7e000
94: #define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
95:
1.1.1.4 root 96: static void cpu_request_exit(void *opaque, int irq, int level)
97: {
98: CPUState *env = cpu_single_env;
99:
100: if (env && level) {
101: cpu_exit(env);
102: }
103: }
104:
1.1.1.7 ! root 105: static void mips_jazz_init(MemoryRegion *address_space,
! 106: MemoryRegion *address_space_io,
! 107: ram_addr_t ram_size,
! 108: const char *cpu_model,
! 109: enum jazz_model_e jazz_model)
1.1 root 110: {
1.1.1.2 root 111: char *filename;
1.1 root 112: int bios_size, n;
113: CPUState *env;
114: qemu_irq *rc4030, *i8259;
115: rc4030_dma *dmas;
1.1.1.2 root 116: void* rc4030_opaque;
1.1.1.7 ! root 117: MemoryRegion *rtc = g_new(MemoryRegion, 1);
! 118: MemoryRegion *i8042 = g_new(MemoryRegion, 1);
! 119: MemoryRegion *dma_dummy = g_new(MemoryRegion, 1);
1.1.1.2 root 120: NICInfo *nd;
1.1.1.6 root 121: DeviceState *dev;
122: SysBusDevice *sysbus;
123: ISADevice *pit;
1.1.1.3 root 124: DriveInfo *fds[MAX_FD];
1.1.1.5 root 125: qemu_irq esp_reset, dma_enable;
1.1.1.4 root 126: qemu_irq *cpu_exit_irq;
1.1.1.7 ! root 127: MemoryRegion *ram = g_new(MemoryRegion, 1);
! 128: MemoryRegion *bios = g_new(MemoryRegion, 1);
! 129: MemoryRegion *bios2 = g_new(MemoryRegion, 1);
1.1 root 130:
131: /* init CPUs */
132: if (cpu_model == NULL) {
133: #ifdef TARGET_MIPS64
134: cpu_model = "R4000";
135: #else
136: /* FIXME: All wrong, this maybe should be R3000 for the older JAZZs. */
137: cpu_model = "24Kf";
138: #endif
139: }
140: env = cpu_init(cpu_model);
141: if (!env) {
142: fprintf(stderr, "Unable to find CPU definition\n");
143: exit(1);
144: }
145: qemu_register_reset(main_cpu_reset, env);
146:
147: /* allocate RAM */
1.1.1.7 ! root 148: memory_region_init_ram(ram, NULL, "mips_jazz.ram", ram_size);
! 149: memory_region_add_subregion(address_space, 0, ram);
1.1.1.2 root 150:
1.1.1.7 ! root 151: memory_region_init_ram(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE);
! 152: memory_region_set_readonly(bios, true);
! 153: memory_region_init_alias(bios2, "mips_jazz.bios", bios,
! 154: 0, MAGNUM_BIOS_SIZE);
! 155: memory_region_add_subregion(address_space, 0x1fc00000LL, bios);
! 156: memory_region_add_subregion(address_space, 0xfff00000LL, bios2);
1.1 root 157:
158: /* load the BIOS image. */
159: if (bios_name == NULL)
160: bios_name = BIOS_FILENAME;
1.1.1.2 root 161: filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
162: if (filename) {
163: bios_size = load_image_targphys(filename, 0xfff00000LL,
164: MAGNUM_BIOS_SIZE);
1.1.1.7 ! root 165: g_free(filename);
1.1.1.2 root 166: } else {
167: bios_size = -1;
168: }
1.1 root 169: if (bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) {
170: fprintf(stderr, "qemu: Could not load MIPS bios '%s'\n",
1.1.1.2 root 171: bios_name);
1.1 root 172: exit(1);
173: }
174:
175: /* Init CPU internal devices */
176: cpu_mips_irq_init_cpu(env);
177: cpu_mips_clock_init(env);
178:
179: /* Chipset */
1.1.1.2 root 180: rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas);
1.1.1.7 ! root 181: memory_region_init_io(dma_dummy, &dma_dummy_ops, NULL, "dummy_dma", 0x1000);
! 182: memory_region_add_subregion(address_space, 0x8000d000, dma_dummy);
1.1 root 183:
184: /* ISA devices */
1.1.1.7 ! root 185: isa_bus_new(NULL, address_space_io);
1.1 root 186: i8259 = i8259_init(env->irq[4]);
1.1.1.3 root 187: isa_bus_irqs(i8259);
1.1.1.4 root 188: cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
189: DMA_init(0, cpu_exit_irq);
1.1.1.6 root 190: pit = pit_init(0x40, 0);
1.1 root 191: pcspk_init(pit);
192:
193: /* ISA IO space at 0x90000000 */
1.1.1.5 root 194: isa_mmio_init(0x90000000, 0x01000000);
1.1 root 195: isa_mem_base = 0x11000000;
196:
197: /* Video card */
198: switch (jazz_model) {
199: case JAZZ_MAGNUM:
1.1.1.7 ! root 200: dev = qdev_create(NULL, "sysbus-g364");
! 201: qdev_init_nofail(dev);
! 202: sysbus = sysbus_from_qdev(dev);
! 203: sysbus_mmio_map(sysbus, 0, 0x60080000);
! 204: sysbus_mmio_map(sysbus, 1, 0x40000000);
! 205: sysbus_connect_irq(sysbus, 0, rc4030[3]);
! 206: {
! 207: /* Simple ROM, so user doesn't have to provide one */
! 208: MemoryRegion *rom_mr = g_new(MemoryRegion, 1);
! 209: memory_region_init_ram(rom_mr, NULL, "g364fb.rom", 0x80000);
! 210: memory_region_set_readonly(rom_mr, true);
! 211: uint8_t *rom = memory_region_get_ram_ptr(rom_mr);
! 212: memory_region_add_subregion(address_space, 0x60000000, rom_mr);
! 213: rom[0] = 0x10; /* Mips G364 */
! 214: }
1.1 root 215: break;
216: case JAZZ_PICA61:
1.1.1.7 ! root 217: isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory());
1.1 root 218: break;
219: default:
220: break;
221: }
222:
223: /* Network controller */
1.1.1.2 root 224: for (n = 0; n < nb_nics; n++) {
225: nd = &nd_table[n];
226: if (!nd->model)
1.1.1.7 ! root 227: nd->model = g_strdup("dp83932");
1.1.1.2 root 228: if (strcmp(nd->model, "dp83932") == 0) {
229: dp83932_init(nd, 0x80001000, 2, rc4030[4],
230: rc4030_opaque, rc4030_dma_memory_rw);
231: break;
232: } else if (strcmp(nd->model, "?") == 0) {
233: fprintf(stderr, "qemu: Supported NICs: dp83932\n");
234: exit(1);
235: } else {
236: fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
237: exit(1);
1.1 root 238: }
239: }
240:
1.1.1.2 root 241: /* SCSI adapter */
242: esp_init(0x80002000, 0,
243: rc4030_dma_read, rc4030_dma_write, dmas[0],
1.1.1.5 root 244: rc4030[5], &esp_reset, &dma_enable);
1.1.1.2 root 245:
1.1 root 246: /* Floppy */
247: if (drive_get_max_bus(IF_FLOPPY) >= MAX_FD) {
248: fprintf(stderr, "qemu: too many floppy drives\n");
249: exit(1);
250: }
251: for (n = 0; n < MAX_FD; n++) {
1.1.1.3 root 252: fds[n] = drive_get(IF_FLOPPY, 0, n);
1.1 root 253: }
1.1.1.3 root 254: fdctrl_init_sysbus(rc4030[1], 0, 0x80003000, fds);
1.1 root 255:
256: /* Real time clock */
1.1.1.4 root 257: rtc_init(1980, NULL);
1.1.1.7 ! root 258: memory_region_init_io(rtc, &rtc_ops, NULL, "rtc", 0x1000);
! 259: memory_region_add_subregion(address_space, 0x80004000, rtc);
1.1 root 260:
261: /* Keyboard (i8042) */
1.1.1.7 ! root 262: i8042_mm_init(rc4030[6], rc4030[7], i8042, 0x1000, 0x1);
! 263: memory_region_add_subregion(address_space, 0x80005000, i8042);
1.1 root 264:
265: /* Serial ports */
1.1.1.4 root 266: if (serial_hds[0]) {
1.1.1.7 ! root 267: serial_mm_init(address_space, 0x80006000, 0, rc4030[8], 8000000/16,
! 268: serial_hds[0], DEVICE_NATIVE_ENDIAN);
1.1.1.4 root 269: }
270: if (serial_hds[1]) {
1.1.1.7 ! root 271: serial_mm_init(address_space, 0x80007000, 0, rc4030[9], 8000000/16,
! 272: serial_hds[1], DEVICE_NATIVE_ENDIAN);
1.1.1.4 root 273: }
1.1 root 274:
275: /* Parallel port */
276: if (parallel_hds[0])
277: parallel_mm_init(0x80008000, 0, rc4030[0], parallel_hds[0]);
278:
279: /* Sound card */
280: /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
1.1.1.5 root 281: audio_init(i8259, NULL);
1.1 root 282:
1.1.1.6 root 283: /* NVRAM */
284: dev = qdev_create(NULL, "ds1225y");
285: qdev_init_nofail(dev);
286: sysbus = sysbus_from_qdev(dev);
287: sysbus_mmio_map(sysbus, 0, 0x80009000);
1.1 root 288:
289: /* LED indicator */
290: jazz_led_init(0x8000f000);
291: }
292:
293: static
1.1.1.2 root 294: void mips_magnum_init (ram_addr_t ram_size,
1.1 root 295: const char *boot_device,
296: const char *kernel_filename, const char *kernel_cmdline,
297: const char *initrd_filename, const char *cpu_model)
298: {
1.1.1.7 ! root 299: mips_jazz_init(get_system_memory(), get_system_io(),
! 300: ram_size, cpu_model, JAZZ_MAGNUM);
1.1 root 301: }
302:
303: static
1.1.1.2 root 304: void mips_pica61_init (ram_addr_t ram_size,
1.1 root 305: const char *boot_device,
306: const char *kernel_filename, const char *kernel_cmdline,
307: const char *initrd_filename, const char *cpu_model)
308: {
1.1.1.7 ! root 309: mips_jazz_init(get_system_memory(), get_system_io(),
! 310: ram_size, cpu_model, JAZZ_PICA61);
1.1 root 311: }
312:
1.1.1.2 root 313: static QEMUMachine mips_magnum_machine = {
1.1 root 314: .name = "magnum",
315: .desc = "MIPS Magnum",
316: .init = mips_magnum_init,
317: .use_scsi = 1,
318: };
319:
1.1.1.2 root 320: static QEMUMachine mips_pica61_machine = {
1.1 root 321: .name = "pica61",
322: .desc = "Acer Pica 61",
323: .init = mips_pica61_init,
324: .use_scsi = 1,
325: };
1.1.1.2 root 326:
327: static void mips_jazz_machine_init(void)
328: {
329: qemu_register_machine(&mips_magnum_machine);
330: qemu_register_machine(&mips_pica61_machine);
331: }
332:
333: machine_init(mips_jazz_machine_init);
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