Diff for /qemu/hw/mips_timer.c between versions 1.1.1.2 and 1.1.1.3

version 1.1.1.2, 2018/04/24 16:48:20 version 1.1.1.3, 2018/04/24 16:52:19
Line 2 Line 2
 #include "mips.h"  #include "mips.h"
 #include "qemu-timer.h"  #include "qemu-timer.h"
   
 void cpu_mips_irqctrl_init (void)  #define TIMER_FREQ      100 * 1000 * 1000
 {  
 }  
   
 /* XXX: do not use a global */  /* XXX: do not use a global */
 uint32_t cpu_mips_get_random (CPUState *env)  uint32_t cpu_mips_get_random (CPUState *env)
 {  {
     static uint32_t seed = 0;      static uint32_t lfsr = 1;
       static uint32_t prev_idx = 0;
     uint32_t idx;      uint32_t idx;
     seed = seed * 314159 + 1;      /* Don't return same value twice, so get another value */
     idx = (seed >> 16) % (env->tlb->nb_tlb - env->CP0_Wired) + env->CP0_Wired;      do {
           lfsr = (lfsr >> 1) ^ (-(lfsr & 1u) & 0xd0000001u);
           idx = lfsr % (env->tlb->nb_tlb - env->CP0_Wired) + env->CP0_Wired;
       } while (idx == prev_idx);
       prev_idx = idx;
     return idx;      return idx;
 }  }
   
Line 24  uint32_t cpu_mips_get_count (CPUState *e Line 27  uint32_t cpu_mips_get_count (CPUState *e
     else      else
         return env->CP0_Count +          return env->CP0_Count +
             (uint32_t)muldiv64(qemu_get_clock(vm_clock),              (uint32_t)muldiv64(qemu_get_clock(vm_clock),
                                100 * 1000 * 1000, ticks_per_sec);                                 TIMER_FREQ, ticks_per_sec);
 }  }
   
 void cpu_mips_store_count (CPUState *env, uint32_t count)  static void cpu_mips_timer_update(CPUState *env)
 {  {
     uint64_t now, next;      uint64_t now, next;
     uint32_t tmp;      uint32_t wait;
     uint32_t compare = env->CP0_Compare;  
   
     tmp = count;  
     if (count == compare)  
         tmp++;  
     now = qemu_get_clock(vm_clock);      now = qemu_get_clock(vm_clock);
     next = now + muldiv64(compare - tmp, ticks_per_sec, 100 * 1000 * 1000);      wait = env->CP0_Compare - env->CP0_Count -
     if (next == now)              (uint32_t)muldiv64(now, TIMER_FREQ, ticks_per_sec);
         next++;      next = now + muldiv64(wait, ticks_per_sec, TIMER_FREQ);
 #if 0  
     if (logfile) {  
         fprintf(logfile, "%s: 0x%08" PRIx64 " %08x %08x => 0x%08" PRIx64 "\n",  
                 __func__, now, count, compare, next - now);  
     }  
 #endif  
     /* Store new count and compare registers */  
     env->CP0_Compare = compare;  
     env->CP0_Count =  
         count - (uint32_t)muldiv64(now, 100 * 1000 * 1000, ticks_per_sec);  
     /* Adjust timer */  
     qemu_mod_timer(env->timer, next);      qemu_mod_timer(env->timer, next);
 }  }
   
 static void cpu_mips_update_count (CPUState *env, uint32_t count)  void cpu_mips_store_count (CPUState *env, uint32_t count)
 {  {
     if (env->CP0_Cause & (1 << CP0Ca_DC))      if (env->CP0_Cause & (1 << CP0Ca_DC))
         return;          env->CP0_Count = count;
       else {
     cpu_mips_store_count(env, count);          /* Store new count register */
           env->CP0_Count =
               count - (uint32_t)muldiv64(qemu_get_clock(vm_clock),
                                          TIMER_FREQ, ticks_per_sec);
           /* Update timer timer */
           cpu_mips_timer_update(env);
       }
 }  }
   
 void cpu_mips_store_compare (CPUState *env, uint32_t value)  void cpu_mips_store_compare (CPUState *env, uint32_t value)
 {  {
     env->CP0_Compare = value;      env->CP0_Compare = value;
     cpu_mips_update_count(env, cpu_mips_get_count(env));      if (!(env->CP0_Cause & (1 << CP0Ca_DC)))
     if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR))          cpu_mips_timer_update(env);
       if (env->insn_flags & ISA_MIPS32R2)
         env->CP0_Cause &= ~(1 << CP0Ca_TI);          env->CP0_Cause &= ~(1 << CP0Ca_TI);
     qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);      qemu_irq_lower(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
 }  }
Line 80  void cpu_mips_stop_count(CPUState *env) Line 75  void cpu_mips_stop_count(CPUState *env)
 {  {
     /* Store the current value */      /* Store the current value */
     env->CP0_Count += (uint32_t)muldiv64(qemu_get_clock(vm_clock),      env->CP0_Count += (uint32_t)muldiv64(qemu_get_clock(vm_clock),
                                          100 * 1000 * 1000, ticks_per_sec);                                           TIMER_FREQ, ticks_per_sec);
 }  }
   
 static void mips_timer_cb (void *opaque)  static void mips_timer_cb (void *opaque)
Line 89  static void mips_timer_cb (void *opaque) Line 84  static void mips_timer_cb (void *opaque)
   
     env = opaque;      env = opaque;
 #if 0  #if 0
     if (logfile) {      qemu_log("%s\n", __func__);
         fprintf(logfile, "%s\n", __func__);  
     }  
 #endif  #endif
   
     if (env->CP0_Cause & (1 << CP0Ca_DC))      if (env->CP0_Cause & (1 << CP0Ca_DC))
         return;          return;
   
     cpu_mips_update_count(env, cpu_mips_get_count(env));      /* ??? This callback should occur when the counter is exactly equal to
     if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR))         the comparator value.  Offset the count by one to avoid immediately
          retriggering the callback before any virtual time has passed.  */
       env->CP0_Count++;
       cpu_mips_timer_update(env);
       env->CP0_Count--;
       if (env->insn_flags & ISA_MIPS32R2)
         env->CP0_Cause |= 1 << CP0Ca_TI;          env->CP0_Cause |= 1 << CP0Ca_TI;
     qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);      qemu_irq_raise(env->irq[(env->CP0_IntCtl >> CP0IntCtl_IPTI) & 0x7]);
 }  }
Line 107  void cpu_mips_clock_init (CPUState *env) Line 105  void cpu_mips_clock_init (CPUState *env)
 {  {
     env->timer = qemu_new_timer(vm_clock, &mips_timer_cb, env);      env->timer = qemu_new_timer(vm_clock, &mips_timer_cb, env);
     env->CP0_Compare = 0;      env->CP0_Compare = 0;
     cpu_mips_update_count(env, 1);      cpu_mips_store_count(env, 1);
 }  }

Removed from v.1.1.1.2  
changed lines
  Added in v.1.1.1.3


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