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1.1 root 1: /*
2: * QEMU PowerPC MPC8544 global util pseudo-device
3: *
4: * Copyright (C) 2011 Freescale Semiconductor, Inc. All rights reserved.
5: *
6: * Author: Alexander Graf, <[email protected]>
7: *
8: * This is free software; you can redistribute it and/or modify
9: * it under the terms of the GNU General Public License as published by
10: * the Free Software Foundation; either version 2 of the License, or
11: * (at your option) any later version.
12: *
13: * *****************************************************************
14: *
15: * The documentation for this device is noted in the MPC8544 documentation,
16: * file name "MPC8544ERM.pdf". You can easily find it on the web.
17: *
18: */
19:
20: #include "hw.h"
21: #include "sysemu.h"
22: #include "sysbus.h"
23:
24: #define MPC8544_GUTS_MMIO_SIZE 0x1000
25: #define MPC8544_GUTS_RSTCR_RESET 0x02
26:
27: #define MPC8544_GUTS_ADDR_PORPLLSR 0x00
28: #define MPC8544_GUTS_ADDR_PORBMSR 0x04
29: #define MPC8544_GUTS_ADDR_PORIMPSCR 0x08
30: #define MPC8544_GUTS_ADDR_PORDEVSR 0x0C
31: #define MPC8544_GUTS_ADDR_PORDBGMSR 0x10
32: #define MPC8544_GUTS_ADDR_PORDEVSR2 0x14
33: #define MPC8544_GUTS_ADDR_GPPORCR 0x20
34: #define MPC8544_GUTS_ADDR_GPIOCR 0x30
35: #define MPC8544_GUTS_ADDR_GPOUTDR 0x40
36: #define MPC8544_GUTS_ADDR_GPINDR 0x50
37: #define MPC8544_GUTS_ADDR_PMUXCR 0x60
38: #define MPC8544_GUTS_ADDR_DEVDISR 0x70
39: #define MPC8544_GUTS_ADDR_POWMGTCSR 0x80
40: #define MPC8544_GUTS_ADDR_MCPSUMR 0x90
41: #define MPC8544_GUTS_ADDR_RSTRSCR 0x94
42: #define MPC8544_GUTS_ADDR_PVR 0xA0
43: #define MPC8544_GUTS_ADDR_SVR 0xA4
44: #define MPC8544_GUTS_ADDR_RSTCR 0xB0
45: #define MPC8544_GUTS_ADDR_IOVSELSR 0xC0
46: #define MPC8544_GUTS_ADDR_DDRCSR 0xB20
47: #define MPC8544_GUTS_ADDR_DDRCDR 0xB24
48: #define MPC8544_GUTS_ADDR_DDRCLKDR 0xB28
49: #define MPC8544_GUTS_ADDR_CLKOCR 0xE00
50: #define MPC8544_GUTS_ADDR_SRDS1CR1 0xF04
51: #define MPC8544_GUTS_ADDR_SRDS2CR1 0xF10
52: #define MPC8544_GUTS_ADDR_SRDS2CR3 0xF18
53:
54: struct GutsState {
55: SysBusDevice busdev;
56: };
57:
58: typedef struct GutsState GutsState;
59:
60: static uint32_t mpc8544_guts_read32(void *opaque, target_phys_addr_t addr)
61: {
62: uint32_t value = 0;
63: CPUState *env = cpu_single_env;
64:
65: addr &= MPC8544_GUTS_MMIO_SIZE - 1;
66: switch (addr) {
67: case MPC8544_GUTS_ADDR_PVR:
68: value = env->spr[SPR_PVR];
69: break;
70: case MPC8544_GUTS_ADDR_SVR:
71: value = env->spr[SPR_E500_SVR];
72: break;
73: default:
74: fprintf(stderr, "guts: Unknown register read: %x\n", (int)addr);
75: break;
76: }
77:
78: return value;
79: }
80:
81: static CPUReadMemoryFunc * const mpc8544_guts_read[] = {
82: NULL,
83: NULL,
84: &mpc8544_guts_read32,
85: };
86:
87: static void mpc8544_guts_write32(void *opaque, target_phys_addr_t addr,
88: uint32_t value)
89: {
90: addr &= MPC8544_GUTS_MMIO_SIZE - 1;
91:
92: switch (addr) {
93: case MPC8544_GUTS_ADDR_RSTCR:
94: if (value & MPC8544_GUTS_RSTCR_RESET) {
95: qemu_system_reset_request();
96: }
97: break;
98: default:
99: fprintf(stderr, "guts: Unknown register write: %x = %x\n",
100: (int)addr, value);
101: break;
102: }
103: }
104:
105: static CPUWriteMemoryFunc * const mpc8544_guts_write[] = {
106: NULL,
107: NULL,
108: &mpc8544_guts_write32,
109: };
110:
111: static int mpc8544_guts_initfn(SysBusDevice *dev)
112: {
113: GutsState *s;
114: int iomem;
115:
116: s = FROM_SYSBUS(GutsState, sysbus_from_qdev(dev));
117:
118: iomem = cpu_register_io_memory(mpc8544_guts_read, mpc8544_guts_write, s,
119: DEVICE_BIG_ENDIAN);
120: sysbus_init_mmio(dev, MPC8544_GUTS_MMIO_SIZE, iomem);
121:
122: return 0;
123: }
124:
125: static SysBusDeviceInfo mpc8544_guts_info = {
126: .init = mpc8544_guts_initfn,
127: .qdev.name = "mpc8544-guts",
128: .qdev.size = sizeof(GutsState),
129: };
130:
131: static void mpc8544_guts_register(void)
132: {
133: sysbus_register_withprop(&mpc8544_guts_info);
134: }
135: device_init(mpc8544_guts_register);
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