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1.1 root 1: /*
2: * QEMU NE2000 emulation
1.1.1.6 root 3: *
1.1 root 4: * Copyright (c) 2003-2004 Fabrice Bellard
1.1.1.6 root 5: *
1.1 root 6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
1.1.1.6 root 24: #include "hw.h"
25: #include "pci.h"
26: #include "net.h"
1.1.1.10 root 27: #include "ne2000.h"
28: #include "loader.h"
1.1 root 29:
30: /* debug NE2000 card */
31: //#define DEBUG_NE2000
32:
33: #define MAX_ETH_FRAME_SIZE 1514
34:
35: #define E8390_CMD 0x00 /* The command register (for all pages) */
36: /* Page 0 register offsets. */
37: #define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */
38: #define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */
39: #define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */
40: #define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */
41: #define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */
42: #define EN0_TSR 0x04 /* Transmit status reg RD */
43: #define EN0_TPSR 0x04 /* Transmit starting page WR */
44: #define EN0_NCR 0x05 /* Number of collision reg RD */
45: #define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */
46: #define EN0_FIFO 0x06 /* FIFO RD */
47: #define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */
48: #define EN0_ISR 0x07 /* Interrupt status reg RD WR */
49: #define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */
50: #define EN0_RSARLO 0x08 /* Remote start address reg 0 */
51: #define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */
52: #define EN0_RSARHI 0x09 /* Remote start address reg 1 */
53: #define EN0_RCNTLO 0x0a /* Remote byte count reg WR */
1.1.1.2 root 54: #define EN0_RTL8029ID0 0x0a /* Realtek ID byte #1 RD */
1.1 root 55: #define EN0_RCNTHI 0x0b /* Remote byte count reg WR */
1.1.1.2 root 56: #define EN0_RTL8029ID1 0x0b /* Realtek ID byte #2 RD */
1.1 root 57: #define EN0_RSR 0x0c /* rx status reg RD */
58: #define EN0_RXCR 0x0c /* RX configuration reg WR */
59: #define EN0_TXCR 0x0d /* TX configuration reg WR */
60: #define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */
61: #define EN0_DCFG 0x0e /* Data configuration reg WR */
62: #define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */
63: #define EN0_IMR 0x0f /* Interrupt mask reg WR */
64: #define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */
65:
66: #define EN1_PHYS 0x11
67: #define EN1_CURPAG 0x17
68: #define EN1_MULT 0x18
69:
70: #define EN2_STARTPG 0x21 /* Starting page of ring bfr RD */
71: #define EN2_STOPPG 0x22 /* Ending page +1 of ring bfr RD */
72:
1.1.1.2 root 73: #define EN3_CONFIG0 0x33
74: #define EN3_CONFIG1 0x34
75: #define EN3_CONFIG2 0x35
76: #define EN3_CONFIG3 0x36
77:
1.1 root 78: /* Register accessed at EN_CMD, the 8390 base addr. */
79: #define E8390_STOP 0x01 /* Stop and reset the chip */
80: #define E8390_START 0x02 /* Start the chip, clear reset */
81: #define E8390_TRANS 0x04 /* Transmit a frame */
82: #define E8390_RREAD 0x08 /* Remote read */
83: #define E8390_RWRITE 0x10 /* Remote write */
84: #define E8390_NODMA 0x20 /* Remote DMA */
85: #define E8390_PAGE0 0x00 /* Select page chip registers */
86: #define E8390_PAGE1 0x40 /* using the two high-order bits */
87: #define E8390_PAGE2 0x80 /* Page 3 is invalid. */
88:
89: /* Bits in EN0_ISR - Interrupt status register */
90: #define ENISR_RX 0x01 /* Receiver, no error */
91: #define ENISR_TX 0x02 /* Transmitter, no error */
92: #define ENISR_RX_ERR 0x04 /* Receiver, with error */
93: #define ENISR_TX_ERR 0x08 /* Transmitter, with error */
94: #define ENISR_OVER 0x10 /* Receiver overwrote the ring */
95: #define ENISR_COUNTERS 0x20 /* Counters need emptying */
96: #define ENISR_RDC 0x40 /* remote dma complete */
97: #define ENISR_RESET 0x80 /* Reset completed */
98: #define ENISR_ALL 0x3f /* Interrupts we will enable */
99:
100: /* Bits in received packet status byte and EN0_RSR*/
101: #define ENRSR_RXOK 0x01 /* Received a good packet */
102: #define ENRSR_CRC 0x02 /* CRC error */
103: #define ENRSR_FAE 0x04 /* frame alignment error */
104: #define ENRSR_FO 0x08 /* FIFO overrun */
105: #define ENRSR_MPA 0x10 /* missed pkt */
106: #define ENRSR_PHY 0x20 /* physical/multicast address */
107: #define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */
108: #define ENRSR_DEF 0x80 /* deferring */
109:
110: /* Transmitted packet status, EN0_TSR. */
111: #define ENTSR_PTX 0x01 /* Packet transmitted without error */
112: #define ENTSR_ND 0x02 /* The transmit wasn't deferred. */
113: #define ENTSR_COL 0x04 /* The transmit collided at least once. */
114: #define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */
115: #define ENTSR_CRS 0x10 /* The carrier sense was lost. */
116: #define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */
117: #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
118: #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */
119:
1.1.1.10 root 120: typedef struct PCINE2000State {
121: PCIDevice dev;
122: NE2000State ne2000;
123: } PCINE2000State;
1.1 root 124:
1.1.1.10 root 125: void ne2000_reset(NE2000State *s)
1.1 root 126: {
127: int i;
128:
129: s->isr = ENISR_RESET;
1.1.1.10 root 130: memcpy(s->mem, &s->c.macaddr, 6);
1.1 root 131: s->mem[14] = 0x57;
132: s->mem[15] = 0x57;
133:
134: /* duplicate prom data */
135: for(i = 15;i >= 0; i--) {
136: s->mem[2 * i] = s->mem[i];
137: s->mem[2 * i + 1] = s->mem[i];
138: }
139: }
140:
141: static void ne2000_update_irq(NE2000State *s)
142: {
143: int isr;
144: isr = (s->isr & s->imr) & 0x7f;
145: #if defined(DEBUG_NE2000)
1.1.1.6 root 146: printf("NE2000: Set IRQ to %d (%02x %02x)\n",
147: isr ? 1 : 0, s->isr, s->imr);
1.1 root 148: #endif
1.1.1.6 root 149: qemu_set_irq(s->irq, (isr != 0));
1.1 root 150: }
151:
1.1.1.2 root 152: #define POLYNOMIAL 0x04c11db6
153:
154: /* From FreeBSD */
155: /* XXX: optimize */
156: static int compute_mcast_idx(const uint8_t *ep)
157: {
158: uint32_t crc;
159: int carry, i, j;
160: uint8_t b;
161:
162: crc = 0xffffffff;
163: for (i = 0; i < 6; i++) {
164: b = *ep++;
165: for (j = 0; j < 8; j++) {
166: carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
167: crc <<= 1;
168: b >>= 1;
169: if (carry)
170: crc = ((crc ^ POLYNOMIAL) | carry);
171: }
172: }
173: return (crc >> 26);
174: }
175:
1.1.1.3 root 176: static int ne2000_buffer_full(NE2000State *s)
1.1 root 177: {
178: int avail, index, boundary;
1.1.1.3 root 179:
1.1 root 180: index = s->curpag << 8;
181: boundary = s->boundary << 8;
1.1.1.6 root 182: if (index < boundary)
1.1 root 183: avail = boundary - index;
184: else
185: avail = (s->stop - s->start) - (index - boundary);
186: if (avail < (MAX_ETH_FRAME_SIZE + 4))
1.1.1.3 root 187: return 1;
188: return 0;
189: }
190:
1.1.1.10 root 191: int ne2000_can_receive(VLANClientState *nc)
1.1.1.3 root 192: {
1.1.1.10 root 193: NE2000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1.1.1.6 root 194:
1.1.1.3 root 195: if (s->cmd & E8390_STOP)
196: return 1;
197: return !ne2000_buffer_full(s);
1.1 root 198: }
199:
200: #define MIN_BUF_SIZE 60
201:
1.1.1.10 root 202: ssize_t ne2000_receive(VLANClientState *nc, const uint8_t *buf, size_t size_)
1.1 root 203: {
1.1.1.10 root 204: NE2000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1.1.1.9 root 205: int size = size_;
1.1 root 206: uint8_t *p;
1.1.1.6 root 207: unsigned int total_len, next, avail, len, index, mcast_idx;
1.1 root 208: uint8_t buf1[60];
1.1.1.6 root 209: static const uint8_t broadcast_macaddr[6] =
1.1.1.2 root 210: { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1.1.1.6 root 211:
1.1 root 212: #if defined(DEBUG_NE2000)
213: printf("NE2000: received len=%d\n", size);
214: #endif
215:
1.1.1.3 root 216: if (s->cmd & E8390_STOP || ne2000_buffer_full(s))
1.1.1.9 root 217: return -1;
1.1.1.6 root 218:
1.1.1.2 root 219: /* XXX: check this */
220: if (s->rxcr & 0x10) {
221: /* promiscuous: receive all */
222: } else {
223: if (!memcmp(buf, broadcast_macaddr, 6)) {
224: /* broadcast address */
225: if (!(s->rxcr & 0x04))
1.1.1.9 root 226: return size;
1.1.1.2 root 227: } else if (buf[0] & 0x01) {
228: /* multicast */
229: if (!(s->rxcr & 0x08))
1.1.1.9 root 230: return size;
1.1.1.2 root 231: mcast_idx = compute_mcast_idx(buf);
232: if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
1.1.1.9 root 233: return size;
1.1.1.2 root 234: } else if (s->mem[0] == buf[0] &&
1.1.1.6 root 235: s->mem[2] == buf[1] &&
236: s->mem[4] == buf[2] &&
237: s->mem[6] == buf[3] &&
238: s->mem[8] == buf[4] &&
1.1.1.2 root 239: s->mem[10] == buf[5]) {
240: /* match */
241: } else {
1.1.1.9 root 242: return size;
1.1.1.2 root 243: }
244: }
245:
246:
1.1 root 247: /* if too small buffer, then expand it */
248: if (size < MIN_BUF_SIZE) {
249: memcpy(buf1, buf, size);
250: memset(buf1 + size, 0, MIN_BUF_SIZE - size);
251: buf = buf1;
252: size = MIN_BUF_SIZE;
253: }
254:
255: index = s->curpag << 8;
256: /* 4 bytes for header */
257: total_len = size + 4;
258: /* address for next packet (4 bytes for CRC) */
259: next = index + ((total_len + 4 + 255) & ~0xff);
260: if (next >= s->stop)
261: next -= (s->stop - s->start);
262: /* prepare packet header */
263: p = s->mem + index;
264: s->rsr = ENRSR_RXOK; /* receive status */
265: /* XXX: check this */
266: if (buf[0] & 0x01)
267: s->rsr |= ENRSR_PHY;
268: p[0] = s->rsr;
269: p[1] = next >> 8;
270: p[2] = total_len;
271: p[3] = total_len >> 8;
272: index += 4;
273:
274: /* write packet data */
275: while (size > 0) {
1.1.1.6 root 276: if (index <= s->stop)
277: avail = s->stop - index;
278: else
279: avail = 0;
1.1 root 280: len = size;
281: if (len > avail)
282: len = avail;
283: memcpy(s->mem + index, buf, len);
284: buf += len;
285: index += len;
286: if (index == s->stop)
287: index = s->start;
288: size -= len;
289: }
290: s->curpag = next >> 8;
291:
1.1.1.5 root 292: /* now we can signal we have received something */
1.1 root 293: s->isr |= ENISR_RX;
294: ne2000_update_irq(s);
1.1.1.9 root 295:
296: return size_;
1.1 root 297: }
298:
1.1.1.10 root 299: void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1.1 root 300: {
301: NE2000State *s = opaque;
302: int offset, page, index;
303:
304: addr &= 0xf;
305: #ifdef DEBUG_NE2000
306: printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
307: #endif
308: if (addr == E8390_CMD) {
309: /* control register */
310: s->cmd = val;
311: if (!(val & E8390_STOP)) { /* START bit makes no sense on RTL8029... */
312: s->isr &= ~ENISR_RESET;
1.1.1.6 root 313: /* test specific case: zero length transfer */
1.1 root 314: if ((val & (E8390_RREAD | E8390_RWRITE)) &&
315: s->rcnt == 0) {
316: s->isr |= ENISR_RDC;
317: ne2000_update_irq(s);
318: }
319: if (val & E8390_TRANS) {
320: index = (s->tpsr << 8);
1.1.1.6 root 321: /* XXX: next 2 lines are a hack to make netware 3.11 work */
1.1 root 322: if (index >= NE2000_PMEM_END)
323: index -= NE2000_PMEM_SIZE;
324: /* fail safe: check range on the transmitted length */
325: if (index + s->tcnt <= NE2000_PMEM_END) {
1.1.1.10 root 326: qemu_send_packet(&s->nic->nc, s->mem + index, s->tcnt);
1.1 root 327: }
1.1.1.6 root 328: /* signal end of transfer */
1.1 root 329: s->tsr = ENTSR_PTX;
330: s->isr |= ENISR_TX;
1.1.1.6 root 331: s->cmd &= ~E8390_TRANS;
1.1 root 332: ne2000_update_irq(s);
333: }
334: }
335: } else {
336: page = s->cmd >> 6;
337: offset = addr | (page << 4);
338: switch(offset) {
339: case EN0_STARTPG:
340: s->start = val << 8;
341: break;
342: case EN0_STOPPG:
343: s->stop = val << 8;
344: break;
345: case EN0_BOUNDARY:
346: s->boundary = val;
347: break;
348: case EN0_IMR:
349: s->imr = val;
350: ne2000_update_irq(s);
351: break;
352: case EN0_TPSR:
353: s->tpsr = val;
354: break;
355: case EN0_TCNTLO:
356: s->tcnt = (s->tcnt & 0xff00) | val;
357: break;
358: case EN0_TCNTHI:
359: s->tcnt = (s->tcnt & 0x00ff) | (val << 8);
360: break;
361: case EN0_RSARLO:
362: s->rsar = (s->rsar & 0xff00) | val;
363: break;
364: case EN0_RSARHI:
365: s->rsar = (s->rsar & 0x00ff) | (val << 8);
366: break;
367: case EN0_RCNTLO:
368: s->rcnt = (s->rcnt & 0xff00) | val;
369: break;
370: case EN0_RCNTHI:
371: s->rcnt = (s->rcnt & 0x00ff) | (val << 8);
372: break;
1.1.1.2 root 373: case EN0_RXCR:
374: s->rxcr = val;
375: break;
1.1 root 376: case EN0_DCFG:
377: s->dcfg = val;
378: break;
379: case EN0_ISR:
380: s->isr &= ~(val & 0x7f);
381: ne2000_update_irq(s);
382: break;
383: case EN1_PHYS ... EN1_PHYS + 5:
384: s->phys[offset - EN1_PHYS] = val;
385: break;
386: case EN1_CURPAG:
387: s->curpag = val;
388: break;
389: case EN1_MULT ... EN1_MULT + 7:
390: s->mult[offset - EN1_MULT] = val;
391: break;
392: }
393: }
394: }
395:
1.1.1.10 root 396: uint32_t ne2000_ioport_read(void *opaque, uint32_t addr)
1.1 root 397: {
398: NE2000State *s = opaque;
399: int offset, page, ret;
400:
401: addr &= 0xf;
402: if (addr == E8390_CMD) {
403: ret = s->cmd;
404: } else {
405: page = s->cmd >> 6;
406: offset = addr | (page << 4);
407: switch(offset) {
408: case EN0_TSR:
409: ret = s->tsr;
410: break;
411: case EN0_BOUNDARY:
412: ret = s->boundary;
413: break;
414: case EN0_ISR:
415: ret = s->isr;
416: break;
417: case EN0_RSARLO:
418: ret = s->rsar & 0x00ff;
419: break;
420: case EN0_RSARHI:
421: ret = s->rsar >> 8;
422: break;
423: case EN1_PHYS ... EN1_PHYS + 5:
424: ret = s->phys[offset - EN1_PHYS];
425: break;
426: case EN1_CURPAG:
427: ret = s->curpag;
428: break;
429: case EN1_MULT ... EN1_MULT + 7:
430: ret = s->mult[offset - EN1_MULT];
431: break;
432: case EN0_RSR:
433: ret = s->rsr;
434: break;
435: case EN2_STARTPG:
436: ret = s->start >> 8;
437: break;
438: case EN2_STOPPG:
439: ret = s->stop >> 8;
440: break;
1.1.1.2 root 441: case EN0_RTL8029ID0:
442: ret = 0x50;
443: break;
444: case EN0_RTL8029ID1:
445: ret = 0x43;
446: break;
447: case EN3_CONFIG0:
448: ret = 0; /* 10baseT media */
449: break;
450: case EN3_CONFIG2:
451: ret = 0x40; /* 10baseT active */
452: break;
453: case EN3_CONFIG3:
454: ret = 0x40; /* Full duplex */
455: break;
1.1 root 456: default:
457: ret = 0x00;
458: break;
459: }
460: }
461: #ifdef DEBUG_NE2000
462: printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
463: #endif
464: return ret;
465: }
466:
1.1.1.6 root 467: static inline void ne2000_mem_writeb(NE2000State *s, uint32_t addr,
1.1 root 468: uint32_t val)
469: {
1.1.1.6 root 470: if (addr < 32 ||
1.1 root 471: (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
472: s->mem[addr] = val;
473: }
474: }
475:
1.1.1.6 root 476: static inline void ne2000_mem_writew(NE2000State *s, uint32_t addr,
1.1 root 477: uint32_t val)
478: {
479: addr &= ~1; /* XXX: check exact behaviour if not even */
1.1.1.6 root 480: if (addr < 32 ||
1.1 root 481: (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
482: *(uint16_t *)(s->mem + addr) = cpu_to_le16(val);
483: }
484: }
485:
1.1.1.6 root 486: static inline void ne2000_mem_writel(NE2000State *s, uint32_t addr,
1.1 root 487: uint32_t val)
488: {
489: addr &= ~1; /* XXX: check exact behaviour if not even */
1.1.1.6 root 490: if (addr < 32 ||
1.1 root 491: (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
492: cpu_to_le32wu((uint32_t *)(s->mem + addr), val);
493: }
494: }
495:
496: static inline uint32_t ne2000_mem_readb(NE2000State *s, uint32_t addr)
497: {
1.1.1.6 root 498: if (addr < 32 ||
1.1 root 499: (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
500: return s->mem[addr];
501: } else {
502: return 0xff;
503: }
504: }
505:
506: static inline uint32_t ne2000_mem_readw(NE2000State *s, uint32_t addr)
507: {
508: addr &= ~1; /* XXX: check exact behaviour if not even */
1.1.1.6 root 509: if (addr < 32 ||
1.1 root 510: (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
511: return le16_to_cpu(*(uint16_t *)(s->mem + addr));
512: } else {
513: return 0xffff;
514: }
515: }
516:
517: static inline uint32_t ne2000_mem_readl(NE2000State *s, uint32_t addr)
518: {
519: addr &= ~1; /* XXX: check exact behaviour if not even */
1.1.1.6 root 520: if (addr < 32 ||
1.1 root 521: (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
522: return le32_to_cpupu((uint32_t *)(s->mem + addr));
523: } else {
524: return 0xffffffff;
525: }
526: }
527:
528: static inline void ne2000_dma_update(NE2000State *s, int len)
529: {
530: s->rsar += len;
531: /* wrap */
532: /* XXX: check what to do if rsar > stop */
533: if (s->rsar == s->stop)
534: s->rsar = s->start;
535:
536: if (s->rcnt <= len) {
537: s->rcnt = 0;
1.1.1.6 root 538: /* signal end of transfer */
1.1 root 539: s->isr |= ENISR_RDC;
540: ne2000_update_irq(s);
541: } else {
542: s->rcnt -= len;
543: }
544: }
545:
1.1.1.10 root 546: void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1.1 root 547: {
548: NE2000State *s = opaque;
549:
550: #ifdef DEBUG_NE2000
551: printf("NE2000: asic write val=0x%04x\n", val);
552: #endif
553: if (s->rcnt == 0)
554: return;
555: if (s->dcfg & 0x01) {
556: /* 16 bit access */
557: ne2000_mem_writew(s, s->rsar, val);
558: ne2000_dma_update(s, 2);
559: } else {
560: /* 8 bit access */
561: ne2000_mem_writeb(s, s->rsar, val);
562: ne2000_dma_update(s, 1);
563: }
564: }
565:
1.1.1.10 root 566: uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr)
1.1 root 567: {
568: NE2000State *s = opaque;
569: int ret;
570:
571: if (s->dcfg & 0x01) {
572: /* 16 bit access */
573: ret = ne2000_mem_readw(s, s->rsar);
574: ne2000_dma_update(s, 2);
575: } else {
576: /* 8 bit access */
577: ret = ne2000_mem_readb(s, s->rsar);
578: ne2000_dma_update(s, 1);
579: }
580: #ifdef DEBUG_NE2000
581: printf("NE2000: asic read val=0x%04x\n", ret);
582: #endif
583: return ret;
584: }
585:
586: static void ne2000_asic_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
587: {
588: NE2000State *s = opaque;
589:
590: #ifdef DEBUG_NE2000
591: printf("NE2000: asic writel val=0x%04x\n", val);
592: #endif
593: if (s->rcnt == 0)
594: return;
595: /* 32 bit access */
596: ne2000_mem_writel(s, s->rsar, val);
597: ne2000_dma_update(s, 4);
598: }
599:
600: static uint32_t ne2000_asic_ioport_readl(void *opaque, uint32_t addr)
601: {
602: NE2000State *s = opaque;
603: int ret;
604:
605: /* 32 bit access */
606: ret = ne2000_mem_readl(s, s->rsar);
607: ne2000_dma_update(s, 4);
608: #ifdef DEBUG_NE2000
609: printf("NE2000: asic readl val=0x%04x\n", ret);
610: #endif
611: return ret;
612: }
613:
1.1.1.10 root 614: void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1.1 root 615: {
616: /* nothing to do (end of reset pulse) */
617: }
618:
1.1.1.10 root 619: uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr)
1.1 root 620: {
621: NE2000State *s = opaque;
622: ne2000_reset(s);
623: return 0;
624: }
625:
1.1.1.10 root 626: static int ne2000_post_load(void* opaque, int version_id)
1.1 root 627: {
1.1.1.10 root 628: NE2000State* s = opaque;
1.1.1.8 root 629:
1.1.1.10 root 630: if (version_id < 2) {
631: s->rxcr = 0x0c;
632: }
633: return 0;
1.1.1.8 root 634: }
635:
1.1.1.10 root 636: const VMStateDescription vmstate_ne2000 = {
637: .name = "ne2000",
638: .version_id = 2,
639: .minimum_version_id = 0,
640: .minimum_version_id_old = 0,
641: .post_load = ne2000_post_load,
642: .fields = (VMStateField []) {
643: VMSTATE_UINT8_V(rxcr, NE2000State, 2),
644: VMSTATE_UINT8(cmd, NE2000State),
645: VMSTATE_UINT32(start, NE2000State),
646: VMSTATE_UINT32(stop, NE2000State),
647: VMSTATE_UINT8(boundary, NE2000State),
648: VMSTATE_UINT8(tsr, NE2000State),
649: VMSTATE_UINT8(tpsr, NE2000State),
650: VMSTATE_UINT16(tcnt, NE2000State),
651: VMSTATE_UINT16(rcnt, NE2000State),
652: VMSTATE_UINT32(rsar, NE2000State),
653: VMSTATE_UINT8(rsr, NE2000State),
654: VMSTATE_UINT8(isr, NE2000State),
655: VMSTATE_UINT8(dcfg, NE2000State),
656: VMSTATE_UINT8(imr, NE2000State),
657: VMSTATE_BUFFER(phys, NE2000State),
658: VMSTATE_UINT8(curpag, NE2000State),
659: VMSTATE_BUFFER(mult, NE2000State),
660: VMSTATE_UNUSED(4), /* was irq */
661: VMSTATE_BUFFER(mem, NE2000State),
662: VMSTATE_END_OF_LIST()
663: }
664: };
1.1.1.6 root 665:
1.1.1.10 root 666: static const VMStateDescription vmstate_pci_ne2000 = {
667: .name = "ne2000",
668: .version_id = 3,
669: .minimum_version_id = 3,
670: .minimum_version_id_old = 3,
671: .fields = (VMStateField []) {
672: VMSTATE_PCI_DEVICE(dev, PCINE2000State),
673: VMSTATE_STRUCT(ne2000, PCINE2000State, 0, vmstate_ne2000, NE2000State),
674: VMSTATE_END_OF_LIST()
675: }
676: };
1.1 root 677:
678: /***********************************************************/
679: /* PCI NE2000 definitions */
680:
1.1.1.6 root 681: static void ne2000_map(PCIDevice *pci_dev, int region_num,
1.1.1.10 root 682: pcibus_t addr, pcibus_t size, int type)
1.1 root 683: {
1.1.1.10 root 684: PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev);
1.1 root 685: NE2000State *s = &d->ne2000;
686:
687: register_ioport_write(addr, 16, 1, ne2000_ioport_write, s);
688: register_ioport_read(addr, 16, 1, ne2000_ioport_read, s);
689:
690: register_ioport_write(addr + 0x10, 1, 1, ne2000_asic_ioport_write, s);
691: register_ioport_read(addr + 0x10, 1, 1, ne2000_asic_ioport_read, s);
692: register_ioport_write(addr + 0x10, 2, 2, ne2000_asic_ioport_write, s);
693: register_ioport_read(addr + 0x10, 2, 2, ne2000_asic_ioport_read, s);
694: register_ioport_write(addr + 0x10, 4, 4, ne2000_asic_ioport_writel, s);
695: register_ioport_read(addr + 0x10, 4, 4, ne2000_asic_ioport_readl, s);
696:
697: register_ioport_write(addr + 0x1f, 1, 1, ne2000_reset_ioport_write, s);
698: register_ioport_read(addr + 0x1f, 1, 1, ne2000_reset_ioport_read, s);
699: }
700:
1.1.1.10 root 701: static void ne2000_cleanup(VLANClientState *nc)
1.1.1.8 root 702: {
1.1.1.10 root 703: NE2000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1.1.1.8 root 704:
1.1.1.10 root 705: s->nic = NULL;
1.1.1.8 root 706: }
707:
1.1.1.10 root 708: static NetClientInfo net_ne2000_info = {
709: .type = NET_CLIENT_TYPE_NIC,
710: .size = sizeof(NICState),
711: .can_receive = ne2000_can_receive,
712: .receive = ne2000_receive,
713: .cleanup = ne2000_cleanup,
714: };
715:
716: static int pci_ne2000_init(PCIDevice *pci_dev)
1.1 root 717: {
1.1.1.10 root 718: PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev);
1.1 root 719: NE2000State *s;
720: uint8_t *pci_conf;
1.1.1.6 root 721:
1.1 root 722: pci_conf = d->dev.config;
1.1.1.7 root 723: pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REALTEK);
1.1.1.9 root 724: pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_REALTEK_8029);
1.1.1.7 root 725: pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
1.1.1.11! root 726: /* TODO: RST# value should be 0. PCI spec 6.2.4 */
! 727: pci_conf[PCI_INTERRUPT_PIN] = 1; // interrupt pin 0
1.1.1.6 root 728:
1.1.1.9 root 729: pci_register_bar(&d->dev, 0, 0x100,
1.1.1.10 root 730: PCI_BASE_ADDRESS_SPACE_IO, ne2000_map);
1.1 root 731: s = &d->ne2000;
1.1.1.6 root 732: s->irq = d->dev.irq[0];
1.1.1.10 root 733:
734: qemu_macaddr_default_if_unset(&s->c.macaddr);
1.1 root 735: ne2000_reset(s);
1.1.1.7 root 736:
1.1.1.10 root 737: s->nic = qemu_new_nic(&net_ne2000_info, &s->c,
738: pci_dev->qdev.info->name, pci_dev->qdev.id, s);
739: qemu_format_nic_info_str(&s->nic->nc, s->c.macaddr.a);
740:
741: if (!pci_dev->qdev.hotplugged) {
742: static int loaded = 0;
743: if (!loaded) {
744: rom_add_option("pxe-ne2k_pci.bin");
745: loaded = 1;
746: }
747: }
1.1 root 748:
1.1.1.10 root 749: return 0;
750: }
751:
752: static int pci_ne2000_exit(PCIDevice *pci_dev)
753: {
754: PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev);
755: NE2000State *s = &d->ne2000;
756:
757: qemu_del_vlan_client(&s->nic->nc);
758: return 0;
1.1.1.9 root 759: }
1.1.1.6 root 760:
1.1.1.9 root 761: static PCIDeviceInfo ne2000_info = {
1.1.1.10 root 762: .qdev.name = "ne2k_pci",
763: .qdev.size = sizeof(PCINE2000State),
764: .qdev.vmsd = &vmstate_pci_ne2000,
765: .init = pci_ne2000_init,
766: .exit = pci_ne2000_exit,
767: .qdev.props = (Property[]) {
768: DEFINE_NIC_PROPERTIES(PCINE2000State, ne2000.c),
769: DEFINE_PROP_END_OF_LIST(),
770: }
1.1.1.9 root 771: };
772:
773: static void ne2000_register_devices(void)
774: {
775: pci_qdev_register(&ne2000_info);
1.1 root 776: }
1.1.1.9 root 777:
778: device_init(ne2000_register_devices)
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