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1.1 root 1: /*
2: * QEMU NE2000 emulation
1.1.1.6 root 3: *
1.1 root 4: * Copyright (c) 2003-2004 Fabrice Bellard
1.1.1.6 root 5: *
1.1 root 6: * Permission is hereby granted, free of charge, to any person obtaining a copy
7: * of this software and associated documentation files (the "Software"), to deal
8: * in the Software without restriction, including without limitation the rights
9: * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10: * copies of the Software, and to permit persons to whom the Software is
11: * furnished to do so, subject to the following conditions:
12: *
13: * The above copyright notice and this permission notice shall be included in
14: * all copies or substantial portions of the Software.
15: *
16: * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17: * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18: * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19: * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20: * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21: * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22: * THE SOFTWARE.
23: */
1.1.1.6 root 24: #include "hw.h"
25: #include "pci.h"
26: #include "net.h"
1.1.1.10 root 27: #include "ne2000.h"
28: #include "loader.h"
1.1.1.12 root 29: #include "sysemu.h"
1.1 root 30:
31: /* debug NE2000 card */
32: //#define DEBUG_NE2000
33:
34: #define MAX_ETH_FRAME_SIZE 1514
35:
36: #define E8390_CMD 0x00 /* The command register (for all pages) */
37: /* Page 0 register offsets. */
38: #define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */
39: #define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */
40: #define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */
41: #define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */
42: #define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */
43: #define EN0_TSR 0x04 /* Transmit status reg RD */
44: #define EN0_TPSR 0x04 /* Transmit starting page WR */
45: #define EN0_NCR 0x05 /* Number of collision reg RD */
46: #define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */
47: #define EN0_FIFO 0x06 /* FIFO RD */
48: #define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */
49: #define EN0_ISR 0x07 /* Interrupt status reg RD WR */
50: #define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */
51: #define EN0_RSARLO 0x08 /* Remote start address reg 0 */
52: #define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */
53: #define EN0_RSARHI 0x09 /* Remote start address reg 1 */
54: #define EN0_RCNTLO 0x0a /* Remote byte count reg WR */
1.1.1.2 root 55: #define EN0_RTL8029ID0 0x0a /* Realtek ID byte #1 RD */
1.1 root 56: #define EN0_RCNTHI 0x0b /* Remote byte count reg WR */
1.1.1.2 root 57: #define EN0_RTL8029ID1 0x0b /* Realtek ID byte #2 RD */
1.1 root 58: #define EN0_RSR 0x0c /* rx status reg RD */
59: #define EN0_RXCR 0x0c /* RX configuration reg WR */
60: #define EN0_TXCR 0x0d /* TX configuration reg WR */
61: #define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */
62: #define EN0_DCFG 0x0e /* Data configuration reg WR */
63: #define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */
64: #define EN0_IMR 0x0f /* Interrupt mask reg WR */
65: #define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */
66:
67: #define EN1_PHYS 0x11
68: #define EN1_CURPAG 0x17
69: #define EN1_MULT 0x18
70:
71: #define EN2_STARTPG 0x21 /* Starting page of ring bfr RD */
72: #define EN2_STOPPG 0x22 /* Ending page +1 of ring bfr RD */
73:
1.1.1.2 root 74: #define EN3_CONFIG0 0x33
75: #define EN3_CONFIG1 0x34
76: #define EN3_CONFIG2 0x35
77: #define EN3_CONFIG3 0x36
78:
1.1 root 79: /* Register accessed at EN_CMD, the 8390 base addr. */
80: #define E8390_STOP 0x01 /* Stop and reset the chip */
81: #define E8390_START 0x02 /* Start the chip, clear reset */
82: #define E8390_TRANS 0x04 /* Transmit a frame */
83: #define E8390_RREAD 0x08 /* Remote read */
84: #define E8390_RWRITE 0x10 /* Remote write */
85: #define E8390_NODMA 0x20 /* Remote DMA */
86: #define E8390_PAGE0 0x00 /* Select page chip registers */
87: #define E8390_PAGE1 0x40 /* using the two high-order bits */
88: #define E8390_PAGE2 0x80 /* Page 3 is invalid. */
89:
90: /* Bits in EN0_ISR - Interrupt status register */
91: #define ENISR_RX 0x01 /* Receiver, no error */
92: #define ENISR_TX 0x02 /* Transmitter, no error */
93: #define ENISR_RX_ERR 0x04 /* Receiver, with error */
94: #define ENISR_TX_ERR 0x08 /* Transmitter, with error */
95: #define ENISR_OVER 0x10 /* Receiver overwrote the ring */
96: #define ENISR_COUNTERS 0x20 /* Counters need emptying */
97: #define ENISR_RDC 0x40 /* remote dma complete */
98: #define ENISR_RESET 0x80 /* Reset completed */
99: #define ENISR_ALL 0x3f /* Interrupts we will enable */
100:
101: /* Bits in received packet status byte and EN0_RSR*/
102: #define ENRSR_RXOK 0x01 /* Received a good packet */
103: #define ENRSR_CRC 0x02 /* CRC error */
104: #define ENRSR_FAE 0x04 /* frame alignment error */
105: #define ENRSR_FO 0x08 /* FIFO overrun */
106: #define ENRSR_MPA 0x10 /* missed pkt */
107: #define ENRSR_PHY 0x20 /* physical/multicast address */
108: #define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */
109: #define ENRSR_DEF 0x80 /* deferring */
110:
111: /* Transmitted packet status, EN0_TSR. */
112: #define ENTSR_PTX 0x01 /* Packet transmitted without error */
113: #define ENTSR_ND 0x02 /* The transmit wasn't deferred. */
114: #define ENTSR_COL 0x04 /* The transmit collided at least once. */
115: #define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */
116: #define ENTSR_CRS 0x10 /* The carrier sense was lost. */
117: #define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */
118: #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
119: #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */
120:
1.1.1.10 root 121: typedef struct PCINE2000State {
122: PCIDevice dev;
123: NE2000State ne2000;
124: } PCINE2000State;
1.1 root 125:
1.1.1.10 root 126: void ne2000_reset(NE2000State *s)
1.1 root 127: {
128: int i;
129:
130: s->isr = ENISR_RESET;
1.1.1.10 root 131: memcpy(s->mem, &s->c.macaddr, 6);
1.1 root 132: s->mem[14] = 0x57;
133: s->mem[15] = 0x57;
134:
135: /* duplicate prom data */
136: for(i = 15;i >= 0; i--) {
137: s->mem[2 * i] = s->mem[i];
138: s->mem[2 * i + 1] = s->mem[i];
139: }
140: }
141:
142: static void ne2000_update_irq(NE2000State *s)
143: {
144: int isr;
145: isr = (s->isr & s->imr) & 0x7f;
146: #if defined(DEBUG_NE2000)
1.1.1.6 root 147: printf("NE2000: Set IRQ to %d (%02x %02x)\n",
148: isr ? 1 : 0, s->isr, s->imr);
1.1 root 149: #endif
1.1.1.6 root 150: qemu_set_irq(s->irq, (isr != 0));
1.1 root 151: }
152:
1.1.1.2 root 153: #define POLYNOMIAL 0x04c11db6
154:
155: /* From FreeBSD */
156: /* XXX: optimize */
157: static int compute_mcast_idx(const uint8_t *ep)
158: {
159: uint32_t crc;
160: int carry, i, j;
161: uint8_t b;
162:
163: crc = 0xffffffff;
164: for (i = 0; i < 6; i++) {
165: b = *ep++;
166: for (j = 0; j < 8; j++) {
167: carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
168: crc <<= 1;
169: b >>= 1;
170: if (carry)
171: crc = ((crc ^ POLYNOMIAL) | carry);
172: }
173: }
174: return (crc >> 26);
175: }
176:
1.1.1.3 root 177: static int ne2000_buffer_full(NE2000State *s)
1.1 root 178: {
179: int avail, index, boundary;
1.1.1.3 root 180:
1.1 root 181: index = s->curpag << 8;
182: boundary = s->boundary << 8;
1.1.1.6 root 183: if (index < boundary)
1.1 root 184: avail = boundary - index;
185: else
186: avail = (s->stop - s->start) - (index - boundary);
187: if (avail < (MAX_ETH_FRAME_SIZE + 4))
1.1.1.3 root 188: return 1;
189: return 0;
190: }
191:
1.1.1.10 root 192: int ne2000_can_receive(VLANClientState *nc)
1.1.1.3 root 193: {
1.1.1.10 root 194: NE2000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1.1.1.6 root 195:
1.1.1.3 root 196: if (s->cmd & E8390_STOP)
197: return 1;
198: return !ne2000_buffer_full(s);
1.1 root 199: }
200:
201: #define MIN_BUF_SIZE 60
202:
1.1.1.10 root 203: ssize_t ne2000_receive(VLANClientState *nc, const uint8_t *buf, size_t size_)
1.1 root 204: {
1.1.1.10 root 205: NE2000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1.1.1.9 root 206: int size = size_;
1.1 root 207: uint8_t *p;
1.1.1.6 root 208: unsigned int total_len, next, avail, len, index, mcast_idx;
1.1 root 209: uint8_t buf1[60];
1.1.1.6 root 210: static const uint8_t broadcast_macaddr[6] =
1.1.1.2 root 211: { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1.1.1.6 root 212:
1.1 root 213: #if defined(DEBUG_NE2000)
214: printf("NE2000: received len=%d\n", size);
215: #endif
216:
1.1.1.3 root 217: if (s->cmd & E8390_STOP || ne2000_buffer_full(s))
1.1.1.9 root 218: return -1;
1.1.1.6 root 219:
1.1.1.2 root 220: /* XXX: check this */
221: if (s->rxcr & 0x10) {
222: /* promiscuous: receive all */
223: } else {
224: if (!memcmp(buf, broadcast_macaddr, 6)) {
225: /* broadcast address */
226: if (!(s->rxcr & 0x04))
1.1.1.9 root 227: return size;
1.1.1.2 root 228: } else if (buf[0] & 0x01) {
229: /* multicast */
230: if (!(s->rxcr & 0x08))
1.1.1.9 root 231: return size;
1.1.1.2 root 232: mcast_idx = compute_mcast_idx(buf);
233: if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
1.1.1.9 root 234: return size;
1.1.1.2 root 235: } else if (s->mem[0] == buf[0] &&
1.1.1.6 root 236: s->mem[2] == buf[1] &&
237: s->mem[4] == buf[2] &&
238: s->mem[6] == buf[3] &&
239: s->mem[8] == buf[4] &&
1.1.1.2 root 240: s->mem[10] == buf[5]) {
241: /* match */
242: } else {
1.1.1.9 root 243: return size;
1.1.1.2 root 244: }
245: }
246:
247:
1.1 root 248: /* if too small buffer, then expand it */
249: if (size < MIN_BUF_SIZE) {
250: memcpy(buf1, buf, size);
251: memset(buf1 + size, 0, MIN_BUF_SIZE - size);
252: buf = buf1;
253: size = MIN_BUF_SIZE;
254: }
255:
256: index = s->curpag << 8;
257: /* 4 bytes for header */
258: total_len = size + 4;
259: /* address for next packet (4 bytes for CRC) */
260: next = index + ((total_len + 4 + 255) & ~0xff);
261: if (next >= s->stop)
262: next -= (s->stop - s->start);
263: /* prepare packet header */
264: p = s->mem + index;
265: s->rsr = ENRSR_RXOK; /* receive status */
266: /* XXX: check this */
267: if (buf[0] & 0x01)
268: s->rsr |= ENRSR_PHY;
269: p[0] = s->rsr;
270: p[1] = next >> 8;
271: p[2] = total_len;
272: p[3] = total_len >> 8;
273: index += 4;
274:
275: /* write packet data */
276: while (size > 0) {
1.1.1.6 root 277: if (index <= s->stop)
278: avail = s->stop - index;
279: else
280: avail = 0;
1.1 root 281: len = size;
282: if (len > avail)
283: len = avail;
284: memcpy(s->mem + index, buf, len);
285: buf += len;
286: index += len;
287: if (index == s->stop)
288: index = s->start;
289: size -= len;
290: }
291: s->curpag = next >> 8;
292:
1.1.1.5 root 293: /* now we can signal we have received something */
1.1 root 294: s->isr |= ENISR_RX;
295: ne2000_update_irq(s);
1.1.1.9 root 296:
297: return size_;
1.1 root 298: }
299:
1.1.1.14! root 300: static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1.1 root 301: {
302: NE2000State *s = opaque;
303: int offset, page, index;
304:
305: addr &= 0xf;
306: #ifdef DEBUG_NE2000
307: printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
308: #endif
309: if (addr == E8390_CMD) {
310: /* control register */
311: s->cmd = val;
312: if (!(val & E8390_STOP)) { /* START bit makes no sense on RTL8029... */
313: s->isr &= ~ENISR_RESET;
1.1.1.6 root 314: /* test specific case: zero length transfer */
1.1 root 315: if ((val & (E8390_RREAD | E8390_RWRITE)) &&
316: s->rcnt == 0) {
317: s->isr |= ENISR_RDC;
318: ne2000_update_irq(s);
319: }
320: if (val & E8390_TRANS) {
321: index = (s->tpsr << 8);
1.1.1.6 root 322: /* XXX: next 2 lines are a hack to make netware 3.11 work */
1.1 root 323: if (index >= NE2000_PMEM_END)
324: index -= NE2000_PMEM_SIZE;
325: /* fail safe: check range on the transmitted length */
326: if (index + s->tcnt <= NE2000_PMEM_END) {
1.1.1.10 root 327: qemu_send_packet(&s->nic->nc, s->mem + index, s->tcnt);
1.1 root 328: }
1.1.1.6 root 329: /* signal end of transfer */
1.1 root 330: s->tsr = ENTSR_PTX;
331: s->isr |= ENISR_TX;
1.1.1.6 root 332: s->cmd &= ~E8390_TRANS;
1.1 root 333: ne2000_update_irq(s);
334: }
335: }
336: } else {
337: page = s->cmd >> 6;
338: offset = addr | (page << 4);
339: switch(offset) {
340: case EN0_STARTPG:
341: s->start = val << 8;
342: break;
343: case EN0_STOPPG:
344: s->stop = val << 8;
345: break;
346: case EN0_BOUNDARY:
347: s->boundary = val;
348: break;
349: case EN0_IMR:
350: s->imr = val;
351: ne2000_update_irq(s);
352: break;
353: case EN0_TPSR:
354: s->tpsr = val;
355: break;
356: case EN0_TCNTLO:
357: s->tcnt = (s->tcnt & 0xff00) | val;
358: break;
359: case EN0_TCNTHI:
360: s->tcnt = (s->tcnt & 0x00ff) | (val << 8);
361: break;
362: case EN0_RSARLO:
363: s->rsar = (s->rsar & 0xff00) | val;
364: break;
365: case EN0_RSARHI:
366: s->rsar = (s->rsar & 0x00ff) | (val << 8);
367: break;
368: case EN0_RCNTLO:
369: s->rcnt = (s->rcnt & 0xff00) | val;
370: break;
371: case EN0_RCNTHI:
372: s->rcnt = (s->rcnt & 0x00ff) | (val << 8);
373: break;
1.1.1.2 root 374: case EN0_RXCR:
375: s->rxcr = val;
376: break;
1.1 root 377: case EN0_DCFG:
378: s->dcfg = val;
379: break;
380: case EN0_ISR:
381: s->isr &= ~(val & 0x7f);
382: ne2000_update_irq(s);
383: break;
384: case EN1_PHYS ... EN1_PHYS + 5:
385: s->phys[offset - EN1_PHYS] = val;
386: break;
387: case EN1_CURPAG:
388: s->curpag = val;
389: break;
390: case EN1_MULT ... EN1_MULT + 7:
391: s->mult[offset - EN1_MULT] = val;
392: break;
393: }
394: }
395: }
396:
1.1.1.14! root 397: static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr)
1.1 root 398: {
399: NE2000State *s = opaque;
400: int offset, page, ret;
401:
402: addr &= 0xf;
403: if (addr == E8390_CMD) {
404: ret = s->cmd;
405: } else {
406: page = s->cmd >> 6;
407: offset = addr | (page << 4);
408: switch(offset) {
409: case EN0_TSR:
410: ret = s->tsr;
411: break;
412: case EN0_BOUNDARY:
413: ret = s->boundary;
414: break;
415: case EN0_ISR:
416: ret = s->isr;
417: break;
418: case EN0_RSARLO:
419: ret = s->rsar & 0x00ff;
420: break;
421: case EN0_RSARHI:
422: ret = s->rsar >> 8;
423: break;
424: case EN1_PHYS ... EN1_PHYS + 5:
425: ret = s->phys[offset - EN1_PHYS];
426: break;
427: case EN1_CURPAG:
428: ret = s->curpag;
429: break;
430: case EN1_MULT ... EN1_MULT + 7:
431: ret = s->mult[offset - EN1_MULT];
432: break;
433: case EN0_RSR:
434: ret = s->rsr;
435: break;
436: case EN2_STARTPG:
437: ret = s->start >> 8;
438: break;
439: case EN2_STOPPG:
440: ret = s->stop >> 8;
441: break;
1.1.1.2 root 442: case EN0_RTL8029ID0:
443: ret = 0x50;
444: break;
445: case EN0_RTL8029ID1:
446: ret = 0x43;
447: break;
448: case EN3_CONFIG0:
449: ret = 0; /* 10baseT media */
450: break;
451: case EN3_CONFIG2:
452: ret = 0x40; /* 10baseT active */
453: break;
454: case EN3_CONFIG3:
455: ret = 0x40; /* Full duplex */
456: break;
1.1 root 457: default:
458: ret = 0x00;
459: break;
460: }
461: }
462: #ifdef DEBUG_NE2000
463: printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
464: #endif
465: return ret;
466: }
467:
1.1.1.6 root 468: static inline void ne2000_mem_writeb(NE2000State *s, uint32_t addr,
1.1 root 469: uint32_t val)
470: {
1.1.1.6 root 471: if (addr < 32 ||
1.1 root 472: (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
473: s->mem[addr] = val;
474: }
475: }
476:
1.1.1.6 root 477: static inline void ne2000_mem_writew(NE2000State *s, uint32_t addr,
1.1 root 478: uint32_t val)
479: {
480: addr &= ~1; /* XXX: check exact behaviour if not even */
1.1.1.6 root 481: if (addr < 32 ||
1.1 root 482: (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
483: *(uint16_t *)(s->mem + addr) = cpu_to_le16(val);
484: }
485: }
486:
1.1.1.6 root 487: static inline void ne2000_mem_writel(NE2000State *s, uint32_t addr,
1.1 root 488: uint32_t val)
489: {
490: addr &= ~1; /* XXX: check exact behaviour if not even */
1.1.1.6 root 491: if (addr < 32 ||
1.1 root 492: (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
493: cpu_to_le32wu((uint32_t *)(s->mem + addr), val);
494: }
495: }
496:
497: static inline uint32_t ne2000_mem_readb(NE2000State *s, uint32_t addr)
498: {
1.1.1.6 root 499: if (addr < 32 ||
1.1 root 500: (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
501: return s->mem[addr];
502: } else {
503: return 0xff;
504: }
505: }
506:
507: static inline uint32_t ne2000_mem_readw(NE2000State *s, uint32_t addr)
508: {
509: addr &= ~1; /* XXX: check exact behaviour if not even */
1.1.1.6 root 510: if (addr < 32 ||
1.1 root 511: (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
512: return le16_to_cpu(*(uint16_t *)(s->mem + addr));
513: } else {
514: return 0xffff;
515: }
516: }
517:
518: static inline uint32_t ne2000_mem_readl(NE2000State *s, uint32_t addr)
519: {
520: addr &= ~1; /* XXX: check exact behaviour if not even */
1.1.1.6 root 521: if (addr < 32 ||
1.1 root 522: (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
523: return le32_to_cpupu((uint32_t *)(s->mem + addr));
524: } else {
525: return 0xffffffff;
526: }
527: }
528:
529: static inline void ne2000_dma_update(NE2000State *s, int len)
530: {
531: s->rsar += len;
532: /* wrap */
533: /* XXX: check what to do if rsar > stop */
534: if (s->rsar == s->stop)
535: s->rsar = s->start;
536:
537: if (s->rcnt <= len) {
538: s->rcnt = 0;
1.1.1.6 root 539: /* signal end of transfer */
1.1 root 540: s->isr |= ENISR_RDC;
541: ne2000_update_irq(s);
542: } else {
543: s->rcnt -= len;
544: }
545: }
546:
1.1.1.14! root 547: static void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1.1 root 548: {
549: NE2000State *s = opaque;
550:
551: #ifdef DEBUG_NE2000
552: printf("NE2000: asic write val=0x%04x\n", val);
553: #endif
554: if (s->rcnt == 0)
555: return;
556: if (s->dcfg & 0x01) {
557: /* 16 bit access */
558: ne2000_mem_writew(s, s->rsar, val);
559: ne2000_dma_update(s, 2);
560: } else {
561: /* 8 bit access */
562: ne2000_mem_writeb(s, s->rsar, val);
563: ne2000_dma_update(s, 1);
564: }
565: }
566:
1.1.1.14! root 567: static uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr)
1.1 root 568: {
569: NE2000State *s = opaque;
570: int ret;
571:
572: if (s->dcfg & 0x01) {
573: /* 16 bit access */
574: ret = ne2000_mem_readw(s, s->rsar);
575: ne2000_dma_update(s, 2);
576: } else {
577: /* 8 bit access */
578: ret = ne2000_mem_readb(s, s->rsar);
579: ne2000_dma_update(s, 1);
580: }
581: #ifdef DEBUG_NE2000
582: printf("NE2000: asic read val=0x%04x\n", ret);
583: #endif
584: return ret;
585: }
586:
587: static void ne2000_asic_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
588: {
589: NE2000State *s = opaque;
590:
591: #ifdef DEBUG_NE2000
592: printf("NE2000: asic writel val=0x%04x\n", val);
593: #endif
594: if (s->rcnt == 0)
595: return;
596: /* 32 bit access */
597: ne2000_mem_writel(s, s->rsar, val);
598: ne2000_dma_update(s, 4);
599: }
600:
601: static uint32_t ne2000_asic_ioport_readl(void *opaque, uint32_t addr)
602: {
603: NE2000State *s = opaque;
604: int ret;
605:
606: /* 32 bit access */
607: ret = ne2000_mem_readl(s, s->rsar);
608: ne2000_dma_update(s, 4);
609: #ifdef DEBUG_NE2000
610: printf("NE2000: asic readl val=0x%04x\n", ret);
611: #endif
612: return ret;
613: }
614:
1.1.1.14! root 615: static void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1.1 root 616: {
617: /* nothing to do (end of reset pulse) */
618: }
619:
1.1.1.14! root 620: static uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr)
1.1 root 621: {
622: NE2000State *s = opaque;
623: ne2000_reset(s);
624: return 0;
625: }
626:
1.1.1.10 root 627: static int ne2000_post_load(void* opaque, int version_id)
1.1 root 628: {
1.1.1.10 root 629: NE2000State* s = opaque;
1.1.1.8 root 630:
1.1.1.10 root 631: if (version_id < 2) {
632: s->rxcr = 0x0c;
633: }
634: return 0;
1.1.1.8 root 635: }
636:
1.1.1.10 root 637: const VMStateDescription vmstate_ne2000 = {
638: .name = "ne2000",
639: .version_id = 2,
640: .minimum_version_id = 0,
641: .minimum_version_id_old = 0,
642: .post_load = ne2000_post_load,
643: .fields = (VMStateField []) {
644: VMSTATE_UINT8_V(rxcr, NE2000State, 2),
645: VMSTATE_UINT8(cmd, NE2000State),
646: VMSTATE_UINT32(start, NE2000State),
647: VMSTATE_UINT32(stop, NE2000State),
648: VMSTATE_UINT8(boundary, NE2000State),
649: VMSTATE_UINT8(tsr, NE2000State),
650: VMSTATE_UINT8(tpsr, NE2000State),
651: VMSTATE_UINT16(tcnt, NE2000State),
652: VMSTATE_UINT16(rcnt, NE2000State),
653: VMSTATE_UINT32(rsar, NE2000State),
654: VMSTATE_UINT8(rsr, NE2000State),
655: VMSTATE_UINT8(isr, NE2000State),
656: VMSTATE_UINT8(dcfg, NE2000State),
657: VMSTATE_UINT8(imr, NE2000State),
658: VMSTATE_BUFFER(phys, NE2000State),
659: VMSTATE_UINT8(curpag, NE2000State),
660: VMSTATE_BUFFER(mult, NE2000State),
661: VMSTATE_UNUSED(4), /* was irq */
662: VMSTATE_BUFFER(mem, NE2000State),
663: VMSTATE_END_OF_LIST()
664: }
665: };
1.1.1.6 root 666:
1.1.1.10 root 667: static const VMStateDescription vmstate_pci_ne2000 = {
668: .name = "ne2000",
669: .version_id = 3,
670: .minimum_version_id = 3,
671: .minimum_version_id_old = 3,
672: .fields = (VMStateField []) {
673: VMSTATE_PCI_DEVICE(dev, PCINE2000State),
674: VMSTATE_STRUCT(ne2000, PCINE2000State, 0, vmstate_ne2000, NE2000State),
675: VMSTATE_END_OF_LIST()
676: }
677: };
1.1 root 678:
1.1.1.14! root 679: static uint64_t ne2000_read(void *opaque, target_phys_addr_t addr,
! 680: unsigned size)
! 681: {
! 682: NE2000State *s = opaque;
! 683:
! 684: if (addr < 0x10 && size == 1) {
! 685: return ne2000_ioport_read(s, addr);
! 686: } else if (addr == 0x10) {
! 687: if (size <= 2) {
! 688: return ne2000_asic_ioport_read(s, addr);
! 689: } else {
! 690: return ne2000_asic_ioport_readl(s, addr);
! 691: }
! 692: } else if (addr == 0x1f && size == 1) {
! 693: return ne2000_reset_ioport_read(s, addr);
! 694: }
! 695: return ((uint64_t)1 << (size * 8)) - 1;
! 696: }
1.1 root 697:
1.1.1.14! root 698: static void ne2000_write(void *opaque, target_phys_addr_t addr,
! 699: uint64_t data, unsigned size)
1.1 root 700: {
1.1.1.14! root 701: NE2000State *s = opaque;
1.1 root 702:
1.1.1.14! root 703: if (addr < 0x10 && size == 1) {
! 704: return ne2000_ioport_write(s, addr, data);
! 705: } else if (addr == 0x10) {
! 706: if (size <= 2) {
! 707: return ne2000_asic_ioport_write(s, addr, data);
! 708: } else {
! 709: return ne2000_asic_ioport_writel(s, addr, data);
! 710: }
! 711: } else if (addr == 0x1f && size == 1) {
! 712: return ne2000_reset_ioport_write(s, addr, data);
! 713: }
! 714: }
1.1 root 715:
1.1.1.14! root 716: static const MemoryRegionOps ne2000_ops = {
! 717: .read = ne2000_read,
! 718: .write = ne2000_write,
! 719: .endianness = DEVICE_NATIVE_ENDIAN,
! 720: };
1.1 root 721:
1.1.1.14! root 722: /***********************************************************/
! 723: /* PCI NE2000 definitions */
! 724:
! 725: void ne2000_setup_io(NE2000State *s, unsigned size)
! 726: {
! 727: memory_region_init_io(&s->io, &ne2000_ops, s, "ne2000", size);
1.1 root 728: }
729:
1.1.1.10 root 730: static void ne2000_cleanup(VLANClientState *nc)
1.1.1.8 root 731: {
1.1.1.10 root 732: NE2000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1.1.1.8 root 733:
1.1.1.10 root 734: s->nic = NULL;
1.1.1.8 root 735: }
736:
1.1.1.10 root 737: static NetClientInfo net_ne2000_info = {
738: .type = NET_CLIENT_TYPE_NIC,
739: .size = sizeof(NICState),
740: .can_receive = ne2000_can_receive,
741: .receive = ne2000_receive,
742: .cleanup = ne2000_cleanup,
743: };
744:
745: static int pci_ne2000_init(PCIDevice *pci_dev)
1.1 root 746: {
1.1.1.10 root 747: PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev);
1.1 root 748: NE2000State *s;
749: uint8_t *pci_conf;
1.1.1.6 root 750:
1.1 root 751: pci_conf = d->dev.config;
1.1.1.14! root 752: pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
1.1.1.6 root 753:
1.1 root 754: s = &d->ne2000;
1.1.1.14! root 755: ne2000_setup_io(s, 0x100);
! 756: pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io);
1.1.1.6 root 757: s->irq = d->dev.irq[0];
1.1.1.10 root 758:
759: qemu_macaddr_default_if_unset(&s->c.macaddr);
1.1 root 760: ne2000_reset(s);
1.1.1.7 root 761:
1.1.1.10 root 762: s->nic = qemu_new_nic(&net_ne2000_info, &s->c,
763: pci_dev->qdev.info->name, pci_dev->qdev.id, s);
764: qemu_format_nic_info_str(&s->nic->nc, s->c.macaddr.a);
765:
766: if (!pci_dev->qdev.hotplugged) {
767: static int loaded = 0;
768: if (!loaded) {
1.1.1.13 root 769: rom_add_option("pxe-ne2k_pci.rom", -1);
1.1.1.10 root 770: loaded = 1;
771: }
772: }
1.1 root 773:
1.1.1.12 root 774: add_boot_device_path(s->c.bootindex, &pci_dev->qdev, "/ethernet-phy@0");
775:
1.1.1.10 root 776: return 0;
777: }
778:
779: static int pci_ne2000_exit(PCIDevice *pci_dev)
780: {
781: PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev);
782: NE2000State *s = &d->ne2000;
783:
1.1.1.14! root 784: memory_region_destroy(&s->io);
1.1.1.10 root 785: qemu_del_vlan_client(&s->nic->nc);
786: return 0;
1.1.1.9 root 787: }
1.1.1.6 root 788:
1.1.1.9 root 789: static PCIDeviceInfo ne2000_info = {
1.1.1.10 root 790: .qdev.name = "ne2k_pci",
791: .qdev.size = sizeof(PCINE2000State),
792: .qdev.vmsd = &vmstate_pci_ne2000,
793: .init = pci_ne2000_init,
794: .exit = pci_ne2000_exit,
1.1.1.13 root 795: .vendor_id = PCI_VENDOR_ID_REALTEK,
796: .device_id = PCI_DEVICE_ID_REALTEK_8029,
797: .class_id = PCI_CLASS_NETWORK_ETHERNET,
1.1.1.10 root 798: .qdev.props = (Property[]) {
799: DEFINE_NIC_PROPERTIES(PCINE2000State, ne2000.c),
800: DEFINE_PROP_END_OF_LIST(),
801: }
1.1.1.9 root 802: };
803:
804: static void ne2000_register_devices(void)
805: {
806: pci_qdev_register(&ne2000_info);
1.1 root 807: }
1.1.1.9 root 808:
809: device_init(ne2000_register_devices)
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