Diff for /qemu/hw/omap.h between versions 1.1.1.7 and 1.1.1.8

version 1.1.1.7, 2018/04/24 19:29:58 version 1.1.1.8, 2018/04/24 19:50:27
Line 76  struct omap_l4_agent_info_s { Line 76  struct omap_l4_agent_info_s {
     int ta_region;      int ta_region;
 };  };
 struct omap_target_agent_s {  struct omap_target_agent_s {
       MemoryRegion iomem;
     struct omap_l4_s *bus;      struct omap_l4_s *bus;
     int regions;      int regions;
     const struct omap_l4_region_s *start;      const struct omap_l4_region_s *start;
Line 84  struct omap_target_agent_s { Line 85  struct omap_target_agent_s {
     uint32_t control;      uint32_t control;
     uint32_t status;      uint32_t status;
 };  };
 struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num);  struct omap_l4_s *omap_l4_init(MemoryRegion *address_space,
                                  target_phys_addr_t base, int ta_num);
   
 struct omap_target_agent_s;  struct omap_target_agent_s;
 struct omap_target_agent_s *omap_l4ta_get(  struct omap_target_agent_s *omap_l4ta_get(
Line 92  struct omap_target_agent_s *omap_l4ta_ge Line 94  struct omap_target_agent_s *omap_l4ta_ge
     const struct omap_l4_region_s *regions,      const struct omap_l4_region_s *regions,
     const struct omap_l4_agent_info_s *agents,      const struct omap_l4_agent_info_s *agents,
     int cs);      int cs);
 target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region,  target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta,
                 int iotype);                                           int region, MemoryRegion *mr);
 target_phys_addr_t omap_l4_region_base(struct omap_target_agent_s *ta,  target_phys_addr_t omap_l4_region_base(struct omap_target_agent_s *ta,
                                        int region);                                         int region);
 int l4_register_io_memory(CPUReadMemoryFunc * const *mem_read,  target_phys_addr_t omap_l4_region_size(struct omap_target_agent_s *ta,
                 CPUWriteMemoryFunc * const *mem_write, void *opaque);                                         int region);
   
 /* OMAP2 SDRAM controller */  /* OMAP2 SDRAM controller */
 struct omap_sdrc_s;  struct omap_sdrc_s;
 struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base);  struct omap_sdrc_s *omap_sdrc_init(MemoryRegion *sysmem,
                                      target_phys_addr_t base);
 void omap_sdrc_reset(struct omap_sdrc_s *s);  void omap_sdrc_reset(struct omap_sdrc_s *s);
   
 /* OMAP2 general purpose memory controller */  /* OMAP2 general purpose memory controller */
Line 431  enum omap_dma_model { Line 434  enum omap_dma_model {
   
 struct soc_dma_s;  struct soc_dma_s;
 struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,  struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
                   MemoryRegion *sysmem,
                 qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,                  qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
                 enum omap_dma_model model);                  enum omap_dma_model model);
 struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,  struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
                   MemoryRegion *sysmem,
                 struct omap_mpu_state_s *mpu, int fifo,                  struct omap_mpu_state_s *mpu, int fifo,
                 int chans, omap_clk iclk, omap_clk fclk);                  int chans, omap_clk iclk, omap_clk fclk);
 void omap_dma_reset(struct soc_dma_s *s);  void omap_dma_reset(struct soc_dma_s *s);
Line 658  struct omap_uart_s *omap_uart_init(targe Line 663  struct omap_uart_s *omap_uart_init(targe
                 qemu_irq irq, omap_clk fclk, omap_clk iclk,                  qemu_irq irq, omap_clk fclk, omap_clk iclk,
                 qemu_irq txdma, qemu_irq rxdma,                  qemu_irq txdma, qemu_irq rxdma,
                 const char *label, CharDriverState *chr);                  const char *label, CharDriverState *chr);
 struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta,  struct omap_uart_s *omap2_uart_init(MemoryRegion *sysmem,
                   struct omap_target_agent_s *ta,
                 qemu_irq irq, omap_clk fclk, omap_clk iclk,                  qemu_irq irq, omap_clk fclk, omap_clk iclk,
                 qemu_irq txdma, qemu_irq rxdma,                  qemu_irq txdma, qemu_irq rxdma,
                 const char *label, CharDriverState *chr);                  const char *label, CharDriverState *chr);
Line 666  void omap_uart_reset(struct omap_uart_s  Line 672  void omap_uart_reset(struct omap_uart_s 
 void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr);  void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr);
   
 struct omap_mpuio_s;  struct omap_mpuio_s;
 struct omap_mpuio_s *omap_mpuio_init(MemoryRegion *system_memory,  
                 target_phys_addr_t base,  
                 qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,  
                 omap_clk clk);  
 qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s);  qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s);
 void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler);  void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler);
 void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down);  void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down);
Line 725  void omap_tap_init(struct omap_target_ag Line 727  void omap_tap_init(struct omap_target_ag
 /* omap_lcdc.c */  /* omap_lcdc.c */
 struct omap_lcd_panel_s;  struct omap_lcd_panel_s;
 void omap_lcdc_reset(struct omap_lcd_panel_s *s);  void omap_lcdc_reset(struct omap_lcd_panel_s *s);
 struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,  struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem,
                 struct omap_dma_lcd_channel_s *dma, omap_clk clk);                                          target_phys_addr_t base,
                                           qemu_irq irq,
                                           struct omap_dma_lcd_channel_s *dma,
                                           omap_clk clk);
   
 /* omap_dss.c */  /* omap_dss.c */
 struct rfbi_chip_s {  struct rfbi_chip_s {
Line 738  struct rfbi_chip_s { Line 743  struct rfbi_chip_s {
 struct omap_dss_s;  struct omap_dss_s;
 void omap_dss_reset(struct omap_dss_s *s);  void omap_dss_reset(struct omap_dss_s *s);
 struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,  struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
                   MemoryRegion *sysmem,
                 target_phys_addr_t l3_base,                  target_phys_addr_t l3_base,
                 qemu_irq irq, qemu_irq drq,                  qemu_irq irq, qemu_irq drq,
                 omap_clk fck1, omap_clk fck2, omap_clk ck54m,                  omap_clk fck1, omap_clk fck2, omap_clk ck54m,
Line 747  void omap_rfbi_attach(struct omap_dss_s  Line 753  void omap_rfbi_attach(struct omap_dss_s 
 /* omap_mmc.c */  /* omap_mmc.c */
 struct omap_mmc_s;  struct omap_mmc_s;
 struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,  struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
                   MemoryRegion *sysmem,
                 BlockDriverState *bd,                  BlockDriverState *bd,
                 qemu_irq irq, qemu_irq dma[], omap_clk clk);                  qemu_irq irq, qemu_irq dma[], omap_clk clk);
 struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,  struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,
Line 757  void omap_mmc_handlers(struct omap_mmc_s Line 764  void omap_mmc_handlers(struct omap_mmc_s
 void omap_mmc_enable(struct omap_mmc_s *s, int enable);  void omap_mmc_enable(struct omap_mmc_s *s, int enable);
   
 /* omap_i2c.c */  /* omap_i2c.c */
 struct omap_i2c_s;  i2c_bus *omap_i2c_bus(DeviceState *omap_i2c);
 struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,  
                 qemu_irq irq, qemu_irq *dma, omap_clk clk);  
 struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta,  
                 qemu_irq irq, qemu_irq *dma, omap_clk fclk, omap_clk iclk);  
 void omap_i2c_reset(struct omap_i2c_s *s);  
 i2c_bus *omap_i2c_bus(struct omap_i2c_s *s);  
   
 # define cpu_is_omap310(cpu)            (cpu->mpu_model == omap310)  # define cpu_is_omap310(cpu)            (cpu->mpu_model == omap310)
 # define cpu_is_omap1510(cpu)           (cpu->mpu_model == omap1510)  # define cpu_is_omap1510(cpu)           (cpu->mpu_model == omap1510)
Line 803  struct omap_mpu_state_s { Line 804  struct omap_mpu_state_s {
         omap3630,          omap3630,
     } mpu_model;      } mpu_model;
   
     CPUState *env;      CPUARMState *env;
   
     qemu_irq *drq;      qemu_irq *drq;
   
Line 819  struct omap_mpu_state_s { Line 820  struct omap_mpu_state_s {
     MemoryRegion tcmi_iomem;      MemoryRegion tcmi_iomem;
     MemoryRegion clkm_iomem;      MemoryRegion clkm_iomem;
     MemoryRegion clkdsp_iomem;      MemoryRegion clkdsp_iomem;
     MemoryRegion pwl_iomem;  
     MemoryRegion pwt_iomem;  
     MemoryRegion mpui_io_iomem;      MemoryRegion mpui_io_iomem;
       MemoryRegion tap_iomem;
     MemoryRegion imif_ram;      MemoryRegion imif_ram;
     MemoryRegion emiff_ram;      MemoryRegion emiff_ram;
       MemoryRegion sdram;
       MemoryRegion sram;
   
     struct omap_dma_port_if_s {      struct omap_dma_port_if_s {
         uint32_t (*read[3])(struct omap_mpu_state_s *s,          uint32_t (*read[3])(struct omap_mpu_state_s *s,
Line 854  struct omap_mpu_state_s { Line 856  struct omap_mpu_state_s {
   
     struct omap_uwire_s *microwire;      struct omap_uwire_s *microwire;
   
     struct {      struct omap_pwl_s *pwl;
         uint8_t output;      struct omap_pwt_s *pwt;
         uint8_t level;      DeviceState *i2c[2];
         uint8_t enable;  
         int clk;  
     } pwl;  
   
     struct {  
         uint8_t frc;  
         uint8_t vrc;  
         uint8_t gcr;  
         omap_clk clk;  
     } pwt;  
   
     struct omap_i2c_s *i2c[2];  
   
     struct omap_rtc_s *rtc;      struct omap_rtc_s *rtc;
   
Line 905  struct omap_mpu_state_s { Line 895  struct omap_mpu_state_s {
   
     uint32_t tcmi_regs[17];      uint32_t tcmi_regs[17];
   
     struct dpll_ctl_s {      struct dpll_ctl_s *dpll[3];
         MemoryRegion iomem;  
         uint16_t mode;  
         omap_clk dpll;  
     } dpll[3];  
   
     omap_clk clks;      omap_clk clks;
     struct {      struct {
Line 952  struct omap_mpu_state_s *omap310_mpu_ini Line 938  struct omap_mpu_state_s *omap310_mpu_ini
                 const char *core);                  const char *core);
   
 /* omap2.c */  /* omap2.c */
 struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,  struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
                   unsigned long sdram_size,
                 const char *core);                  const char *core);
   
 # if TARGET_PHYS_ADDR_BITS == 32  # if TARGET_PHYS_ADDR_BITS == 32
Line 1125  inline static int debug_register_io_memo Line 1112  inline static int debug_register_io_memo
 #  define cpu_register_io_memory        debug_register_io_memory  #  define cpu_register_io_memory        debug_register_io_memory
 # endif  # endif
   
 /* Define when we want to reduce the number of IO regions registered.  */  
 /*# define L4_MUX_HACK*/  
   
 #endif /* hw_omap_h */  #endif /* hw_omap_h */

Removed from v.1.1.1.7  
changed lines
  Added in v.1.1.1.8


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