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1.1 root 1: /*
2: * Texas Instruments OMAP processors.
3: *
1.1.1.2 ! root 4: * Copyright (C) 2006-2008 Andrzej Zaborowski <[email protected]>
1.1 root 5: *
6: * This program is free software; you can redistribute it and/or
7: * modify it under the terms of the GNU General Public License as
1.1.1.2 ! root 8: * published by the Free Software Foundation; either version 2 or
! 9: * (at your option) version 3 of the License.
1.1 root 10: *
11: * This program is distributed in the hope that it will be useful,
12: * but WITHOUT ANY WARRANTY; without even the implied warranty of
13: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14: * GNU General Public License for more details.
15: *
1.1.1.2 ! root 16: * You should have received a copy of the GNU General Public License along
! 17: * with this program; if not, write to the Free Software Foundation, Inc.,
! 18: * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
1.1 root 19: */
20: #ifndef hw_omap_h
21: # define hw_omap_h "omap.h"
22:
23: # define OMAP_EMIFS_BASE 0x00000000
1.1.1.2 ! root 24: # define OMAP2_Q0_BASE 0x00000000
1.1 root 25: # define OMAP_CS0_BASE 0x00000000
26: # define OMAP_CS1_BASE 0x04000000
27: # define OMAP_CS2_BASE 0x08000000
28: # define OMAP_CS3_BASE 0x0c000000
29: # define OMAP_EMIFF_BASE 0x10000000
30: # define OMAP_IMIF_BASE 0x20000000
31: # define OMAP_LOCALBUS_BASE 0x30000000
1.1.1.2 ! root 32: # define OMAP2_Q1_BASE 0x40000000
! 33: # define OMAP2_L4_BASE 0x48000000
! 34: # define OMAP2_SRAM_BASE 0x40200000
! 35: # define OMAP2_L3_BASE 0x68000000
! 36: # define OMAP2_Q2_BASE 0x80000000
! 37: # define OMAP2_Q3_BASE 0xc0000000
1.1 root 38: # define OMAP_MPUI_BASE 0xe1000000
39:
40: # define OMAP730_SRAM_SIZE 0x00032000
41: # define OMAP15XX_SRAM_SIZE 0x00030000
42: # define OMAP16XX_SRAM_SIZE 0x00004000
43: # define OMAP1611_SRAM_SIZE 0x0003e800
1.1.1.2 ! root 44: # define OMAP242X_SRAM_SIZE 0x000a0000
! 45: # define OMAP243X_SRAM_SIZE 0x00010000
1.1 root 46: # define OMAP_CS0_SIZE 0x04000000
47: # define OMAP_CS1_SIZE 0x04000000
48: # define OMAP_CS2_SIZE 0x04000000
49: # define OMAP_CS3_SIZE 0x04000000
50:
1.1.1.2 ! root 51: /* omap_clk.c */
1.1 root 52: struct omap_mpu_state_s;
53: typedef struct clk *omap_clk;
54: omap_clk omap_findclk(struct omap_mpu_state_s *mpu, const char *name);
55: void omap_clk_init(struct omap_mpu_state_s *mpu);
56: void omap_clk_adduser(struct clk *clk, qemu_irq user);
57: void omap_clk_get(omap_clk clk);
58: void omap_clk_put(omap_clk clk);
59: void omap_clk_onoff(omap_clk clk, int on);
60: void omap_clk_canidle(omap_clk clk, int can);
61: void omap_clk_setrate(omap_clk clk, int divide, int multiply);
62: int64_t omap_clk_getrate(omap_clk clk);
63: void omap_clk_reparent(omap_clk clk, omap_clk parent);
64:
1.1.1.2 ! root 65: /* omap[123].c */
! 66: struct omap_l4_s;
! 67: struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num);
! 68:
! 69: struct omap_target_agent_s;
! 70: struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus, int cs);
! 71: target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region,
! 72: int iotype);
! 73: # define l4_register_io_memory cpu_register_io_memory
! 74:
1.1 root 75: struct omap_intr_handler_s;
76: struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
1.1.1.2 ! root 77: unsigned long size, unsigned char nbanks, qemu_irq **pins,
1.1 root 78: qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk);
1.1.1.2 ! root 79: struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base,
! 80: int size, int nbanks, qemu_irq **pins,
! 81: qemu_irq parent_irq, qemu_irq parent_fiq,
! 82: omap_clk fclk, omap_clk iclk);
! 83: void omap_inth_reset(struct omap_intr_handler_s *s);
! 84:
! 85: struct omap_prcm_s;
! 86: struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta,
! 87: qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int,
! 88: struct omap_mpu_state_s *mpu);
! 89:
! 90: struct omap_sysctl_s;
! 91: struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta,
! 92: omap_clk iclk, struct omap_mpu_state_s *mpu);
! 93:
! 94: struct omap_sdrc_s;
! 95: struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base);
! 96:
! 97: struct omap_gpmc_s;
! 98: struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq);
! 99: void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
! 100: void (*base_upd)(void *opaque, target_phys_addr_t new),
! 101: void (*unmap)(void *opaque), void *opaque);
1.1 root 102:
103: /*
104: * Common IRQ numbers for level 1 interrupt handler
105: * See /usr/include/asm-arm/arch-omap/irqs.h in Linux.
106: */
107: # define OMAP_INT_CAMERA 1
108: # define OMAP_INT_FIQ 3
109: # define OMAP_INT_RTDX 6
110: # define OMAP_INT_DSP_MMU_ABORT 7
111: # define OMAP_INT_HOST 8
112: # define OMAP_INT_ABORT 9
113: # define OMAP_INT_BRIDGE_PRIV 13
114: # define OMAP_INT_GPIO_BANK1 14
115: # define OMAP_INT_UART3 15
116: # define OMAP_INT_TIMER3 16
117: # define OMAP_INT_DMA_CH0_6 19
118: # define OMAP_INT_DMA_CH1_7 20
119: # define OMAP_INT_DMA_CH2_8 21
120: # define OMAP_INT_DMA_CH3 22
121: # define OMAP_INT_DMA_CH4 23
122: # define OMAP_INT_DMA_CH5 24
123: # define OMAP_INT_DMA_LCD 25
124: # define OMAP_INT_TIMER1 26
125: # define OMAP_INT_WD_TIMER 27
126: # define OMAP_INT_BRIDGE_PUB 28
127: # define OMAP_INT_TIMER2 30
128: # define OMAP_INT_LCD_CTRL 31
129:
130: /*
131: * Common OMAP-15xx IRQ numbers for level 1 interrupt handler
132: */
133: # define OMAP_INT_15XX_IH2_IRQ 0
134: # define OMAP_INT_15XX_LB_MMU 17
135: # define OMAP_INT_15XX_LOCAL_BUS 29
136:
137: /*
138: * OMAP-1510 specific IRQ numbers for level 1 interrupt handler
139: */
140: # define OMAP_INT_1510_SPI_TX 4
141: # define OMAP_INT_1510_SPI_RX 5
142: # define OMAP_INT_1510_DSP_MAILBOX1 10
143: # define OMAP_INT_1510_DSP_MAILBOX2 11
144:
145: /*
146: * OMAP-310 specific IRQ numbers for level 1 interrupt handler
147: */
148: # define OMAP_INT_310_McBSP2_TX 4
149: # define OMAP_INT_310_McBSP2_RX 5
150: # define OMAP_INT_310_HSB_MAILBOX1 12
151: # define OMAP_INT_310_HSAB_MMU 18
152:
153: /*
154: * OMAP-1610 specific IRQ numbers for level 1 interrupt handler
155: */
156: # define OMAP_INT_1610_IH2_IRQ 0
157: # define OMAP_INT_1610_IH2_FIQ 2
158: # define OMAP_INT_1610_McBSP2_TX 4
159: # define OMAP_INT_1610_McBSP2_RX 5
160: # define OMAP_INT_1610_DSP_MAILBOX1 10
161: # define OMAP_INT_1610_DSP_MAILBOX2 11
162: # define OMAP_INT_1610_LCD_LINE 12
163: # define OMAP_INT_1610_GPTIMER1 17
164: # define OMAP_INT_1610_GPTIMER2 18
165: # define OMAP_INT_1610_SSR_FIFO_0 29
166:
167: /*
168: * OMAP-730 specific IRQ numbers for level 1 interrupt handler
169: */
170: # define OMAP_INT_730_IH2_FIQ 0
171: # define OMAP_INT_730_IH2_IRQ 1
172: # define OMAP_INT_730_USB_NON_ISO 2
173: # define OMAP_INT_730_USB_ISO 3
174: # define OMAP_INT_730_ICR 4
175: # define OMAP_INT_730_EAC 5
176: # define OMAP_INT_730_GPIO_BANK1 6
177: # define OMAP_INT_730_GPIO_BANK2 7
178: # define OMAP_INT_730_GPIO_BANK3 8
179: # define OMAP_INT_730_McBSP2TX 10
180: # define OMAP_INT_730_McBSP2RX 11
181: # define OMAP_INT_730_McBSP2RX_OVF 12
182: # define OMAP_INT_730_LCD_LINE 14
183: # define OMAP_INT_730_GSM_PROTECT 15
184: # define OMAP_INT_730_TIMER3 16
185: # define OMAP_INT_730_GPIO_BANK5 17
186: # define OMAP_INT_730_GPIO_BANK6 18
187: # define OMAP_INT_730_SPGIO_WR 29
188:
189: /*
190: * Common IRQ numbers for level 2 interrupt handler
191: */
192: # define OMAP_INT_KEYBOARD 1
193: # define OMAP_INT_uWireTX 2
194: # define OMAP_INT_uWireRX 3
195: # define OMAP_INT_I2C 4
196: # define OMAP_INT_MPUIO 5
197: # define OMAP_INT_USB_HHC_1 6
198: # define OMAP_INT_McBSP3TX 10
199: # define OMAP_INT_McBSP3RX 11
200: # define OMAP_INT_McBSP1TX 12
201: # define OMAP_INT_McBSP1RX 13
202: # define OMAP_INT_UART1 14
203: # define OMAP_INT_UART2 15
204: # define OMAP_INT_USB_W2FC 20
205: # define OMAP_INT_1WIRE 21
206: # define OMAP_INT_OS_TIMER 22
207: # define OMAP_INT_OQN 23
208: # define OMAP_INT_GAUGE_32K 24
209: # define OMAP_INT_RTC_TIMER 25
210: # define OMAP_INT_RTC_ALARM 26
211: # define OMAP_INT_DSP_MMU 28
212:
213: /*
214: * OMAP-1510 specific IRQ numbers for level 2 interrupt handler
215: */
216: # define OMAP_INT_1510_BT_MCSI1TX 16
217: # define OMAP_INT_1510_BT_MCSI1RX 17
218: # define OMAP_INT_1510_SoSSI_MATCH 19
219: # define OMAP_INT_1510_MEM_STICK 27
220: # define OMAP_INT_1510_COM_SPI_RO 31
221:
222: /*
223: * OMAP-310 specific IRQ numbers for level 2 interrupt handler
224: */
225: # define OMAP_INT_310_FAC 0
226: # define OMAP_INT_310_USB_HHC_2 7
227: # define OMAP_INT_310_MCSI1_FE 16
228: # define OMAP_INT_310_MCSI2_FE 17
229: # define OMAP_INT_310_USB_W2FC_ISO 29
230: # define OMAP_INT_310_USB_W2FC_NON_ISO 30
231: # define OMAP_INT_310_McBSP2RX_OF 31
232:
233: /*
234: * OMAP-1610 specific IRQ numbers for level 2 interrupt handler
235: */
236: # define OMAP_INT_1610_FAC 0
237: # define OMAP_INT_1610_USB_HHC_2 7
238: # define OMAP_INT_1610_USB_OTG 8
239: # define OMAP_INT_1610_SoSSI 9
240: # define OMAP_INT_1610_BT_MCSI1TX 16
241: # define OMAP_INT_1610_BT_MCSI1RX 17
242: # define OMAP_INT_1610_SoSSI_MATCH 19
243: # define OMAP_INT_1610_MEM_STICK 27
244: # define OMAP_INT_1610_McBSP2RX_OF 31
245: # define OMAP_INT_1610_STI 32
246: # define OMAP_INT_1610_STI_WAKEUP 33
247: # define OMAP_INT_1610_GPTIMER3 34
248: # define OMAP_INT_1610_GPTIMER4 35
249: # define OMAP_INT_1610_GPTIMER5 36
250: # define OMAP_INT_1610_GPTIMER6 37
251: # define OMAP_INT_1610_GPTIMER7 38
252: # define OMAP_INT_1610_GPTIMER8 39
253: # define OMAP_INT_1610_GPIO_BANK2 40
254: # define OMAP_INT_1610_GPIO_BANK3 41
255: # define OMAP_INT_1610_MMC2 42
256: # define OMAP_INT_1610_CF 43
257: # define OMAP_INT_1610_WAKE_UP_REQ 46
258: # define OMAP_INT_1610_GPIO_BANK4 48
259: # define OMAP_INT_1610_SPI 49
260: # define OMAP_INT_1610_DMA_CH6 53
261: # define OMAP_INT_1610_DMA_CH7 54
262: # define OMAP_INT_1610_DMA_CH8 55
263: # define OMAP_INT_1610_DMA_CH9 56
264: # define OMAP_INT_1610_DMA_CH10 57
265: # define OMAP_INT_1610_DMA_CH11 58
266: # define OMAP_INT_1610_DMA_CH12 59
267: # define OMAP_INT_1610_DMA_CH13 60
268: # define OMAP_INT_1610_DMA_CH14 61
269: # define OMAP_INT_1610_DMA_CH15 62
270: # define OMAP_INT_1610_NAND 63
271:
272: /*
273: * OMAP-730 specific IRQ numbers for level 2 interrupt handler
274: */
275: # define OMAP_INT_730_HW_ERRORS 0
276: # define OMAP_INT_730_NFIQ_PWR_FAIL 1
277: # define OMAP_INT_730_CFCD 2
278: # define OMAP_INT_730_CFIREQ 3
279: # define OMAP_INT_730_I2C 4
280: # define OMAP_INT_730_PCC 5
281: # define OMAP_INT_730_MPU_EXT_NIRQ 6
282: # define OMAP_INT_730_SPI_100K_1 7
283: # define OMAP_INT_730_SYREN_SPI 8
284: # define OMAP_INT_730_VLYNQ 9
285: # define OMAP_INT_730_GPIO_BANK4 10
286: # define OMAP_INT_730_McBSP1TX 11
287: # define OMAP_INT_730_McBSP1RX 12
288: # define OMAP_INT_730_McBSP1RX_OF 13
289: # define OMAP_INT_730_UART_MODEM_IRDA_2 14
290: # define OMAP_INT_730_UART_MODEM_1 15
291: # define OMAP_INT_730_MCSI 16
292: # define OMAP_INT_730_uWireTX 17
293: # define OMAP_INT_730_uWireRX 18
294: # define OMAP_INT_730_SMC_CD 19
295: # define OMAP_INT_730_SMC_IREQ 20
296: # define OMAP_INT_730_HDQ_1WIRE 21
297: # define OMAP_INT_730_TIMER32K 22
298: # define OMAP_INT_730_MMC_SDIO 23
299: # define OMAP_INT_730_UPLD 24
300: # define OMAP_INT_730_USB_HHC_1 27
301: # define OMAP_INT_730_USB_HHC_2 28
302: # define OMAP_INT_730_USB_GENI 29
303: # define OMAP_INT_730_USB_OTG 30
304: # define OMAP_INT_730_CAMERA_IF 31
305: # define OMAP_INT_730_RNG 32
306: # define OMAP_INT_730_DUAL_MODE_TIMER 33
307: # define OMAP_INT_730_DBB_RF_EN 34
308: # define OMAP_INT_730_MPUIO_KEYPAD 35
309: # define OMAP_INT_730_SHA1_MD5 36
310: # define OMAP_INT_730_SPI_100K_2 37
311: # define OMAP_INT_730_RNG_IDLE 38
312: # define OMAP_INT_730_MPUIO 39
313: # define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40
314: # define OMAP_INT_730_LLPC_OE_FALLING 41
315: # define OMAP_INT_730_LLPC_OE_RISING 42
316: # define OMAP_INT_730_LLPC_VSYNC 43
317: # define OMAP_INT_730_WAKE_UP_REQ 46
318: # define OMAP_INT_730_DMA_CH6 53
319: # define OMAP_INT_730_DMA_CH7 54
320: # define OMAP_INT_730_DMA_CH8 55
321: # define OMAP_INT_730_DMA_CH9 56
322: # define OMAP_INT_730_DMA_CH10 57
323: # define OMAP_INT_730_DMA_CH11 58
324: # define OMAP_INT_730_DMA_CH12 59
325: # define OMAP_INT_730_DMA_CH13 60
326: # define OMAP_INT_730_DMA_CH14 61
327: # define OMAP_INT_730_DMA_CH15 62
328: # define OMAP_INT_730_NAND 63
329:
330: /*
331: * OMAP-24xx common IRQ numbers
332: */
1.1.1.2 ! root 333: # define OMAP_INT_24XX_STI 4
1.1 root 334: # define OMAP_INT_24XX_SYS_NIRQ 7
1.1.1.2 ! root 335: # define OMAP_INT_24XX_L3_IRQ 10
! 336: # define OMAP_INT_24XX_PRCM_MPU_IRQ 11
1.1 root 337: # define OMAP_INT_24XX_SDMA_IRQ0 12
338: # define OMAP_INT_24XX_SDMA_IRQ1 13
339: # define OMAP_INT_24XX_SDMA_IRQ2 14
340: # define OMAP_INT_24XX_SDMA_IRQ3 15
1.1.1.2 ! root 341: # define OMAP_INT_243X_MCBSP2_IRQ 16
! 342: # define OMAP_INT_243X_MCBSP3_IRQ 17
! 343: # define OMAP_INT_243X_MCBSP4_IRQ 18
! 344: # define OMAP_INT_243X_MCBSP5_IRQ 19
! 345: # define OMAP_INT_24XX_GPMC_IRQ 20
! 346: # define OMAP_INT_24XX_GUFFAW_IRQ 21
! 347: # define OMAP_INT_24XX_IVA_IRQ 22
! 348: # define OMAP_INT_24XX_EAC_IRQ 23
1.1 root 349: # define OMAP_INT_24XX_CAM_IRQ 24
350: # define OMAP_INT_24XX_DSS_IRQ 25
351: # define OMAP_INT_24XX_MAIL_U0_MPU 26
352: # define OMAP_INT_24XX_DSP_UMA 27
353: # define OMAP_INT_24XX_DSP_MMU 28
354: # define OMAP_INT_24XX_GPIO_BANK1 29
355: # define OMAP_INT_24XX_GPIO_BANK2 30
356: # define OMAP_INT_24XX_GPIO_BANK3 31
357: # define OMAP_INT_24XX_GPIO_BANK4 32
1.1.1.2 ! root 358: # define OMAP_INT_243X_GPIO_BANK5 33
1.1 root 359: # define OMAP_INT_24XX_MAIL_U3_MPU 34
1.1.1.2 ! root 360: # define OMAP_INT_24XX_WDT3 35
! 361: # define OMAP_INT_24XX_WDT4 36
1.1 root 362: # define OMAP_INT_24XX_GPTIMER1 37
363: # define OMAP_INT_24XX_GPTIMER2 38
364: # define OMAP_INT_24XX_GPTIMER3 39
365: # define OMAP_INT_24XX_GPTIMER4 40
366: # define OMAP_INT_24XX_GPTIMER5 41
367: # define OMAP_INT_24XX_GPTIMER6 42
368: # define OMAP_INT_24XX_GPTIMER7 43
369: # define OMAP_INT_24XX_GPTIMER8 44
370: # define OMAP_INT_24XX_GPTIMER9 45
371: # define OMAP_INT_24XX_GPTIMER10 46
372: # define OMAP_INT_24XX_GPTIMER11 47
373: # define OMAP_INT_24XX_GPTIMER12 48
1.1.1.2 ! root 374: # define OMAP_INT_24XX_PKA_IRQ 50
! 375: # define OMAP_INT_24XX_SHA1MD5_IRQ 51
! 376: # define OMAP_INT_24XX_RNG_IRQ 52
! 377: # define OMAP_INT_24XX_MG_IRQ 53
! 378: # define OMAP_INT_24XX_I2C1_IRQ 56
! 379: # define OMAP_INT_24XX_I2C2_IRQ 57
1.1 root 380: # define OMAP_INT_24XX_MCBSP1_IRQ_TX 59
381: # define OMAP_INT_24XX_MCBSP1_IRQ_RX 60
382: # define OMAP_INT_24XX_MCBSP2_IRQ_TX 62
383: # define OMAP_INT_24XX_MCBSP2_IRQ_RX 63
1.1.1.2 ! root 384: # define OMAP_INT_243X_MCBSP1_IRQ 64
! 385: # define OMAP_INT_24XX_MCSPI1_IRQ 65
! 386: # define OMAP_INT_24XX_MCSPI2_IRQ 66
! 387: # define OMAP_INT_24XX_SSI1_IRQ0 67
! 388: # define OMAP_INT_24XX_SSI1_IRQ1 68
! 389: # define OMAP_INT_24XX_SSI2_IRQ0 69
! 390: # define OMAP_INT_24XX_SSI2_IRQ1 70
! 391: # define OMAP_INT_24XX_SSI_GDD_IRQ 71
1.1 root 392: # define OMAP_INT_24XX_UART1_IRQ 72
393: # define OMAP_INT_24XX_UART2_IRQ 73
394: # define OMAP_INT_24XX_UART3_IRQ 74
395: # define OMAP_INT_24XX_USB_IRQ_GEN 75
396: # define OMAP_INT_24XX_USB_IRQ_NISO 76
397: # define OMAP_INT_24XX_USB_IRQ_ISO 77
398: # define OMAP_INT_24XX_USB_IRQ_HGEN 78
399: # define OMAP_INT_24XX_USB_IRQ_HSOF 79
400: # define OMAP_INT_24XX_USB_IRQ_OTG 80
1.1.1.2 ! root 401: # define OMAP_INT_24XX_VLYNQ_IRQ 81
1.1 root 402: # define OMAP_INT_24XX_MMC_IRQ 83
1.1.1.2 ! root 403: # define OMAP_INT_24XX_MS_IRQ 84
! 404: # define OMAP_INT_24XX_FAC_IRQ 85
! 405: # define OMAP_INT_24XX_MCSPI3_IRQ 91
1.1 root 406: # define OMAP_INT_243X_HS_USB_MC 92
407: # define OMAP_INT_243X_HS_USB_DMA 93
408: # define OMAP_INT_243X_CARKIT 94
1.1.1.2 ! root 409: # define OMAP_INT_34XX_GPTIMER12 95
1.1 root 410:
1.1.1.2 ! root 411: /* omap_dma.c */
1.1 root 412: enum omap_dma_model {
1.1.1.2 ! root 413: omap_dma_3_0,
! 414: omap_dma_3_1,
! 415: omap_dma_3_2,
! 416: omap_dma_4,
1.1 root 417: };
418:
1.1.1.2 ! root 419: struct soc_dma_s;
! 420: struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
1.1 root 421: qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
422: enum omap_dma_model model);
1.1.1.2 ! root 423: struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
! 424: struct omap_mpu_state_s *mpu, int fifo,
! 425: int chans, omap_clk iclk, omap_clk fclk);
! 426: void omap_dma_reset(struct soc_dma_s *s);
! 427:
! 428: struct dma_irq_map {
! 429: int ih;
! 430: int intr;
! 431: };
1.1 root 432:
1.1.1.2 ! root 433: /* Only used in OMAP DMA 3.x gigacells */
1.1 root 434: enum omap_dma_port {
435: emiff = 0,
436: emifs,
437: imif, /* omap16xx: ocp_t1 */
438: tipb,
439: local, /* omap16xx: ocp_t2 */
440: tipb_mpui,
1.1.1.2 ! root 441: __omap_dma_port_last,
1.1 root 442: };
443:
444: typedef enum {
445: constant = 0,
446: post_incremented,
447: single_index,
448: double_index,
449: } omap_dma_addressing_t;
450:
1.1.1.2 ! root 451: /* Only used in OMAP DMA 3.x gigacells */
1.1 root 452: struct omap_dma_lcd_channel_s {
453: enum omap_dma_port src;
454: target_phys_addr_t src_f1_top;
455: target_phys_addr_t src_f1_bottom;
456: target_phys_addr_t src_f2_top;
457: target_phys_addr_t src_f2_bottom;
458:
459: /* Used in OMAP DMA 3.2 gigacell */
460: unsigned char brust_f1;
461: unsigned char pack_f1;
462: unsigned char data_type_f1;
463: unsigned char brust_f2;
464: unsigned char pack_f2;
465: unsigned char data_type_f2;
466: unsigned char end_prog;
467: unsigned char repeat;
468: unsigned char auto_init;
469: unsigned char priority;
470: unsigned char fs;
471: unsigned char running;
472: unsigned char bs;
473: unsigned char omap_3_1_compatible_disable;
474: unsigned char dst;
475: unsigned char lch_type;
476: int16_t element_index_f1;
477: int16_t element_index_f2;
478: int32_t frame_index_f1;
479: int32_t frame_index_f2;
480: uint16_t elements_f1;
481: uint16_t frames_f1;
482: uint16_t elements_f2;
483: uint16_t frames_f2;
484: omap_dma_addressing_t mode_f1;
485: omap_dma_addressing_t mode_f2;
486:
487: /* Destination port is fixed. */
488: int interrupts;
489: int condition;
490: int dual;
491:
492: int current_frame;
493: ram_addr_t phys_framebuffer[2];
494: qemu_irq irq;
495: struct omap_mpu_state_s *mpu;
1.1.1.2 ! root 496: } *omap_dma_get_lcdch(struct soc_dma_s *s);
1.1 root 497:
498: /*
499: * DMA request numbers for OMAP1
500: * See /usr/include/asm-arm/arch-omap/dma.h in Linux.
501: */
502: # define OMAP_DMA_NO_DEVICE 0
503: # define OMAP_DMA_MCSI1_TX 1
504: # define OMAP_DMA_MCSI1_RX 2
505: # define OMAP_DMA_I2C_RX 3
506: # define OMAP_DMA_I2C_TX 4
507: # define OMAP_DMA_EXT_NDMA_REQ0 5
508: # define OMAP_DMA_EXT_NDMA_REQ1 6
509: # define OMAP_DMA_UWIRE_TX 7
510: # define OMAP_DMA_MCBSP1_TX 8
511: # define OMAP_DMA_MCBSP1_RX 9
512: # define OMAP_DMA_MCBSP3_TX 10
513: # define OMAP_DMA_MCBSP3_RX 11
514: # define OMAP_DMA_UART1_TX 12
515: # define OMAP_DMA_UART1_RX 13
516: # define OMAP_DMA_UART2_TX 14
517: # define OMAP_DMA_UART2_RX 15
518: # define OMAP_DMA_MCBSP2_TX 16
519: # define OMAP_DMA_MCBSP2_RX 17
520: # define OMAP_DMA_UART3_TX 18
521: # define OMAP_DMA_UART3_RX 19
522: # define OMAP_DMA_CAMERA_IF_RX 20
523: # define OMAP_DMA_MMC_TX 21
524: # define OMAP_DMA_MMC_RX 22
525: # define OMAP_DMA_NAND 23 /* Not in OMAP310 */
526: # define OMAP_DMA_IRQ_LCD_LINE 24 /* Not in OMAP310 */
527: # define OMAP_DMA_MEMORY_STICK 25 /* Not in OMAP310 */
528: # define OMAP_DMA_USB_W2FC_RX0 26
529: # define OMAP_DMA_USB_W2FC_RX1 27
530: # define OMAP_DMA_USB_W2FC_RX2 28
531: # define OMAP_DMA_USB_W2FC_TX0 29
532: # define OMAP_DMA_USB_W2FC_TX1 30
533: # define OMAP_DMA_USB_W2FC_TX2 31
534:
535: /* These are only for 1610 */
536: # define OMAP_DMA_CRYPTO_DES_IN 32
537: # define OMAP_DMA_SPI_TX 33
538: # define OMAP_DMA_SPI_RX 34
539: # define OMAP_DMA_CRYPTO_HASH 35
540: # define OMAP_DMA_CCP_ATTN 36
541: # define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37
542: # define OMAP_DMA_CMT_APE_TX_CHAN_0 38
543: # define OMAP_DMA_CMT_APE_RV_CHAN_0 39
544: # define OMAP_DMA_CMT_APE_TX_CHAN_1 40
545: # define OMAP_DMA_CMT_APE_RV_CHAN_1 41
546: # define OMAP_DMA_CMT_APE_TX_CHAN_2 42
547: # define OMAP_DMA_CMT_APE_RV_CHAN_2 43
548: # define OMAP_DMA_CMT_APE_TX_CHAN_3 44
549: # define OMAP_DMA_CMT_APE_RV_CHAN_3 45
550: # define OMAP_DMA_CMT_APE_TX_CHAN_4 46
551: # define OMAP_DMA_CMT_APE_RV_CHAN_4 47
552: # define OMAP_DMA_CMT_APE_TX_CHAN_5 48
553: # define OMAP_DMA_CMT_APE_RV_CHAN_5 49
554: # define OMAP_DMA_CMT_APE_TX_CHAN_6 50
555: # define OMAP_DMA_CMT_APE_RV_CHAN_6 51
556: # define OMAP_DMA_CMT_APE_TX_CHAN_7 52
557: # define OMAP_DMA_CMT_APE_RV_CHAN_7 53
558: # define OMAP_DMA_MMC2_TX 54
559: # define OMAP_DMA_MMC2_RX 55
560: # define OMAP_DMA_CRYPTO_DES_OUT 56
561:
1.1.1.2 ! root 562: /*
! 563: * DMA request numbers for the OMAP2
! 564: */
! 565: # define OMAP24XX_DMA_NO_DEVICE 0
! 566: # define OMAP24XX_DMA_XTI_DMA 1 /* Not in OMAP2420 */
! 567: # define OMAP24XX_DMA_EXT_DMAREQ0 2
! 568: # define OMAP24XX_DMA_EXT_DMAREQ1 3
! 569: # define OMAP24XX_DMA_GPMC 4
! 570: # define OMAP24XX_DMA_GFX 5 /* Not in OMAP2420 */
! 571: # define OMAP24XX_DMA_DSS 6
! 572: # define OMAP24XX_DMA_VLYNQ_TX 7 /* Not in OMAP2420 */
! 573: # define OMAP24XX_DMA_CWT 8 /* Not in OMAP2420 */
! 574: # define OMAP24XX_DMA_AES_TX 9 /* Not in OMAP2420 */
! 575: # define OMAP24XX_DMA_AES_RX 10 /* Not in OMAP2420 */
! 576: # define OMAP24XX_DMA_DES_TX 11 /* Not in OMAP2420 */
! 577: # define OMAP24XX_DMA_DES_RX 12 /* Not in OMAP2420 */
! 578: # define OMAP24XX_DMA_SHA1MD5_RX 13 /* Not in OMAP2420 */
! 579: # define OMAP24XX_DMA_EXT_DMAREQ2 14
! 580: # define OMAP24XX_DMA_EXT_DMAREQ3 15
! 581: # define OMAP24XX_DMA_EXT_DMAREQ4 16
! 582: # define OMAP24XX_DMA_EAC_AC_RD 17
! 583: # define OMAP24XX_DMA_EAC_AC_WR 18
! 584: # define OMAP24XX_DMA_EAC_MD_UL_RD 19
! 585: # define OMAP24XX_DMA_EAC_MD_UL_WR 20
! 586: # define OMAP24XX_DMA_EAC_MD_DL_RD 21
! 587: # define OMAP24XX_DMA_EAC_MD_DL_WR 22
! 588: # define OMAP24XX_DMA_EAC_BT_UL_RD 23
! 589: # define OMAP24XX_DMA_EAC_BT_UL_WR 24
! 590: # define OMAP24XX_DMA_EAC_BT_DL_RD 25
! 591: # define OMAP24XX_DMA_EAC_BT_DL_WR 26
! 592: # define OMAP24XX_DMA_I2C1_TX 27
! 593: # define OMAP24XX_DMA_I2C1_RX 28
! 594: # define OMAP24XX_DMA_I2C2_TX 29
! 595: # define OMAP24XX_DMA_I2C2_RX 30
! 596: # define OMAP24XX_DMA_MCBSP1_TX 31
! 597: # define OMAP24XX_DMA_MCBSP1_RX 32
! 598: # define OMAP24XX_DMA_MCBSP2_TX 33
! 599: # define OMAP24XX_DMA_MCBSP2_RX 34
! 600: # define OMAP24XX_DMA_SPI1_TX0 35
! 601: # define OMAP24XX_DMA_SPI1_RX0 36
! 602: # define OMAP24XX_DMA_SPI1_TX1 37
! 603: # define OMAP24XX_DMA_SPI1_RX1 38
! 604: # define OMAP24XX_DMA_SPI1_TX2 39
! 605: # define OMAP24XX_DMA_SPI1_RX2 40
! 606: # define OMAP24XX_DMA_SPI1_TX3 41
! 607: # define OMAP24XX_DMA_SPI1_RX3 42
! 608: # define OMAP24XX_DMA_SPI2_TX0 43
! 609: # define OMAP24XX_DMA_SPI2_RX0 44
! 610: # define OMAP24XX_DMA_SPI2_TX1 45
! 611: # define OMAP24XX_DMA_SPI2_RX1 46
! 612:
! 613: # define OMAP24XX_DMA_UART1_TX 49
! 614: # define OMAP24XX_DMA_UART1_RX 50
! 615: # define OMAP24XX_DMA_UART2_TX 51
! 616: # define OMAP24XX_DMA_UART2_RX 52
! 617: # define OMAP24XX_DMA_UART3_TX 53
! 618: # define OMAP24XX_DMA_UART3_RX 54
! 619: # define OMAP24XX_DMA_USB_W2FC_TX0 55
! 620: # define OMAP24XX_DMA_USB_W2FC_RX0 56
! 621: # define OMAP24XX_DMA_USB_W2FC_TX1 57
! 622: # define OMAP24XX_DMA_USB_W2FC_RX1 58
! 623: # define OMAP24XX_DMA_USB_W2FC_TX2 59
! 624: # define OMAP24XX_DMA_USB_W2FC_RX2 60
! 625: # define OMAP24XX_DMA_MMC1_TX 61
! 626: # define OMAP24XX_DMA_MMC1_RX 62
! 627: # define OMAP24XX_DMA_MS 63 /* Not in OMAP2420 */
! 628: # define OMAP24XX_DMA_EXT_DMAREQ5 64
! 629:
! 630: /* omap[123].c */
1.1 root 631: struct omap_mpu_timer_s;
632: struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
633: qemu_irq irq, omap_clk clk);
634:
1.1.1.2 ! root 635: struct omap_gp_timer_s;
! 636: struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta,
! 637: qemu_irq irq, omap_clk fclk, omap_clk iclk);
! 638:
1.1 root 639: struct omap_watchdog_timer_s;
640: struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
641: qemu_irq irq, omap_clk clk);
642:
643: struct omap_32khz_timer_s;
644: struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,
645: qemu_irq irq, omap_clk clk);
646:
1.1.1.2 ! root 647: void omap_synctimer_init(struct omap_target_agent_s *ta,
! 648: struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk);
! 649:
1.1 root 650: struct omap_tipb_bridge_s;
651: struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base,
652: qemu_irq abort_irq, omap_clk clk);
653:
654: struct omap_uart_s;
655: struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
1.1.1.2 ! root 656: qemu_irq irq, omap_clk fclk, omap_clk iclk,
! 657: qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr);
! 658: struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta,
! 659: qemu_irq irq, omap_clk fclk, omap_clk iclk,
! 660: qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr);
! 661: void omap_uart_reset(struct omap_uart_s *s);
! 662: void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr);
1.1 root 663:
664: struct omap_mpuio_s;
665: struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
666: qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
667: omap_clk clk);
668: qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s);
669: void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler);
670: void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down);
671:
672: struct omap_gpio_s;
673: struct omap_gpio_s *omap_gpio_init(target_phys_addr_t base,
674: qemu_irq irq, omap_clk clk);
675: qemu_irq *omap_gpio_in_get(struct omap_gpio_s *s);
676: void omap_gpio_out_set(struct omap_gpio_s *s, int line, qemu_irq handler);
677:
1.1.1.2 ! root 678: struct omap_gpif_s;
! 679: struct omap_gpif_s *omap2_gpio_init(struct omap_target_agent_s *ta,
! 680: qemu_irq *irq, omap_clk *fclk, omap_clk iclk, int modules);
! 681: qemu_irq *omap2_gpio_in_get(struct omap_gpif_s *s, int start);
! 682: void omap2_gpio_out_set(struct omap_gpif_s *s, int line, qemu_irq handler);
! 683:
1.1 root 684: struct uwire_slave_s {
685: uint16_t (*receive)(void *opaque);
686: void (*send)(void *opaque, uint16_t data);
687: void *opaque;
688: };
689: struct omap_uwire_s;
690: struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
691: qemu_irq *irq, qemu_irq dma, omap_clk clk);
692: void omap_uwire_attach(struct omap_uwire_s *s,
693: struct uwire_slave_s *slave, int chipselect);
694:
1.1.1.2 ! root 695: struct omap_mcspi_s;
! 696: struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
! 697: qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk);
! 698: void omap_mcspi_attach(struct omap_mcspi_s *s,
! 699: uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque,
! 700: int chipselect);
! 701:
1.1 root 702: struct omap_rtc_s;
703: struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,
704: qemu_irq *irq, omap_clk clk);
705:
706: struct i2s_codec_s {
707: void *opaque;
708:
709: /* The CPU can call this if it is generating the clock signal on the
710: * i2s port. The CODEC can ignore it if it is set up as a clock
711: * master and generates its own clock. */
712: void (*set_rate)(void *opaque, int in, int out);
713:
714: void (*tx_swallow)(void *opaque);
715: qemu_irq rx_swallow;
716: qemu_irq tx_start;
717:
718: int tx_rate;
719: int cts;
720: int rx_rate;
721: int rts;
722:
723: struct i2s_fifo_s {
724: uint8_t *fifo;
725: int len;
726: int start;
727: int size;
728: } in, out;
729: };
730: struct omap_mcbsp_s;
731: struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
732: qemu_irq *irq, qemu_irq *dma, omap_clk clk);
733: void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, struct i2s_codec_s *slave);
734:
735: struct omap_lpg_s;
736: struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk);
737:
1.1.1.2 ! root 738: void omap_tap_init(struct omap_target_agent_s *ta,
! 739: struct omap_mpu_state_s *mpu);
! 740:
! 741: struct omap_eac_s;
! 742: struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta,
! 743: qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk);
! 744:
1.1 root 745: /* omap_lcdc.c */
746: struct omap_lcd_panel_s;
747: void omap_lcdc_reset(struct omap_lcd_panel_s *s);
748: struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
1.1.1.2 ! root 749: struct omap_dma_lcd_channel_s *dma,
1.1 root 750: ram_addr_t imif_base, ram_addr_t emiff_base, omap_clk clk);
751:
1.1.1.2 ! root 752: /* omap_dss.c */
! 753: struct rfbi_chip_s {
! 754: void *opaque;
! 755: void (*write)(void *opaque, int dc, uint16_t value);
! 756: void (*block)(void *opaque, int dc, void *buf, size_t len, int pitch);
! 757: uint16_t (*read)(void *opaque, int dc);
! 758: };
! 759: struct omap_dss_s;
! 760: void omap_dss_reset(struct omap_dss_s *s);
! 761: struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
! 762: target_phys_addr_t l3_base,
! 763: qemu_irq irq, qemu_irq drq,
! 764: omap_clk fck1, omap_clk fck2, omap_clk ck54m,
! 765: omap_clk ick1, omap_clk ick2);
! 766: void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip);
! 767:
1.1 root 768: /* omap_mmc.c */
769: struct omap_mmc_s;
770: struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
771: BlockDriverState *bd,
772: qemu_irq irq, qemu_irq dma[], omap_clk clk);
1.1.1.2 ! root 773: struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,
! 774: BlockDriverState *bd, qemu_irq irq, qemu_irq dma[],
! 775: omap_clk fclk, omap_clk iclk);
1.1 root 776: void omap_mmc_reset(struct omap_mmc_s *s);
777: void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover);
1.1.1.2 ! root 778: void omap_mmc_enable(struct omap_mmc_s *s, int enable);
1.1 root 779:
780: /* omap_i2c.c */
781: struct omap_i2c_s;
782: struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
783: qemu_irq irq, qemu_irq *dma, omap_clk clk);
1.1.1.2 ! root 784: struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta,
! 785: qemu_irq irq, qemu_irq *dma, omap_clk fclk, omap_clk iclk);
1.1 root 786: void omap_i2c_reset(struct omap_i2c_s *s);
787: i2c_bus *omap_i2c_bus(struct omap_i2c_s *s);
788:
789: # define cpu_is_omap310(cpu) (cpu->mpu_model == omap310)
790: # define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510)
1.1.1.2 ! root 791: # define cpu_is_omap1610(cpu) (cpu->mpu_model == omap1610)
! 792: # define cpu_is_omap1710(cpu) (cpu->mpu_model == omap1710)
! 793: # define cpu_is_omap2410(cpu) (cpu->mpu_model == omap2410)
! 794: # define cpu_is_omap2420(cpu) (cpu->mpu_model == omap2420)
! 795: # define cpu_is_omap2430(cpu) (cpu->mpu_model == omap2430)
! 796: # define cpu_is_omap3430(cpu) (cpu->mpu_model == omap3430)
! 797:
1.1 root 798: # define cpu_is_omap15xx(cpu) \
799: (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu))
1.1.1.2 ! root 800: # define cpu_is_omap16xx(cpu) \
! 801: (cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu))
! 802: # define cpu_is_omap24xx(cpu) \
! 803: (cpu_is_omap2410(cpu) || cpu_is_omap2420(cpu) || cpu_is_omap2430(cpu))
! 804:
! 805: # define cpu_class_omap1(cpu) \
! 806: (cpu_is_omap15xx(cpu) || cpu_is_omap16xx(cpu))
! 807: # define cpu_class_omap2(cpu) cpu_is_omap24xx(cpu)
! 808: # define cpu_class_omap3(cpu) cpu_is_omap3430(cpu)
1.1 root 809:
810: struct omap_mpu_state_s {
1.1.1.2 ! root 811: enum omap_mpu_model {
1.1 root 812: omap310,
813: omap1510,
1.1.1.2 ! root 814: omap1610,
! 815: omap1710,
! 816: omap2410,
! 817: omap2420,
! 818: omap2422,
! 819: omap2423,
! 820: omap2430,
! 821: omap3430,
1.1 root 822: } mpu_model;
823:
824: CPUState *env;
825:
826: qemu_irq *irq[2];
827: qemu_irq *drq;
828:
829: qemu_irq wakeup;
830:
831: struct omap_dma_port_if_s {
832: uint32_t (*read[3])(struct omap_mpu_state_s *s,
833: target_phys_addr_t offset);
834: void (*write[3])(struct omap_mpu_state_s *s,
835: target_phys_addr_t offset, uint32_t value);
836: int (*addr_valid)(struct omap_mpu_state_s *s,
837: target_phys_addr_t addr);
1.1.1.2 ! root 838: } port[__omap_dma_port_last];
1.1 root 839:
840: unsigned long sdram_size;
841: unsigned long sram_size;
842:
843: /* MPUI-TIPB peripherals */
844: struct omap_uart_s *uart[3];
845:
846: struct omap_gpio_s *gpio;
847:
848: struct omap_mcbsp_s *mcbsp1;
849: struct omap_mcbsp_s *mcbsp3;
850:
851: /* MPU public TIPB peripherals */
852: struct omap_32khz_timer_s *os_timer;
853:
854: struct omap_mmc_s *mmc;
855:
856: struct omap_mpuio_s *mpuio;
857:
858: struct omap_uwire_s *microwire;
859:
860: struct {
861: uint8_t output;
862: uint8_t level;
863: uint8_t enable;
864: int clk;
865: } pwl;
866:
867: struct {
868: uint8_t frc;
869: uint8_t vrc;
870: uint8_t gcr;
871: omap_clk clk;
872: } pwt;
873:
1.1.1.2 ! root 874: struct omap_i2c_s *i2c[2];
1.1 root 875:
876: struct omap_rtc_s *rtc;
877:
878: struct omap_mcbsp_s *mcbsp2;
879:
880: struct omap_lpg_s *led[2];
881:
882: /* MPU private TIPB peripherals */
883: struct omap_intr_handler_s *ih[2];
884:
1.1.1.2 ! root 885: struct soc_dma_s *dma;
1.1 root 886:
887: struct omap_mpu_timer_s *timer[3];
888: struct omap_watchdog_timer_s *wdt;
889:
890: struct omap_lcd_panel_s *lcd;
891:
892: uint32_t ulpd_pm_regs[21];
893: int64_t ulpd_gauge_start;
894:
895: uint32_t func_mux_ctrl[14];
896: uint32_t comp_mode_ctrl[1];
897: uint32_t pull_dwn_ctrl[4];
898: uint32_t gate_inh_ctrl[1];
899: uint32_t voltage_ctrl[1];
900: uint32_t test_dbg_ctrl[1];
901: uint32_t mod_conf_ctrl[1];
902: int compat1509;
903:
904: uint32_t mpui_ctrl;
905:
906: struct omap_tipb_bridge_s *private_tipb;
907: struct omap_tipb_bridge_s *public_tipb;
908:
909: uint32_t tcmi_regs[17];
910:
911: struct dpll_ctl_s {
912: uint16_t mode;
913: omap_clk dpll;
914: } dpll[3];
915:
916: omap_clk clks;
917: struct {
918: int cold_start;
919: int clocking_scheme;
920: uint16_t arm_ckctl;
921: uint16_t arm_idlect1;
922: uint16_t arm_idlect2;
923: uint16_t arm_ewupct;
924: uint16_t arm_rstct1;
925: uint16_t arm_rstct2;
926: uint16_t arm_ckout1;
927: int dpll1_mode;
928: uint16_t dsp_idlect1;
929: uint16_t dsp_idlect2;
930: uint16_t dsp_rstct2;
931: } clkm;
1.1.1.2 ! root 932:
! 933: /* OMAP2-only peripherals */
! 934: struct omap_l4_s *l4;
! 935:
! 936: struct omap_gp_timer_s *gptimer[12];
! 937:
! 938: struct omap_synctimer_s {
! 939: uint32_t val;
! 940: uint16_t readh;
! 941: } synctimer;
! 942:
! 943: struct omap_prcm_s *prcm;
! 944: struct omap_sdrc_s *sdrc;
! 945: struct omap_gpmc_s *gpmc;
! 946: struct omap_sysctl_s *sysc;
! 947:
! 948: struct omap_gpif_s *gpif;
! 949:
! 950: struct omap_mcspi_s *mcspi[2];
! 951:
! 952: struct omap_dss_s *dss;
! 953:
! 954: struct omap_eac_s *eac;
! 955: };
! 956:
! 957: /* omap1.c */
! 958: struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
! 959: const char *core);
! 960:
! 961: /* omap2.c */
! 962: struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
! 963: const char *core);
1.1 root 964:
965: # if TARGET_PHYS_ADDR_BITS == 32
966: # define OMAP_FMT_plx "%#08x"
967: # elif TARGET_PHYS_ADDR_BITS == 64
968: # define OMAP_FMT_plx "%#08" PRIx64
969: # else
970: # error TARGET_PHYS_ADDR_BITS undefined
971: # endif
972:
973: uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr);
974: void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,
975: uint32_t value);
976: uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr);
977: void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
978: uint32_t value);
979: uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr);
980: void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
981: uint32_t value);
982:
1.1.1.2 ! root 983: void omap_mpu_wakeup(void *opaque, int irq, int req);
! 984:
1.1 root 985: # define OMAP_BAD_REG(paddr) \
1.1.1.2 ! root 986: fprintf(stderr, "%s: Bad register " OMAP_FMT_plx "\n", \
! 987: __FUNCTION__, paddr)
1.1 root 988: # define OMAP_RO_REG(paddr) \
1.1.1.2 ! root 989: fprintf(stderr, "%s: Read-only register " OMAP_FMT_plx "\n", \
1.1 root 990: __FUNCTION__, paddr)
991:
1.1.1.2 ! root 992: /* OMAP-specific Linux bootloader tags for the ATAG_BOARD area
! 993: (Board-specifc tags are not here) */
! 994: #define OMAP_TAG_CLOCK 0x4f01
! 995: #define OMAP_TAG_MMC 0x4f02
! 996: #define OMAP_TAG_SERIAL_CONSOLE 0x4f03
! 997: #define OMAP_TAG_USB 0x4f04
! 998: #define OMAP_TAG_LCD 0x4f05
! 999: #define OMAP_TAG_GPIO_SWITCH 0x4f06
! 1000: #define OMAP_TAG_UART 0x4f07
! 1001: #define OMAP_TAG_FBMEM 0x4f08
! 1002: #define OMAP_TAG_STI_CONSOLE 0x4f09
! 1003: #define OMAP_TAG_CAMERA_SENSOR 0x4f0a
! 1004: #define OMAP_TAG_PARTITION 0x4f0b
! 1005: #define OMAP_TAG_TEA5761 0x4f10
! 1006: #define OMAP_TAG_TMP105 0x4f11
! 1007: #define OMAP_TAG_BOOT_REASON 0x4f80
! 1008: #define OMAP_TAG_FLASH_PART_STR 0x4f81
! 1009: #define OMAP_TAG_VERSION_STR 0x4f82
! 1010:
! 1011: enum {
! 1012: OMAP_GPIOSW_TYPE_COVER = 0 << 4,
! 1013: OMAP_GPIOSW_TYPE_CONNECTION = 1 << 4,
! 1014: OMAP_GPIOSW_TYPE_ACTIVITY = 2 << 4,
! 1015: };
! 1016:
! 1017: #define OMAP_GPIOSW_INVERTED 0x0001
! 1018: #define OMAP_GPIOSW_OUTPUT 0x0002
! 1019:
1.1 root 1020: # define TCMI_VERBOSE 1
1021: //# define MEM_VERBOSE 1
1022:
1023: # ifdef TCMI_VERBOSE
1024: # define OMAP_8B_REG(paddr) \
1.1.1.2 ! root 1025: fprintf(stderr, "%s: 8-bit register " OMAP_FMT_plx "\n", \
1.1 root 1026: __FUNCTION__, paddr)
1027: # define OMAP_16B_REG(paddr) \
1.1.1.2 ! root 1028: fprintf(stderr, "%s: 16-bit register " OMAP_FMT_plx "\n", \
1.1 root 1029: __FUNCTION__, paddr)
1030: # define OMAP_32B_REG(paddr) \
1.1.1.2 ! root 1031: fprintf(stderr, "%s: 32-bit register " OMAP_FMT_plx "\n", \
1.1 root 1032: __FUNCTION__, paddr)
1033: # else
1034: # define OMAP_8B_REG(paddr)
1035: # define OMAP_16B_REG(paddr)
1036: # define OMAP_32B_REG(paddr)
1037: # endif
1038:
1039: # define OMAP_MPUI_REG_MASK 0x000007ff
1040:
1041: # ifdef MEM_VERBOSE
1042: struct io_fn {
1043: CPUReadMemoryFunc **mem_read;
1044: CPUWriteMemoryFunc **mem_write;
1045: void *opaque;
1046: int in;
1047: };
1048:
1049: static uint32_t io_readb(void *opaque, target_phys_addr_t addr)
1050: {
1051: struct io_fn *s = opaque;
1052: uint32_t ret;
1053:
1054: s->in ++;
1055: ret = s->mem_read[0](s->opaque, addr);
1056: s->in --;
1057: if (!s->in)
1058: fprintf(stderr, "%08x ---> %02x\n", (uint32_t) addr, ret);
1059: return ret;
1060: }
1061: static uint32_t io_readh(void *opaque, target_phys_addr_t addr)
1062: {
1063: struct io_fn *s = opaque;
1064: uint32_t ret;
1065:
1066: s->in ++;
1067: ret = s->mem_read[1](s->opaque, addr);
1068: s->in --;
1069: if (!s->in)
1070: fprintf(stderr, "%08x ---> %04x\n", (uint32_t) addr, ret);
1071: return ret;
1072: }
1073: static uint32_t io_readw(void *opaque, target_phys_addr_t addr)
1074: {
1075: struct io_fn *s = opaque;
1076: uint32_t ret;
1077:
1078: s->in ++;
1079: ret = s->mem_read[2](s->opaque, addr);
1080: s->in --;
1081: if (!s->in)
1082: fprintf(stderr, "%08x ---> %08x\n", (uint32_t) addr, ret);
1083: return ret;
1084: }
1085: static void io_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
1086: {
1087: struct io_fn *s = opaque;
1088:
1089: if (!s->in)
1090: fprintf(stderr, "%08x <--- %02x\n", (uint32_t) addr, value);
1091: s->in ++;
1092: s->mem_write[0](s->opaque, addr, value);
1093: s->in --;
1094: }
1095: static void io_writeh(void *opaque, target_phys_addr_t addr, uint32_t value)
1096: {
1097: struct io_fn *s = opaque;
1098:
1099: if (!s->in)
1100: fprintf(stderr, "%08x <--- %04x\n", (uint32_t) addr, value);
1101: s->in ++;
1102: s->mem_write[1](s->opaque, addr, value);
1103: s->in --;
1104: }
1105: static void io_writew(void *opaque, target_phys_addr_t addr, uint32_t value)
1106: {
1107: struct io_fn *s = opaque;
1108:
1109: if (!s->in)
1110: fprintf(stderr, "%08x <--- %08x\n", (uint32_t) addr, value);
1111: s->in ++;
1112: s->mem_write[2](s->opaque, addr, value);
1113: s->in --;
1114: }
1115:
1116: static CPUReadMemoryFunc *io_readfn[] = { io_readb, io_readh, io_readw, };
1117: static CPUWriteMemoryFunc *io_writefn[] = { io_writeb, io_writeh, io_writew, };
1118:
1119: inline static int debug_register_io_memory(int io_index,
1120: CPUReadMemoryFunc **mem_read, CPUWriteMemoryFunc **mem_write,
1121: void *opaque)
1122: {
1123: struct io_fn *s = qemu_malloc(sizeof(struct io_fn));
1124:
1125: s->mem_read = mem_read;
1126: s->mem_write = mem_write;
1127: s->opaque = opaque;
1128: s->in = 0;
1129: return cpu_register_io_memory(io_index, io_readfn, io_writefn, s);
1130: }
1131: # define cpu_register_io_memory debug_register_io_memory
1132: # endif
1133:
1.1.1.2 ! root 1134: /* Define when we want to reduce the number of IO regions registered. */
! 1135: /*# define L4_MUX_HACK*/
! 1136:
! 1137: # ifdef L4_MUX_HACK
! 1138: # undef l4_register_io_memory
! 1139: int l4_register_io_memory(int io_index, CPUReadMemoryFunc **mem_read,
! 1140: CPUWriteMemoryFunc **mem_write, void *opaque);
! 1141: # endif
1.1 root 1142:
1143: #endif /* hw_omap_h */
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