![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to omap.h CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [Qemu by Fabrice Bellard] / qemu / hw|
Return to omap.h CVS log | Up to [Qemu by Fabrice Bellard] / qemu / hw |
1.1 root 1: /*
2: * Texas Instruments OMAP processors.
3: *
1.1.1.2 root 4: * Copyright (C) 2006-2008 Andrzej Zaborowski <[email protected]>
1.1 root 5: *
6: * This program is free software; you can redistribute it and/or
7: * modify it under the terms of the GNU General Public License as
1.1.1.2 root 8: * published by the Free Software Foundation; either version 2 or
9: * (at your option) version 3 of the License.
1.1 root 10: *
11: * This program is distributed in the hope that it will be useful,
12: * but WITHOUT ANY WARRANTY; without even the implied warranty of
13: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14: * GNU General Public License for more details.
15: *
1.1.1.2 root 16: * You should have received a copy of the GNU General Public License along
1.1.1.3 root 17: * with this program; if not, see <http://www.gnu.org/licenses/>.
1.1 root 18: */
19: #ifndef hw_omap_h
20: # define hw_omap_h "omap.h"
21:
22: # define OMAP_EMIFS_BASE 0x00000000
1.1.1.2 root 23: # define OMAP2_Q0_BASE 0x00000000
1.1 root 24: # define OMAP_CS0_BASE 0x00000000
25: # define OMAP_CS1_BASE 0x04000000
26: # define OMAP_CS2_BASE 0x08000000
27: # define OMAP_CS3_BASE 0x0c000000
28: # define OMAP_EMIFF_BASE 0x10000000
29: # define OMAP_IMIF_BASE 0x20000000
30: # define OMAP_LOCALBUS_BASE 0x30000000
1.1.1.2 root 31: # define OMAP2_Q1_BASE 0x40000000
32: # define OMAP2_L4_BASE 0x48000000
33: # define OMAP2_SRAM_BASE 0x40200000
34: # define OMAP2_L3_BASE 0x68000000
35: # define OMAP2_Q2_BASE 0x80000000
36: # define OMAP2_Q3_BASE 0xc0000000
1.1 root 37: # define OMAP_MPUI_BASE 0xe1000000
38:
39: # define OMAP730_SRAM_SIZE 0x00032000
40: # define OMAP15XX_SRAM_SIZE 0x00030000
41: # define OMAP16XX_SRAM_SIZE 0x00004000
42: # define OMAP1611_SRAM_SIZE 0x0003e800
1.1.1.2 root 43: # define OMAP242X_SRAM_SIZE 0x000a0000
44: # define OMAP243X_SRAM_SIZE 0x00010000
1.1 root 45: # define OMAP_CS0_SIZE 0x04000000
46: # define OMAP_CS1_SIZE 0x04000000
47: # define OMAP_CS2_SIZE 0x04000000
48: # define OMAP_CS3_SIZE 0x04000000
49:
1.1.1.2 root 50: /* omap_clk.c */
1.1 root 51: struct omap_mpu_state_s;
52: typedef struct clk *omap_clk;
53: omap_clk omap_findclk(struct omap_mpu_state_s *mpu, const char *name);
54: void omap_clk_init(struct omap_mpu_state_s *mpu);
55: void omap_clk_adduser(struct clk *clk, qemu_irq user);
56: void omap_clk_get(omap_clk clk);
57: void omap_clk_put(omap_clk clk);
58: void omap_clk_onoff(omap_clk clk, int on);
59: void omap_clk_canidle(omap_clk clk, int can);
60: void omap_clk_setrate(omap_clk clk, int divide, int multiply);
61: int64_t omap_clk_getrate(omap_clk clk);
62: void omap_clk_reparent(omap_clk clk, omap_clk parent);
63:
1.1.1.5 root 64: /* OMAP2 l4 Interconnect */
1.1.1.2 root 65: struct omap_l4_s;
1.1.1.5 root 66: struct omap_l4_region_s {
67: target_phys_addr_t offset;
68: size_t size;
69: int access;
70: };
71: struct omap_l4_agent_info_s {
72: int ta;
73: int region;
74: int regions;
75: int ta_region;
76: };
77: struct omap_target_agent_s {
78: struct omap_l4_s *bus;
79: int regions;
80: const struct omap_l4_region_s *start;
81: target_phys_addr_t base;
82: uint32_t component;
83: uint32_t control;
84: uint32_t status;
85: };
1.1.1.2 root 86: struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num);
87:
88: struct omap_target_agent_s;
1.1.1.5 root 89: struct omap_target_agent_s *omap_l4ta_get(
90: struct omap_l4_s *bus,
91: const struct omap_l4_region_s *regions,
92: const struct omap_l4_agent_info_s *agents,
93: int cs);
1.1.1.2 root 94: target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region,
95: int iotype);
1.1.1.5 root 96: int l4_register_io_memory(CPUReadMemoryFunc * const *mem_read,
97: CPUWriteMemoryFunc * const *mem_write, void *opaque);
1.1.1.2 root 98:
1.1.1.5 root 99: /* OMAP interrupt controller */
1.1 root 100: struct omap_intr_handler_s;
101: struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
1.1.1.2 root 102: unsigned long size, unsigned char nbanks, qemu_irq **pins,
1.1 root 103: qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk);
1.1.1.2 root 104: struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base,
105: int size, int nbanks, qemu_irq **pins,
106: qemu_irq parent_irq, qemu_irq parent_fiq,
107: omap_clk fclk, omap_clk iclk);
108: void omap_inth_reset(struct omap_intr_handler_s *s);
1.1.1.5 root 109: qemu_irq omap_inth_get_pin(struct omap_intr_handler_s *s, int n);
1.1.1.2 root 110:
1.1.1.5 root 111: /* OMAP2 SDRAM controller */
1.1.1.2 root 112: struct omap_sdrc_s;
113: struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base);
1.1.1.5 root 114: void omap_sdrc_reset(struct omap_sdrc_s *s);
1.1.1.2 root 115:
1.1.1.5 root 116: /* OMAP2 general purpose memory controller */
1.1.1.2 root 117: struct omap_gpmc_s;
118: struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq);
1.1.1.5 root 119: void omap_gpmc_reset(struct omap_gpmc_s *s);
1.1.1.2 root 120: void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
121: void (*base_upd)(void *opaque, target_phys_addr_t new),
122: void (*unmap)(void *opaque), void *opaque);
1.1 root 123:
124: /*
125: * Common IRQ numbers for level 1 interrupt handler
126: * See /usr/include/asm-arm/arch-omap/irqs.h in Linux.
127: */
128: # define OMAP_INT_CAMERA 1
129: # define OMAP_INT_FIQ 3
130: # define OMAP_INT_RTDX 6
131: # define OMAP_INT_DSP_MMU_ABORT 7
132: # define OMAP_INT_HOST 8
133: # define OMAP_INT_ABORT 9
134: # define OMAP_INT_BRIDGE_PRIV 13
135: # define OMAP_INT_GPIO_BANK1 14
136: # define OMAP_INT_UART3 15
137: # define OMAP_INT_TIMER3 16
138: # define OMAP_INT_DMA_CH0_6 19
139: # define OMAP_INT_DMA_CH1_7 20
140: # define OMAP_INT_DMA_CH2_8 21
141: # define OMAP_INT_DMA_CH3 22
142: # define OMAP_INT_DMA_CH4 23
143: # define OMAP_INT_DMA_CH5 24
144: # define OMAP_INT_DMA_LCD 25
145: # define OMAP_INT_TIMER1 26
146: # define OMAP_INT_WD_TIMER 27
147: # define OMAP_INT_BRIDGE_PUB 28
148: # define OMAP_INT_TIMER2 30
149: # define OMAP_INT_LCD_CTRL 31
150:
151: /*
152: * Common OMAP-15xx IRQ numbers for level 1 interrupt handler
153: */
154: # define OMAP_INT_15XX_IH2_IRQ 0
155: # define OMAP_INT_15XX_LB_MMU 17
156: # define OMAP_INT_15XX_LOCAL_BUS 29
157:
158: /*
159: * OMAP-1510 specific IRQ numbers for level 1 interrupt handler
160: */
161: # define OMAP_INT_1510_SPI_TX 4
162: # define OMAP_INT_1510_SPI_RX 5
163: # define OMAP_INT_1510_DSP_MAILBOX1 10
164: # define OMAP_INT_1510_DSP_MAILBOX2 11
165:
166: /*
167: * OMAP-310 specific IRQ numbers for level 1 interrupt handler
168: */
169: # define OMAP_INT_310_McBSP2_TX 4
170: # define OMAP_INT_310_McBSP2_RX 5
171: # define OMAP_INT_310_HSB_MAILBOX1 12
172: # define OMAP_INT_310_HSAB_MMU 18
173:
174: /*
175: * OMAP-1610 specific IRQ numbers for level 1 interrupt handler
176: */
177: # define OMAP_INT_1610_IH2_IRQ 0
178: # define OMAP_INT_1610_IH2_FIQ 2
179: # define OMAP_INT_1610_McBSP2_TX 4
180: # define OMAP_INT_1610_McBSP2_RX 5
181: # define OMAP_INT_1610_DSP_MAILBOX1 10
182: # define OMAP_INT_1610_DSP_MAILBOX2 11
183: # define OMAP_INT_1610_LCD_LINE 12
184: # define OMAP_INT_1610_GPTIMER1 17
185: # define OMAP_INT_1610_GPTIMER2 18
186: # define OMAP_INT_1610_SSR_FIFO_0 29
187:
188: /*
189: * OMAP-730 specific IRQ numbers for level 1 interrupt handler
190: */
191: # define OMAP_INT_730_IH2_FIQ 0
192: # define OMAP_INT_730_IH2_IRQ 1
193: # define OMAP_INT_730_USB_NON_ISO 2
194: # define OMAP_INT_730_USB_ISO 3
195: # define OMAP_INT_730_ICR 4
196: # define OMAP_INT_730_EAC 5
197: # define OMAP_INT_730_GPIO_BANK1 6
198: # define OMAP_INT_730_GPIO_BANK2 7
199: # define OMAP_INT_730_GPIO_BANK3 8
200: # define OMAP_INT_730_McBSP2TX 10
201: # define OMAP_INT_730_McBSP2RX 11
202: # define OMAP_INT_730_McBSP2RX_OVF 12
203: # define OMAP_INT_730_LCD_LINE 14
204: # define OMAP_INT_730_GSM_PROTECT 15
205: # define OMAP_INT_730_TIMER3 16
206: # define OMAP_INT_730_GPIO_BANK5 17
207: # define OMAP_INT_730_GPIO_BANK6 18
208: # define OMAP_INT_730_SPGIO_WR 29
209:
210: /*
211: * Common IRQ numbers for level 2 interrupt handler
212: */
213: # define OMAP_INT_KEYBOARD 1
214: # define OMAP_INT_uWireTX 2
215: # define OMAP_INT_uWireRX 3
216: # define OMAP_INT_I2C 4
217: # define OMAP_INT_MPUIO 5
218: # define OMAP_INT_USB_HHC_1 6
219: # define OMAP_INT_McBSP3TX 10
220: # define OMAP_INT_McBSP3RX 11
221: # define OMAP_INT_McBSP1TX 12
222: # define OMAP_INT_McBSP1RX 13
223: # define OMAP_INT_UART1 14
224: # define OMAP_INT_UART2 15
225: # define OMAP_INT_USB_W2FC 20
226: # define OMAP_INT_1WIRE 21
227: # define OMAP_INT_OS_TIMER 22
228: # define OMAP_INT_OQN 23
229: # define OMAP_INT_GAUGE_32K 24
230: # define OMAP_INT_RTC_TIMER 25
231: # define OMAP_INT_RTC_ALARM 26
232: # define OMAP_INT_DSP_MMU 28
233:
234: /*
235: * OMAP-1510 specific IRQ numbers for level 2 interrupt handler
236: */
237: # define OMAP_INT_1510_BT_MCSI1TX 16
238: # define OMAP_INT_1510_BT_MCSI1RX 17
239: # define OMAP_INT_1510_SoSSI_MATCH 19
240: # define OMAP_INT_1510_MEM_STICK 27
241: # define OMAP_INT_1510_COM_SPI_RO 31
242:
243: /*
244: * OMAP-310 specific IRQ numbers for level 2 interrupt handler
245: */
246: # define OMAP_INT_310_FAC 0
247: # define OMAP_INT_310_USB_HHC_2 7
248: # define OMAP_INT_310_MCSI1_FE 16
249: # define OMAP_INT_310_MCSI2_FE 17
250: # define OMAP_INT_310_USB_W2FC_ISO 29
251: # define OMAP_INT_310_USB_W2FC_NON_ISO 30
252: # define OMAP_INT_310_McBSP2RX_OF 31
253:
254: /*
255: * OMAP-1610 specific IRQ numbers for level 2 interrupt handler
256: */
257: # define OMAP_INT_1610_FAC 0
258: # define OMAP_INT_1610_USB_HHC_2 7
259: # define OMAP_INT_1610_USB_OTG 8
260: # define OMAP_INT_1610_SoSSI 9
261: # define OMAP_INT_1610_BT_MCSI1TX 16
262: # define OMAP_INT_1610_BT_MCSI1RX 17
263: # define OMAP_INT_1610_SoSSI_MATCH 19
264: # define OMAP_INT_1610_MEM_STICK 27
265: # define OMAP_INT_1610_McBSP2RX_OF 31
266: # define OMAP_INT_1610_STI 32
267: # define OMAP_INT_1610_STI_WAKEUP 33
268: # define OMAP_INT_1610_GPTIMER3 34
269: # define OMAP_INT_1610_GPTIMER4 35
270: # define OMAP_INT_1610_GPTIMER5 36
271: # define OMAP_INT_1610_GPTIMER6 37
272: # define OMAP_INT_1610_GPTIMER7 38
273: # define OMAP_INT_1610_GPTIMER8 39
274: # define OMAP_INT_1610_GPIO_BANK2 40
275: # define OMAP_INT_1610_GPIO_BANK3 41
276: # define OMAP_INT_1610_MMC2 42
277: # define OMAP_INT_1610_CF 43
278: # define OMAP_INT_1610_WAKE_UP_REQ 46
279: # define OMAP_INT_1610_GPIO_BANK4 48
280: # define OMAP_INT_1610_SPI 49
281: # define OMAP_INT_1610_DMA_CH6 53
282: # define OMAP_INT_1610_DMA_CH7 54
283: # define OMAP_INT_1610_DMA_CH8 55
284: # define OMAP_INT_1610_DMA_CH9 56
285: # define OMAP_INT_1610_DMA_CH10 57
286: # define OMAP_INT_1610_DMA_CH11 58
287: # define OMAP_INT_1610_DMA_CH12 59
288: # define OMAP_INT_1610_DMA_CH13 60
289: # define OMAP_INT_1610_DMA_CH14 61
290: # define OMAP_INT_1610_DMA_CH15 62
291: # define OMAP_INT_1610_NAND 63
292:
293: /*
294: * OMAP-730 specific IRQ numbers for level 2 interrupt handler
295: */
296: # define OMAP_INT_730_HW_ERRORS 0
297: # define OMAP_INT_730_NFIQ_PWR_FAIL 1
298: # define OMAP_INT_730_CFCD 2
299: # define OMAP_INT_730_CFIREQ 3
300: # define OMAP_INT_730_I2C 4
301: # define OMAP_INT_730_PCC 5
302: # define OMAP_INT_730_MPU_EXT_NIRQ 6
303: # define OMAP_INT_730_SPI_100K_1 7
304: # define OMAP_INT_730_SYREN_SPI 8
305: # define OMAP_INT_730_VLYNQ 9
306: # define OMAP_INT_730_GPIO_BANK4 10
307: # define OMAP_INT_730_McBSP1TX 11
308: # define OMAP_INT_730_McBSP1RX 12
309: # define OMAP_INT_730_McBSP1RX_OF 13
310: # define OMAP_INT_730_UART_MODEM_IRDA_2 14
311: # define OMAP_INT_730_UART_MODEM_1 15
312: # define OMAP_INT_730_MCSI 16
313: # define OMAP_INT_730_uWireTX 17
314: # define OMAP_INT_730_uWireRX 18
315: # define OMAP_INT_730_SMC_CD 19
316: # define OMAP_INT_730_SMC_IREQ 20
317: # define OMAP_INT_730_HDQ_1WIRE 21
318: # define OMAP_INT_730_TIMER32K 22
319: # define OMAP_INT_730_MMC_SDIO 23
320: # define OMAP_INT_730_UPLD 24
321: # define OMAP_INT_730_USB_HHC_1 27
322: # define OMAP_INT_730_USB_HHC_2 28
323: # define OMAP_INT_730_USB_GENI 29
324: # define OMAP_INT_730_USB_OTG 30
325: # define OMAP_INT_730_CAMERA_IF 31
326: # define OMAP_INT_730_RNG 32
327: # define OMAP_INT_730_DUAL_MODE_TIMER 33
328: # define OMAP_INT_730_DBB_RF_EN 34
329: # define OMAP_INT_730_MPUIO_KEYPAD 35
330: # define OMAP_INT_730_SHA1_MD5 36
331: # define OMAP_INT_730_SPI_100K_2 37
332: # define OMAP_INT_730_RNG_IDLE 38
333: # define OMAP_INT_730_MPUIO 39
334: # define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40
335: # define OMAP_INT_730_LLPC_OE_FALLING 41
336: # define OMAP_INT_730_LLPC_OE_RISING 42
337: # define OMAP_INT_730_LLPC_VSYNC 43
338: # define OMAP_INT_730_WAKE_UP_REQ 46
339: # define OMAP_INT_730_DMA_CH6 53
340: # define OMAP_INT_730_DMA_CH7 54
341: # define OMAP_INT_730_DMA_CH8 55
342: # define OMAP_INT_730_DMA_CH9 56
343: # define OMAP_INT_730_DMA_CH10 57
344: # define OMAP_INT_730_DMA_CH11 58
345: # define OMAP_INT_730_DMA_CH12 59
346: # define OMAP_INT_730_DMA_CH13 60
347: # define OMAP_INT_730_DMA_CH14 61
348: # define OMAP_INT_730_DMA_CH15 62
349: # define OMAP_INT_730_NAND 63
350:
351: /*
352: * OMAP-24xx common IRQ numbers
353: */
1.1.1.2 root 354: # define OMAP_INT_24XX_STI 4
1.1 root 355: # define OMAP_INT_24XX_SYS_NIRQ 7
1.1.1.2 root 356: # define OMAP_INT_24XX_L3_IRQ 10
357: # define OMAP_INT_24XX_PRCM_MPU_IRQ 11
1.1 root 358: # define OMAP_INT_24XX_SDMA_IRQ0 12
359: # define OMAP_INT_24XX_SDMA_IRQ1 13
360: # define OMAP_INT_24XX_SDMA_IRQ2 14
361: # define OMAP_INT_24XX_SDMA_IRQ3 15
1.1.1.2 root 362: # define OMAP_INT_243X_MCBSP2_IRQ 16
363: # define OMAP_INT_243X_MCBSP3_IRQ 17
364: # define OMAP_INT_243X_MCBSP4_IRQ 18
365: # define OMAP_INT_243X_MCBSP5_IRQ 19
366: # define OMAP_INT_24XX_GPMC_IRQ 20
367: # define OMAP_INT_24XX_GUFFAW_IRQ 21
368: # define OMAP_INT_24XX_IVA_IRQ 22
369: # define OMAP_INT_24XX_EAC_IRQ 23
1.1 root 370: # define OMAP_INT_24XX_CAM_IRQ 24
371: # define OMAP_INT_24XX_DSS_IRQ 25
372: # define OMAP_INT_24XX_MAIL_U0_MPU 26
373: # define OMAP_INT_24XX_DSP_UMA 27
374: # define OMAP_INT_24XX_DSP_MMU 28
375: # define OMAP_INT_24XX_GPIO_BANK1 29
376: # define OMAP_INT_24XX_GPIO_BANK2 30
377: # define OMAP_INT_24XX_GPIO_BANK3 31
378: # define OMAP_INT_24XX_GPIO_BANK4 32
1.1.1.2 root 379: # define OMAP_INT_243X_GPIO_BANK5 33
1.1 root 380: # define OMAP_INT_24XX_MAIL_U3_MPU 34
1.1.1.2 root 381: # define OMAP_INT_24XX_WDT3 35
382: # define OMAP_INT_24XX_WDT4 36
1.1 root 383: # define OMAP_INT_24XX_GPTIMER1 37
384: # define OMAP_INT_24XX_GPTIMER2 38
385: # define OMAP_INT_24XX_GPTIMER3 39
386: # define OMAP_INT_24XX_GPTIMER4 40
387: # define OMAP_INT_24XX_GPTIMER5 41
388: # define OMAP_INT_24XX_GPTIMER6 42
389: # define OMAP_INT_24XX_GPTIMER7 43
390: # define OMAP_INT_24XX_GPTIMER8 44
391: # define OMAP_INT_24XX_GPTIMER9 45
392: # define OMAP_INT_24XX_GPTIMER10 46
393: # define OMAP_INT_24XX_GPTIMER11 47
394: # define OMAP_INT_24XX_GPTIMER12 48
1.1.1.2 root 395: # define OMAP_INT_24XX_PKA_IRQ 50
396: # define OMAP_INT_24XX_SHA1MD5_IRQ 51
397: # define OMAP_INT_24XX_RNG_IRQ 52
398: # define OMAP_INT_24XX_MG_IRQ 53
399: # define OMAP_INT_24XX_I2C1_IRQ 56
400: # define OMAP_INT_24XX_I2C2_IRQ 57
1.1 root 401: # define OMAP_INT_24XX_MCBSP1_IRQ_TX 59
402: # define OMAP_INT_24XX_MCBSP1_IRQ_RX 60
403: # define OMAP_INT_24XX_MCBSP2_IRQ_TX 62
404: # define OMAP_INT_24XX_MCBSP2_IRQ_RX 63
1.1.1.2 root 405: # define OMAP_INT_243X_MCBSP1_IRQ 64
406: # define OMAP_INT_24XX_MCSPI1_IRQ 65
407: # define OMAP_INT_24XX_MCSPI2_IRQ 66
408: # define OMAP_INT_24XX_SSI1_IRQ0 67
409: # define OMAP_INT_24XX_SSI1_IRQ1 68
410: # define OMAP_INT_24XX_SSI2_IRQ0 69
411: # define OMAP_INT_24XX_SSI2_IRQ1 70
412: # define OMAP_INT_24XX_SSI_GDD_IRQ 71
1.1 root 413: # define OMAP_INT_24XX_UART1_IRQ 72
414: # define OMAP_INT_24XX_UART2_IRQ 73
415: # define OMAP_INT_24XX_UART3_IRQ 74
416: # define OMAP_INT_24XX_USB_IRQ_GEN 75
417: # define OMAP_INT_24XX_USB_IRQ_NISO 76
418: # define OMAP_INT_24XX_USB_IRQ_ISO 77
419: # define OMAP_INT_24XX_USB_IRQ_HGEN 78
420: # define OMAP_INT_24XX_USB_IRQ_HSOF 79
421: # define OMAP_INT_24XX_USB_IRQ_OTG 80
1.1.1.2 root 422: # define OMAP_INT_24XX_VLYNQ_IRQ 81
1.1 root 423: # define OMAP_INT_24XX_MMC_IRQ 83
1.1.1.2 root 424: # define OMAP_INT_24XX_MS_IRQ 84
425: # define OMAP_INT_24XX_FAC_IRQ 85
426: # define OMAP_INT_24XX_MCSPI3_IRQ 91
1.1 root 427: # define OMAP_INT_243X_HS_USB_MC 92
428: # define OMAP_INT_243X_HS_USB_DMA 93
429: # define OMAP_INT_243X_CARKIT 94
1.1.1.2 root 430: # define OMAP_INT_34XX_GPTIMER12 95
1.1 root 431:
1.1.1.2 root 432: /* omap_dma.c */
1.1 root 433: enum omap_dma_model {
1.1.1.2 root 434: omap_dma_3_0,
435: omap_dma_3_1,
436: omap_dma_3_2,
437: omap_dma_4,
1.1 root 438: };
439:
1.1.1.2 root 440: struct soc_dma_s;
441: struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
1.1 root 442: qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
443: enum omap_dma_model model);
1.1.1.2 root 444: struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
445: struct omap_mpu_state_s *mpu, int fifo,
446: int chans, omap_clk iclk, omap_clk fclk);
447: void omap_dma_reset(struct soc_dma_s *s);
448:
449: struct dma_irq_map {
450: int ih;
451: int intr;
452: };
1.1 root 453:
1.1.1.2 root 454: /* Only used in OMAP DMA 3.x gigacells */
1.1 root 455: enum omap_dma_port {
456: emiff = 0,
457: emifs,
458: imif, /* omap16xx: ocp_t1 */
459: tipb,
460: local, /* omap16xx: ocp_t2 */
461: tipb_mpui,
1.1.1.2 root 462: __omap_dma_port_last,
1.1 root 463: };
464:
465: typedef enum {
466: constant = 0,
467: post_incremented,
468: single_index,
469: double_index,
470: } omap_dma_addressing_t;
471:
1.1.1.2 root 472: /* Only used in OMAP DMA 3.x gigacells */
1.1 root 473: struct omap_dma_lcd_channel_s {
474: enum omap_dma_port src;
475: target_phys_addr_t src_f1_top;
476: target_phys_addr_t src_f1_bottom;
477: target_phys_addr_t src_f2_top;
478: target_phys_addr_t src_f2_bottom;
479:
480: /* Used in OMAP DMA 3.2 gigacell */
481: unsigned char brust_f1;
482: unsigned char pack_f1;
483: unsigned char data_type_f1;
484: unsigned char brust_f2;
485: unsigned char pack_f2;
486: unsigned char data_type_f2;
487: unsigned char end_prog;
488: unsigned char repeat;
489: unsigned char auto_init;
490: unsigned char priority;
491: unsigned char fs;
492: unsigned char running;
493: unsigned char bs;
494: unsigned char omap_3_1_compatible_disable;
495: unsigned char dst;
496: unsigned char lch_type;
497: int16_t element_index_f1;
498: int16_t element_index_f2;
499: int32_t frame_index_f1;
500: int32_t frame_index_f2;
501: uint16_t elements_f1;
502: uint16_t frames_f1;
503: uint16_t elements_f2;
504: uint16_t frames_f2;
505: omap_dma_addressing_t mode_f1;
506: omap_dma_addressing_t mode_f2;
507:
508: /* Destination port is fixed. */
509: int interrupts;
510: int condition;
511: int dual;
512:
513: int current_frame;
1.1.1.3 root 514: target_phys_addr_t phys_framebuffer[2];
1.1 root 515: qemu_irq irq;
516: struct omap_mpu_state_s *mpu;
1.1.1.2 root 517: } *omap_dma_get_lcdch(struct soc_dma_s *s);
1.1 root 518:
519: /*
520: * DMA request numbers for OMAP1
521: * See /usr/include/asm-arm/arch-omap/dma.h in Linux.
522: */
523: # define OMAP_DMA_NO_DEVICE 0
524: # define OMAP_DMA_MCSI1_TX 1
525: # define OMAP_DMA_MCSI1_RX 2
526: # define OMAP_DMA_I2C_RX 3
527: # define OMAP_DMA_I2C_TX 4
528: # define OMAP_DMA_EXT_NDMA_REQ0 5
529: # define OMAP_DMA_EXT_NDMA_REQ1 6
530: # define OMAP_DMA_UWIRE_TX 7
531: # define OMAP_DMA_MCBSP1_TX 8
532: # define OMAP_DMA_MCBSP1_RX 9
533: # define OMAP_DMA_MCBSP3_TX 10
534: # define OMAP_DMA_MCBSP3_RX 11
535: # define OMAP_DMA_UART1_TX 12
536: # define OMAP_DMA_UART1_RX 13
537: # define OMAP_DMA_UART2_TX 14
538: # define OMAP_DMA_UART2_RX 15
539: # define OMAP_DMA_MCBSP2_TX 16
540: # define OMAP_DMA_MCBSP2_RX 17
541: # define OMAP_DMA_UART3_TX 18
542: # define OMAP_DMA_UART3_RX 19
543: # define OMAP_DMA_CAMERA_IF_RX 20
544: # define OMAP_DMA_MMC_TX 21
545: # define OMAP_DMA_MMC_RX 22
546: # define OMAP_DMA_NAND 23 /* Not in OMAP310 */
547: # define OMAP_DMA_IRQ_LCD_LINE 24 /* Not in OMAP310 */
548: # define OMAP_DMA_MEMORY_STICK 25 /* Not in OMAP310 */
549: # define OMAP_DMA_USB_W2FC_RX0 26
550: # define OMAP_DMA_USB_W2FC_RX1 27
551: # define OMAP_DMA_USB_W2FC_RX2 28
552: # define OMAP_DMA_USB_W2FC_TX0 29
553: # define OMAP_DMA_USB_W2FC_TX1 30
554: # define OMAP_DMA_USB_W2FC_TX2 31
555:
556: /* These are only for 1610 */
557: # define OMAP_DMA_CRYPTO_DES_IN 32
558: # define OMAP_DMA_SPI_TX 33
559: # define OMAP_DMA_SPI_RX 34
560: # define OMAP_DMA_CRYPTO_HASH 35
561: # define OMAP_DMA_CCP_ATTN 36
562: # define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37
563: # define OMAP_DMA_CMT_APE_TX_CHAN_0 38
564: # define OMAP_DMA_CMT_APE_RV_CHAN_0 39
565: # define OMAP_DMA_CMT_APE_TX_CHAN_1 40
566: # define OMAP_DMA_CMT_APE_RV_CHAN_1 41
567: # define OMAP_DMA_CMT_APE_TX_CHAN_2 42
568: # define OMAP_DMA_CMT_APE_RV_CHAN_2 43
569: # define OMAP_DMA_CMT_APE_TX_CHAN_3 44
570: # define OMAP_DMA_CMT_APE_RV_CHAN_3 45
571: # define OMAP_DMA_CMT_APE_TX_CHAN_4 46
572: # define OMAP_DMA_CMT_APE_RV_CHAN_4 47
573: # define OMAP_DMA_CMT_APE_TX_CHAN_5 48
574: # define OMAP_DMA_CMT_APE_RV_CHAN_5 49
575: # define OMAP_DMA_CMT_APE_TX_CHAN_6 50
576: # define OMAP_DMA_CMT_APE_RV_CHAN_6 51
577: # define OMAP_DMA_CMT_APE_TX_CHAN_7 52
578: # define OMAP_DMA_CMT_APE_RV_CHAN_7 53
579: # define OMAP_DMA_MMC2_TX 54
580: # define OMAP_DMA_MMC2_RX 55
581: # define OMAP_DMA_CRYPTO_DES_OUT 56
582:
1.1.1.2 root 583: /*
584: * DMA request numbers for the OMAP2
585: */
586: # define OMAP24XX_DMA_NO_DEVICE 0
587: # define OMAP24XX_DMA_XTI_DMA 1 /* Not in OMAP2420 */
588: # define OMAP24XX_DMA_EXT_DMAREQ0 2
589: # define OMAP24XX_DMA_EXT_DMAREQ1 3
590: # define OMAP24XX_DMA_GPMC 4
591: # define OMAP24XX_DMA_GFX 5 /* Not in OMAP2420 */
592: # define OMAP24XX_DMA_DSS 6
593: # define OMAP24XX_DMA_VLYNQ_TX 7 /* Not in OMAP2420 */
594: # define OMAP24XX_DMA_CWT 8 /* Not in OMAP2420 */
595: # define OMAP24XX_DMA_AES_TX 9 /* Not in OMAP2420 */
596: # define OMAP24XX_DMA_AES_RX 10 /* Not in OMAP2420 */
597: # define OMAP24XX_DMA_DES_TX 11 /* Not in OMAP2420 */
598: # define OMAP24XX_DMA_DES_RX 12 /* Not in OMAP2420 */
599: # define OMAP24XX_DMA_SHA1MD5_RX 13 /* Not in OMAP2420 */
600: # define OMAP24XX_DMA_EXT_DMAREQ2 14
601: # define OMAP24XX_DMA_EXT_DMAREQ3 15
602: # define OMAP24XX_DMA_EXT_DMAREQ4 16
603: # define OMAP24XX_DMA_EAC_AC_RD 17
604: # define OMAP24XX_DMA_EAC_AC_WR 18
605: # define OMAP24XX_DMA_EAC_MD_UL_RD 19
606: # define OMAP24XX_DMA_EAC_MD_UL_WR 20
607: # define OMAP24XX_DMA_EAC_MD_DL_RD 21
608: # define OMAP24XX_DMA_EAC_MD_DL_WR 22
609: # define OMAP24XX_DMA_EAC_BT_UL_RD 23
610: # define OMAP24XX_DMA_EAC_BT_UL_WR 24
611: # define OMAP24XX_DMA_EAC_BT_DL_RD 25
612: # define OMAP24XX_DMA_EAC_BT_DL_WR 26
613: # define OMAP24XX_DMA_I2C1_TX 27
614: # define OMAP24XX_DMA_I2C1_RX 28
615: # define OMAP24XX_DMA_I2C2_TX 29
616: # define OMAP24XX_DMA_I2C2_RX 30
617: # define OMAP24XX_DMA_MCBSP1_TX 31
618: # define OMAP24XX_DMA_MCBSP1_RX 32
619: # define OMAP24XX_DMA_MCBSP2_TX 33
620: # define OMAP24XX_DMA_MCBSP2_RX 34
621: # define OMAP24XX_DMA_SPI1_TX0 35
622: # define OMAP24XX_DMA_SPI1_RX0 36
623: # define OMAP24XX_DMA_SPI1_TX1 37
624: # define OMAP24XX_DMA_SPI1_RX1 38
625: # define OMAP24XX_DMA_SPI1_TX2 39
626: # define OMAP24XX_DMA_SPI1_RX2 40
627: # define OMAP24XX_DMA_SPI1_TX3 41
628: # define OMAP24XX_DMA_SPI1_RX3 42
629: # define OMAP24XX_DMA_SPI2_TX0 43
630: # define OMAP24XX_DMA_SPI2_RX0 44
631: # define OMAP24XX_DMA_SPI2_TX1 45
632: # define OMAP24XX_DMA_SPI2_RX1 46
633:
634: # define OMAP24XX_DMA_UART1_TX 49
635: # define OMAP24XX_DMA_UART1_RX 50
636: # define OMAP24XX_DMA_UART2_TX 51
637: # define OMAP24XX_DMA_UART2_RX 52
638: # define OMAP24XX_DMA_UART3_TX 53
639: # define OMAP24XX_DMA_UART3_RX 54
640: # define OMAP24XX_DMA_USB_W2FC_TX0 55
641: # define OMAP24XX_DMA_USB_W2FC_RX0 56
642: # define OMAP24XX_DMA_USB_W2FC_TX1 57
643: # define OMAP24XX_DMA_USB_W2FC_RX1 58
644: # define OMAP24XX_DMA_USB_W2FC_TX2 59
645: # define OMAP24XX_DMA_USB_W2FC_RX2 60
646: # define OMAP24XX_DMA_MMC1_TX 61
647: # define OMAP24XX_DMA_MMC1_RX 62
648: # define OMAP24XX_DMA_MS 63 /* Not in OMAP2420 */
649: # define OMAP24XX_DMA_EXT_DMAREQ5 64
650:
651: /* omap[123].c */
1.1.1.5 root 652: /* OMAP2 gp timer */
1.1.1.2 root 653: struct omap_gp_timer_s;
654: struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta,
655: qemu_irq irq, omap_clk fclk, omap_clk iclk);
1.1.1.5 root 656: void omap_gp_timer_reset(struct omap_gp_timer_s *s);
1.1.1.2 root 657:
1.1.1.5 root 658: /* OMAP2 sysctimer */
659: struct omap_synctimer_s;
660: struct omap_synctimer_s *omap_synctimer_init(struct omap_target_agent_s *ta,
1.1.1.2 root 661: struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk);
1.1.1.5 root 662: void omap_synctimer_reset(struct omap_synctimer_s *s);
1.1 root 663:
664: struct omap_uart_s;
665: struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
1.1.1.2 root 666: qemu_irq irq, omap_clk fclk, omap_clk iclk,
1.1.1.6 ! root 667: qemu_irq txdma, qemu_irq rxdma,
! 668: const char *label, CharDriverState *chr);
1.1.1.2 root 669: struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta,
670: qemu_irq irq, omap_clk fclk, omap_clk iclk,
1.1.1.6 ! root 671: qemu_irq txdma, qemu_irq rxdma,
! 672: const char *label, CharDriverState *chr);
1.1.1.2 root 673: void omap_uart_reset(struct omap_uart_s *s);
674: void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr);
1.1 root 675:
676: struct omap_mpuio_s;
677: struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,
678: qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
679: omap_clk clk);
680: qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s);
681: void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler);
682: void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down);
683:
1.1.1.5 root 684: /* omap1 gpio module interface */
1.1 root 685: struct omap_gpio_s;
686: struct omap_gpio_s *omap_gpio_init(target_phys_addr_t base,
687: qemu_irq irq, omap_clk clk);
1.1.1.5 root 688: void omap_gpio_reset(struct omap_gpio_s *s);
1.1 root 689: qemu_irq *omap_gpio_in_get(struct omap_gpio_s *s);
690: void omap_gpio_out_set(struct omap_gpio_s *s, int line, qemu_irq handler);
691:
1.1.1.5 root 692: /* omap2 gpio interface */
1.1.1.2 root 693: struct omap_gpif_s;
694: struct omap_gpif_s *omap2_gpio_init(struct omap_target_agent_s *ta,
695: qemu_irq *irq, omap_clk *fclk, omap_clk iclk, int modules);
1.1.1.5 root 696: void omap_gpif_reset(struct omap_gpif_s *s);
1.1.1.2 root 697: qemu_irq *omap2_gpio_in_get(struct omap_gpif_s *s, int start);
698: void omap2_gpio_out_set(struct omap_gpif_s *s, int line, qemu_irq handler);
699:
1.1.1.3 root 700: struct uWireSlave {
1.1 root 701: uint16_t (*receive)(void *opaque);
702: void (*send)(void *opaque, uint16_t data);
703: void *opaque;
704: };
705: struct omap_uwire_s;
706: struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,
707: qemu_irq *irq, qemu_irq dma, omap_clk clk);
708: void omap_uwire_attach(struct omap_uwire_s *s,
1.1.1.3 root 709: uWireSlave *slave, int chipselect);
1.1 root 710:
1.1.1.5 root 711: /* OMAP2 spi */
1.1.1.2 root 712: struct omap_mcspi_s;
713: struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
714: qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk);
715: void omap_mcspi_attach(struct omap_mcspi_s *s,
716: uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque,
717: int chipselect);
1.1.1.5 root 718: void omap_mcspi_reset(struct omap_mcspi_s *s);
1.1 root 719:
1.1.1.3 root 720: struct I2SCodec {
1.1 root 721: void *opaque;
722:
723: /* The CPU can call this if it is generating the clock signal on the
724: * i2s port. The CODEC can ignore it if it is set up as a clock
725: * master and generates its own clock. */
726: void (*set_rate)(void *opaque, int in, int out);
727:
728: void (*tx_swallow)(void *opaque);
729: qemu_irq rx_swallow;
730: qemu_irq tx_start;
731:
732: int tx_rate;
733: int cts;
734: int rx_rate;
735: int rts;
736:
737: struct i2s_fifo_s {
738: uint8_t *fifo;
739: int len;
740: int start;
741: int size;
742: } in, out;
743: };
744: struct omap_mcbsp_s;
745: struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
746: qemu_irq *irq, qemu_irq *dma, omap_clk clk);
1.1.1.3 root 747: void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave);
1.1 root 748:
1.1.1.2 root 749: void omap_tap_init(struct omap_target_agent_s *ta,
750: struct omap_mpu_state_s *mpu);
751:
1.1 root 752: /* omap_lcdc.c */
753: struct omap_lcd_panel_s;
754: void omap_lcdc_reset(struct omap_lcd_panel_s *s);
755: struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
1.1.1.2 root 756: struct omap_dma_lcd_channel_s *dma,
1.1 root 757: ram_addr_t imif_base, ram_addr_t emiff_base, omap_clk clk);
758:
1.1.1.2 root 759: /* omap_dss.c */
760: struct rfbi_chip_s {
761: void *opaque;
762: void (*write)(void *opaque, int dc, uint16_t value);
763: void (*block)(void *opaque, int dc, void *buf, size_t len, int pitch);
764: uint16_t (*read)(void *opaque, int dc);
765: };
766: struct omap_dss_s;
767: void omap_dss_reset(struct omap_dss_s *s);
768: struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
769: target_phys_addr_t l3_base,
770: qemu_irq irq, qemu_irq drq,
771: omap_clk fck1, omap_clk fck2, omap_clk ck54m,
772: omap_clk ick1, omap_clk ick2);
773: void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip);
774:
1.1 root 775: /* omap_mmc.c */
776: struct omap_mmc_s;
777: struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
778: BlockDriverState *bd,
779: qemu_irq irq, qemu_irq dma[], omap_clk clk);
1.1.1.2 root 780: struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,
781: BlockDriverState *bd, qemu_irq irq, qemu_irq dma[],
782: omap_clk fclk, omap_clk iclk);
1.1 root 783: void omap_mmc_reset(struct omap_mmc_s *s);
784: void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover);
1.1.1.2 root 785: void omap_mmc_enable(struct omap_mmc_s *s, int enable);
1.1 root 786:
787: /* omap_i2c.c */
788: struct omap_i2c_s;
789: struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
790: qemu_irq irq, qemu_irq *dma, omap_clk clk);
1.1.1.2 root 791: struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta,
792: qemu_irq irq, qemu_irq *dma, omap_clk fclk, omap_clk iclk);
1.1 root 793: void omap_i2c_reset(struct omap_i2c_s *s);
794: i2c_bus *omap_i2c_bus(struct omap_i2c_s *s);
795:
796: # define cpu_is_omap310(cpu) (cpu->mpu_model == omap310)
797: # define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510)
1.1.1.2 root 798: # define cpu_is_omap1610(cpu) (cpu->mpu_model == omap1610)
799: # define cpu_is_omap1710(cpu) (cpu->mpu_model == omap1710)
800: # define cpu_is_omap2410(cpu) (cpu->mpu_model == omap2410)
801: # define cpu_is_omap2420(cpu) (cpu->mpu_model == omap2420)
802: # define cpu_is_omap2430(cpu) (cpu->mpu_model == omap2430)
803: # define cpu_is_omap3430(cpu) (cpu->mpu_model == omap3430)
804:
1.1 root 805: # define cpu_is_omap15xx(cpu) \
806: (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu))
1.1.1.2 root 807: # define cpu_is_omap16xx(cpu) \
808: (cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu))
809: # define cpu_is_omap24xx(cpu) \
810: (cpu_is_omap2410(cpu) || cpu_is_omap2420(cpu) || cpu_is_omap2430(cpu))
811:
812: # define cpu_class_omap1(cpu) \
813: (cpu_is_omap15xx(cpu) || cpu_is_omap16xx(cpu))
814: # define cpu_class_omap2(cpu) cpu_is_omap24xx(cpu)
815: # define cpu_class_omap3(cpu) cpu_is_omap3430(cpu)
1.1 root 816:
817: struct omap_mpu_state_s {
1.1.1.2 root 818: enum omap_mpu_model {
1.1 root 819: omap310,
820: omap1510,
1.1.1.2 root 821: omap1610,
822: omap1710,
823: omap2410,
824: omap2420,
825: omap2422,
826: omap2423,
827: omap2430,
828: omap3430,
1.1 root 829: } mpu_model;
830:
831: CPUState *env;
832:
833: qemu_irq *irq[2];
834: qemu_irq *drq;
835:
836: qemu_irq wakeup;
837:
838: struct omap_dma_port_if_s {
839: uint32_t (*read[3])(struct omap_mpu_state_s *s,
840: target_phys_addr_t offset);
841: void (*write[3])(struct omap_mpu_state_s *s,
842: target_phys_addr_t offset, uint32_t value);
843: int (*addr_valid)(struct omap_mpu_state_s *s,
844: target_phys_addr_t addr);
1.1.1.2 root 845: } port[__omap_dma_port_last];
1.1 root 846:
847: unsigned long sdram_size;
848: unsigned long sram_size;
849:
850: /* MPUI-TIPB peripherals */
851: struct omap_uart_s *uart[3];
852:
853: struct omap_gpio_s *gpio;
854:
855: struct omap_mcbsp_s *mcbsp1;
856: struct omap_mcbsp_s *mcbsp3;
857:
858: /* MPU public TIPB peripherals */
859: struct omap_32khz_timer_s *os_timer;
860:
861: struct omap_mmc_s *mmc;
862:
863: struct omap_mpuio_s *mpuio;
864:
865: struct omap_uwire_s *microwire;
866:
867: struct {
868: uint8_t output;
869: uint8_t level;
870: uint8_t enable;
871: int clk;
872: } pwl;
873:
874: struct {
875: uint8_t frc;
876: uint8_t vrc;
877: uint8_t gcr;
878: omap_clk clk;
879: } pwt;
880:
1.1.1.2 root 881: struct omap_i2c_s *i2c[2];
1.1 root 882:
883: struct omap_rtc_s *rtc;
884:
885: struct omap_mcbsp_s *mcbsp2;
886:
887: struct omap_lpg_s *led[2];
888:
889: /* MPU private TIPB peripherals */
890: struct omap_intr_handler_s *ih[2];
891:
1.1.1.2 root 892: struct soc_dma_s *dma;
1.1 root 893:
894: struct omap_mpu_timer_s *timer[3];
895: struct omap_watchdog_timer_s *wdt;
896:
897: struct omap_lcd_panel_s *lcd;
898:
899: uint32_t ulpd_pm_regs[21];
900: int64_t ulpd_gauge_start;
901:
902: uint32_t func_mux_ctrl[14];
903: uint32_t comp_mode_ctrl[1];
904: uint32_t pull_dwn_ctrl[4];
905: uint32_t gate_inh_ctrl[1];
906: uint32_t voltage_ctrl[1];
907: uint32_t test_dbg_ctrl[1];
908: uint32_t mod_conf_ctrl[1];
909: int compat1509;
910:
911: uint32_t mpui_ctrl;
912:
913: struct omap_tipb_bridge_s *private_tipb;
914: struct omap_tipb_bridge_s *public_tipb;
915:
916: uint32_t tcmi_regs[17];
917:
918: struct dpll_ctl_s {
919: uint16_t mode;
920: omap_clk dpll;
921: } dpll[3];
922:
923: omap_clk clks;
924: struct {
925: int cold_start;
926: int clocking_scheme;
927: uint16_t arm_ckctl;
928: uint16_t arm_idlect1;
929: uint16_t arm_idlect2;
930: uint16_t arm_ewupct;
931: uint16_t arm_rstct1;
932: uint16_t arm_rstct2;
933: uint16_t arm_ckout1;
934: int dpll1_mode;
935: uint16_t dsp_idlect1;
936: uint16_t dsp_idlect2;
937: uint16_t dsp_rstct2;
938: } clkm;
1.1.1.2 root 939:
940: /* OMAP2-only peripherals */
941: struct omap_l4_s *l4;
942:
943: struct omap_gp_timer_s *gptimer[12];
1.1.1.5 root 944: struct omap_synctimer_s *synctimer;
1.1.1.2 root 945:
946: struct omap_prcm_s *prcm;
947: struct omap_sdrc_s *sdrc;
948: struct omap_gpmc_s *gpmc;
949: struct omap_sysctl_s *sysc;
950:
951: struct omap_gpif_s *gpif;
952:
953: struct omap_mcspi_s *mcspi[2];
954:
955: struct omap_dss_s *dss;
956:
957: struct omap_eac_s *eac;
958: };
959:
960: /* omap1.c */
961: struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
962: const char *core);
963:
964: /* omap2.c */
965: struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
966: const char *core);
1.1 root 967:
968: # if TARGET_PHYS_ADDR_BITS == 32
969: # define OMAP_FMT_plx "%#08x"
970: # elif TARGET_PHYS_ADDR_BITS == 64
971: # define OMAP_FMT_plx "%#08" PRIx64
972: # else
973: # error TARGET_PHYS_ADDR_BITS undefined
974: # endif
975:
976: uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr);
977: void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,
978: uint32_t value);
979: uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr);
980: void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
981: uint32_t value);
982: uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr);
983: void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
984: uint32_t value);
985:
1.1.1.2 root 986: void omap_mpu_wakeup(void *opaque, int irq, int req);
987:
1.1 root 988: # define OMAP_BAD_REG(paddr) \
1.1.1.2 root 989: fprintf(stderr, "%s: Bad register " OMAP_FMT_plx "\n", \
990: __FUNCTION__, paddr)
1.1 root 991: # define OMAP_RO_REG(paddr) \
1.1.1.2 root 992: fprintf(stderr, "%s: Read-only register " OMAP_FMT_plx "\n", \
1.1 root 993: __FUNCTION__, paddr)
994:
1.1.1.2 root 995: /* OMAP-specific Linux bootloader tags for the ATAG_BOARD area
996: (Board-specifc tags are not here) */
997: #define OMAP_TAG_CLOCK 0x4f01
998: #define OMAP_TAG_MMC 0x4f02
999: #define OMAP_TAG_SERIAL_CONSOLE 0x4f03
1000: #define OMAP_TAG_USB 0x4f04
1001: #define OMAP_TAG_LCD 0x4f05
1002: #define OMAP_TAG_GPIO_SWITCH 0x4f06
1003: #define OMAP_TAG_UART 0x4f07
1004: #define OMAP_TAG_FBMEM 0x4f08
1005: #define OMAP_TAG_STI_CONSOLE 0x4f09
1006: #define OMAP_TAG_CAMERA_SENSOR 0x4f0a
1007: #define OMAP_TAG_PARTITION 0x4f0b
1008: #define OMAP_TAG_TEA5761 0x4f10
1009: #define OMAP_TAG_TMP105 0x4f11
1010: #define OMAP_TAG_BOOT_REASON 0x4f80
1011: #define OMAP_TAG_FLASH_PART_STR 0x4f81
1012: #define OMAP_TAG_VERSION_STR 0x4f82
1013:
1014: enum {
1015: OMAP_GPIOSW_TYPE_COVER = 0 << 4,
1016: OMAP_GPIOSW_TYPE_CONNECTION = 1 << 4,
1017: OMAP_GPIOSW_TYPE_ACTIVITY = 2 << 4,
1018: };
1019:
1020: #define OMAP_GPIOSW_INVERTED 0x0001
1021: #define OMAP_GPIOSW_OUTPUT 0x0002
1022:
1.1 root 1023: # define TCMI_VERBOSE 1
1024: //# define MEM_VERBOSE 1
1025:
1026: # ifdef TCMI_VERBOSE
1027: # define OMAP_8B_REG(paddr) \
1.1.1.2 root 1028: fprintf(stderr, "%s: 8-bit register " OMAP_FMT_plx "\n", \
1.1 root 1029: __FUNCTION__, paddr)
1030: # define OMAP_16B_REG(paddr) \
1.1.1.2 root 1031: fprintf(stderr, "%s: 16-bit register " OMAP_FMT_plx "\n", \
1.1 root 1032: __FUNCTION__, paddr)
1033: # define OMAP_32B_REG(paddr) \
1.1.1.2 root 1034: fprintf(stderr, "%s: 32-bit register " OMAP_FMT_plx "\n", \
1.1 root 1035: __FUNCTION__, paddr)
1036: # else
1037: # define OMAP_8B_REG(paddr)
1038: # define OMAP_16B_REG(paddr)
1039: # define OMAP_32B_REG(paddr)
1040: # endif
1041:
1042: # define OMAP_MPUI_REG_MASK 0x000007ff
1043:
1044: # ifdef MEM_VERBOSE
1045: struct io_fn {
1.1.1.4 root 1046: CPUReadMemoryFunc * const *mem_read;
1047: CPUWriteMemoryFunc * const *mem_write;
1.1 root 1048: void *opaque;
1049: int in;
1050: };
1051:
1052: static uint32_t io_readb(void *opaque, target_phys_addr_t addr)
1053: {
1054: struct io_fn *s = opaque;
1055: uint32_t ret;
1056:
1057: s->in ++;
1058: ret = s->mem_read[0](s->opaque, addr);
1059: s->in --;
1060: if (!s->in)
1061: fprintf(stderr, "%08x ---> %02x\n", (uint32_t) addr, ret);
1062: return ret;
1063: }
1064: static uint32_t io_readh(void *opaque, target_phys_addr_t addr)
1065: {
1066: struct io_fn *s = opaque;
1067: uint32_t ret;
1068:
1069: s->in ++;
1070: ret = s->mem_read[1](s->opaque, addr);
1071: s->in --;
1072: if (!s->in)
1073: fprintf(stderr, "%08x ---> %04x\n", (uint32_t) addr, ret);
1074: return ret;
1075: }
1076: static uint32_t io_readw(void *opaque, target_phys_addr_t addr)
1077: {
1078: struct io_fn *s = opaque;
1079: uint32_t ret;
1080:
1081: s->in ++;
1082: ret = s->mem_read[2](s->opaque, addr);
1083: s->in --;
1084: if (!s->in)
1085: fprintf(stderr, "%08x ---> %08x\n", (uint32_t) addr, ret);
1086: return ret;
1087: }
1088: static void io_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
1089: {
1090: struct io_fn *s = opaque;
1091:
1092: if (!s->in)
1093: fprintf(stderr, "%08x <--- %02x\n", (uint32_t) addr, value);
1094: s->in ++;
1095: s->mem_write[0](s->opaque, addr, value);
1096: s->in --;
1097: }
1098: static void io_writeh(void *opaque, target_phys_addr_t addr, uint32_t value)
1099: {
1100: struct io_fn *s = opaque;
1101:
1102: if (!s->in)
1103: fprintf(stderr, "%08x <--- %04x\n", (uint32_t) addr, value);
1104: s->in ++;
1105: s->mem_write[1](s->opaque, addr, value);
1106: s->in --;
1107: }
1108: static void io_writew(void *opaque, target_phys_addr_t addr, uint32_t value)
1109: {
1110: struct io_fn *s = opaque;
1111:
1112: if (!s->in)
1113: fprintf(stderr, "%08x <--- %08x\n", (uint32_t) addr, value);
1114: s->in ++;
1115: s->mem_write[2](s->opaque, addr, value);
1116: s->in --;
1117: }
1118:
1.1.1.4 root 1119: static CPUReadMemoryFunc * const io_readfn[] = { io_readb, io_readh, io_readw, };
1120: static CPUWriteMemoryFunc * const io_writefn[] = { io_writeb, io_writeh, io_writew, };
1.1 root 1121:
1.1.1.4 root 1122: inline static int debug_register_io_memory(CPUReadMemoryFunc * const *mem_read,
1123: CPUWriteMemoryFunc * const *mem_write,
1124: void *opaque)
1.1 root 1125: {
1126: struct io_fn *s = qemu_malloc(sizeof(struct io_fn));
1127:
1128: s->mem_read = mem_read;
1129: s->mem_write = mem_write;
1130: s->opaque = opaque;
1131: s->in = 0;
1.1.1.6 ! root 1132: return cpu_register_io_memory(io_readfn, io_writefn, s,
! 1133: DEVICE_NATIVE_ENDIAN);
1.1 root 1134: }
1135: # define cpu_register_io_memory debug_register_io_memory
1136: # endif
1137:
1.1.1.2 root 1138: /* Define when we want to reduce the number of IO regions registered. */
1139: /*# define L4_MUX_HACK*/
1140:
1.1 root 1141: #endif /* hw_omap_h */
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.